MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c

   1 /** @file
   2   Cache Maintenance Functions.
   3
   4   Copyright (c) 2006 - 2008, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include <Base.h>
  16 #include <Library/CacheMaintenanceLib.h>
  17 #include <Library/BaseLib.h>
  18 #include <Library/DebugLib.h>
  19 #include <Library/PalLib.h>
  20
  21 /**
  22   Invalidates the entire instruction cache in cache coherency domain of the
  23   calling CPU.
  24
  25 **/
  26 VOID
  27 EFIAPI
  28 InvalidateInstructionCache (
  29   VOID
  30   )
  31 {
  32   PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
  33 }
  34
  35 /**
  36   Invalidates a range of instruction cache lines in the cache coherency domain
  37   of the calling CPU.
  38
  39   Invalidates the instruction cache lines specified by Address and Length. If
  40   Address is not aligned on a cache line boundary, then entire instruction
  41   cache line containing Address is invalidated. If Address + Length is not
  42   aligned on a cache line boundary, then the entire instruction cache line
  43   containing Address + Length -1 is invalidated. This function may choose to
  44   invalidate the entire instruction cache if that is more efficient than
  45   invalidating the specified range. If Length is 0, the no instruction cache
  46   lines are invalidated. Address is returned.
  47
  48   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  49
  50   @param  Address The base address of the instruction cache lines to
  51                   invalidate. If the CPU is in a physical addressing mode, then
  52                   Address is a physical address. If the CPU is in a virtual
  53                   addressing mode, then Address is a virtual address.
  54
  55   @param  Length  The number of bytes to invalidate from the instruction cache.
  56
  57   @return Address.
  58
  59 **/
  60 VOID *
  61 EFIAPI
  62 InvalidateInstructionCacheRange (
  63   IN      VOID                      *Address,
  64   IN      UINTN                     Length
  65   )
  66 {
  67   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
  68   return AsmFlushCacheRange (Address, Length);
  69 }
  70
  71 /**
  72   Writes Back and Invalidates the entire data cache in cache coherency domain
  73   of the calling CPU.
  74
  75   Writes Back and Invalidates the entire data cache in cache coherency domain
  76   of the calling CPU. This function guarantees that all dirty cache lines are
  77   written back to system memory, and also invalidates all the data cache lines
  78   in the cache coherency domain of the calling CPU.
  79
  80 **/
  81 VOID
  82 EFIAPI
  83 WriteBackInvalidateDataCache (
  84   VOID
  85   )
  86 {
  87   PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
  88 }
  89
  90 /**
  91   Writes Back and Invalidates a range of data cache lines in the cache
  92   coherency domain of the calling CPU.
  93
  94   Writes Back and Invalidate the data cache lines specified by Address and
  95   Length. If Address is not aligned on a cache line boundary, then entire data
  96   cache line containing Address is written back and invalidated. If Address +
  97   Length is not aligned on a cache line boundary, then the entire data cache
  98   line containing Address + Length -1 is written back and invalidated. This
  99   function may choose to write back and invalidate the entire data cache if
 100   that is more efficient than writing back and invalidating the specified
 101   range. If Length is 0, the no data cache lines are written back and
 102   invalidated. Address is returned.
 103
 104   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 105
 106   @param  Address The base address of the data cache lines to write back and
 107                   invalidate. If the CPU is in a physical addressing mode, then
 108                   Address is a physical address. If the CPU is in a virtual
 109                   addressing mode, then Address is a virtual address.
 110   @param  Length  The number of bytes to write back and invalidate from the
 111                   data cache.
 112
 113   @return Address of cache invalidation.
 114
 115 **/
 116 VOID *
 117 EFIAPI
 118 WriteBackInvalidateDataCacheRange (
 119   IN      VOID                      *Address,
 120   IN      UINTN                     Length
 121   )
 122 {
 123   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 124
 125   return AsmFlushCacheRange (Address, Length);
 126 }
 127
 128 /**
 129   Writes Back the entire data cache in cache coherency domain of the calling
 130   CPU.
 131
 132   Writes Back the entire data cache in cache coherency domain of the calling
 133   CPU. This function guarantees that all dirty cache lines are written back to
 134   system memory. This function may also invalidate all the data cache lines in
 135   the cache coherency domain of the calling CPU.
 136
 137 **/
 138 VOID
 139 EFIAPI
 140 WriteBackDataCache (
 141   VOID
 142   )
 143 {
 144   PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_NO_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
 145 }
 146
 147 /**
 148   Writes Back a range of data cache lines in the cache coherency domain of the
 149   calling CPU.
 150
 151   Writes Back the data cache lines specified by Address and Length. If Address
 152   is not aligned on a cache line boundary, then entire data cache line
 153   containing Address is written back. If Address + Length is not aligned on a
 154   cache line boundary, then the entire data cache line containing Address +
 155   Length -1 is written back. This function may choose to write back the entire
 156   data cache if that is more efficient than writing back the specified range.
 157   If Length is 0, the no data cache lines are written back. This function may
 158   also invalidate all the data cache lines in the specified range of the cache
 159   coherency domain of the calling CPU. Address is returned.
 160
 161   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 162
 163   @param  Address The base address of the data cache lines to write back. If
 164                   the CPU is in a physical addressing mode, then Address is a
 165                   physical address. If the CPU is in a virtual addressing
 166                   mode, then Address is a virtual address.
 167   @param  Length  The number of bytes to write back from the data cache.
 168
 169   @return Address of cache written in main memory.
 170
 171 **/
 172 VOID *
 173 EFIAPI
 174 WriteBackDataCacheRange (
 175   IN      VOID                      *Address,
 176   IN      UINTN                     Length
 177   )
 178 {
 179   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 180
 181   return AsmFlushCacheRange (Address, Length);
 182 }
 183
 184 /**
 185   Invalidates the entire data cache in cache coherency domain of the calling
 186   CPU.
 187
 188   Invalidates the entire data cache in cache coherency domain of the calling
 189   CPU. This function must be used with care because dirty cache lines are not
 190   written back to system memory. It is typically used for cache diagnostics. If
 191   the CPU does not support invalidation of the entire data cache, then a write
 192   back and invalidate operation should be performed on the entire data cache.
 193
 194 **/
 195 VOID
 196 EFIAPI
 197 InvalidateDataCache (
 198   VOID
 199   )
 200 {
 201   //
 202   // Invalidation of entire data cache without writing back is not supported on
 203   // IPF architecture, so write back and invalidate operation is performed.
 204   //
 205   WriteBackInvalidateDataCache ();
 206 }
 207
 208 /**
 209   Invalidates a range of data cache lines in the cache coherency domain of the
 210   calling CPU.
 211
 212   Invalidates the data cache lines specified by Address and Length. If Address
 213   is not aligned on a cache line boundary, then entire data cache line
 214   containing Address is invalidated. If Address + Length is not aligned on a
 215   cache line boundary, then the entire data cache line containing Address +
 216   Length -1 is invalidated. This function must never invalidate any cache lines
 217   outside the specified range. If Length is 0, the no data cache lines are
 218   invalidated. Address is returned. This function must be used with care
 219   because dirty cache lines are not written back to system memory. It is
 220   typically used for cache diagnostics. If the CPU does not support
 221   invalidation of a data cache range, then a write back and invalidate
 222   operation should be performed on the data cache range.
 223
 224   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 225
 226   @param  Address The base address of the data cache lines to invalidate. If
 227                   the CPU is in a physical addressing mode, then Address is a
 228                   physical address. If the CPU is in a virtual addressing mode,
 229                   then Address is a virtual address.
 230   @param  Length  The number of bytes to invalidate from the data cache.
 231
 232   @return Address.
 233
 234 **/
 235 VOID *
 236 EFIAPI
 237 InvalidateDataCacheRange (
 238   IN      VOID                      *Address,
 239   IN      UINTN                     Length
 240   )
 241 {
 242   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 243   //
 244   // Invalidation of a data cache range without writing back is not supported on
 245   // IPF architecture, so write back and invalidate operation is performed.
 246   //
 247   return AsmFlushCacheRange (Address, Length);
 248 }