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git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
2 Cache Maintenance Functions.
4 Copyright (c) 2006, Intel Corporation<BR>
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 // Include common header file for this module.
20 #include <Library/BaseLib.h>
21 #include <Library/DebugLib.h>
24 Invalidates the entire instruction cache in cache coherency domain of the
27 Invalidates the entire instruction cache in cache coherency domain of the
33 InvalidateInstructionCache (
37 PalCallStatic (NULL
, 1, 1, 1, 0);
41 Invalidates a range of instruction cache lines in the cache coherency domain
44 Invalidates the instruction cache lines specified by Address and Length. If
45 Address is not aligned on a cache line boundary, then entire instruction
46 cache line containing Address is invalidated. If Address + Length is not
47 aligned on a cache line boundary, then the entire instruction cache line
48 containing Address + Length -1 is invalidated. This function may choose to
49 invalidate the entire instruction cache if that is more efficient than
50 invalidating the specified range. If Length is 0, the no instruction cache
51 lines are invalidated. Address is returned.
53 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
55 @param Address The base address of the instruction cache lines to
56 invalidate. If the CPU is in a physical addressing mode, then
57 Address is a physical address. If the CPU is in a virtual
58 addressing mode, then Address is a virtual address.
60 @param Length The number of bytes to invalidate from the instruction cache.
67 InvalidateInstructionCacheRange (
72 return IpfFlushCacheRange (Address
, Length
);
76 Writes Back and Invalidates the entire data cache in cache coherency domain
79 Writes Back and Invalidates the entire data cache in cache coherency domain
80 of the calling CPU. This function guarantees that all dirty cache lines are
81 written back to system memory, and also invalidates all the data cache lines
82 in the cache coherency domain of the calling CPU.
87 WriteBackInvalidateDataCache (
91 PalCallStatic (NULL
, 1, 2, 1, 0);
95 Writes Back and Invalidates a range of data cache lines in the cache
96 coherency domain of the calling CPU.
98 Writes Back and Invalidate the data cache lines specified by Address and
99 Length. If Address is not aligned on a cache line boundary, then entire data
100 cache line containing Address is written back and invalidated. If Address +
101 Length is not aligned on a cache line boundary, then the entire data cache
102 line containing Address + Length -1 is written back and invalidated. This
103 function may choose to write back and invalidate the entire data cache if
104 that is more efficient than writing back and invalidating the specified
105 range. If Length is 0, the no data cache lines are written back and
106 invalidated. Address is returned.
108 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
110 @param Address The base address of the data cache lines to write back and
111 invalidate. If the CPU is in a physical addressing mode, then
112 Address is a physical address. If the CPU is in a virtual
113 addressing mode, then Address is a virtual address.
114 @param Length The number of bytes to write back and invalidate from the
122 WriteBackInvalidateDataCacheRange (
127 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);
129 return IpfFlushCacheRange (Address
, Length
);
133 Writes Back the entire data cache in cache coherency domain of the calling
136 Writes Back the entire data cache in cache coherency domain of the calling
137 CPU. This function guarantees that all dirty cache lines are written back to
138 system memory. This function may also invalidate all the data cache lines in
139 the cache coherency domain of the calling CPU.
148 PalCallStatic (NULL
, 1, 2, 0, 0);
152 Writes Back a range of data cache lines in the cache coherency domain of the
155 Writes Back the data cache lines specified by Address and Length. If Address
156 is not aligned on a cache line boundary, then entire data cache line
157 containing Address is written back. If Address + Length is not aligned on a
158 cache line boundary, then the entire data cache line containing Address +
159 Length -1 is written back. This function may choose to write back the entire
160 data cache if that is more efficient than writing back the specified range.
161 If Length is 0, the no data cache lines are written back. This function may
162 also invalidate all the data cache lines in the specified range of the cache
163 coherency domain of the calling CPU. Address is returned.
165 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
167 @param Address The base address of the data cache lines to write back. If
168 the CPU is in a physical addressing mode, then Address is a
169 physical address. If the CPU is in a virtual addressing
170 mode, then Address is a virtual address.
171 @param Length The number of bytes to write back from the data cache.
178 WriteBackDataCacheRange (
183 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);
185 return IpfFlushCacheRange (Address
, Length
);
189 Invalidates the entire data cache in cache coherency domain of the calling
192 Invalidates the entire data cache in cache coherency domain of the calling
193 CPU. This function must be used with care because dirty cache lines are not
194 written back to system memory. It is typically used for cache diagnostics. If
195 the CPU does not support invalidation of the entire data cache, then a write
196 back and invalidate operation should be performed on the entire data cache.
201 InvalidateDataCache (
205 WriteBackInvalidateDataCache ();
209 Invalidates a range of data cache lines in the cache coherency domain of the
212 Invalidates the data cache lines specified by Address and Length. If Address
213 is not aligned on a cache line boundary, then entire data cache line
214 containing Address is invalidated. If Address + Length is not aligned on a
215 cache line boundary, then the entire data cache line containing Address +
216 Length -1 is invalidated. This function must never invalidate any cache lines
217 outside the specified range. If Length is 0, the no data cache lines are
218 invalidated. Address is returned. This function must be used with care
219 because dirty cache lines are not written back to system memory. It is
220 typically used for cache diagnostics. If the CPU does not support
221 invalidation of a data cache range, then a write back and invalidate
222 operation should be performed on the data cache range.
224 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
226 @param Address The base address of the data cache lines to invalidate. If
227 the CPU is in a physical addressing mode, then Address is a
228 physical address. If the CPU is in a virtual addressing mode,
229 then Address is a virtual address.
230 @param Length The number of bytes to invalidate from the data cache.
237 InvalidateDataCacheRange (
242 return IpfFlushCacheRange (Address
, Length
);