MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c

   1 /** @file
   2   Cache Maintenance Functions for LoongArch.
   3   LoongArch cache maintenance functions has not yet been completed, and will added in later.
   4   Functions are null functions now.
   5
   6   Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
   7
   8   SPDX-License-Identifier: BSD-2-Clause-Patent
   9
  10 **/
  11
  12 //
  13 // Include common header file for this module.
  14 //
  15 #include <Base.h>
  16 #include <Library/BaseLib.h>
  17 #include <Library/DebugLib.h>
  18
  19 /**
  20   LoongArch data barrier operation.
  21 **/
  22 VOID
  23 EFIAPI
  24 AsmDataBarrierLoongArch (
  25   VOID
  26   );
  27
  28 /**
  29   LoongArch instruction barrier operation.
  30 **/
  31 VOID
  32 EFIAPI
  33 AsmInstructionBarrierLoongArch (
  34   VOID
  35   );
  36
  37 /**
  38   Invalidates the entire instruction cache in cache coherency domain of the
  39   calling CPU.
  40
  41 **/
  42 VOID
  43 EFIAPI
  44 InvalidateInstructionCache (
  45   VOID
  46   )
  47 {
  48   AsmInstructionBarrierLoongArch ();
  49 }
  50
  51 /**
  52   Invalidates a range of instruction cache lines in the cache coherency domain
  53   of the calling CPU.
  54
  55   Invalidates the instruction cache lines specified by Address and Length. If
  56   Address is not aligned on a cache line boundary, then entire instruction
  57   cache line containing Address is invalidated. If Address + Length is not
  58   aligned on a cache line boundary, then the entire instruction cache line
  59   containing Address + Length -1 is invalidated. This function may choose to
  60   invalidate the entire instruction cache if that is more efficient than
  61   invalidating the specified range. If Length is 0, the no instruction cache
  62   lines are invalidated. Address is returned.
  63
  64   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  65
  66   @param[in]  Address The base address of the instruction cache lines to
  67                   invalidate. If the CPU is in a physical addressing mode, then
  68                   Address is a physical address. If the CPU is in a virtual
  69                   addressing mode, then Address is a virtual address.
  70
  71   @param[in]  Length  The number of bytes to invalidate from the instruction cache.
  72
  73   @return Address.
  74
  75 **/
  76 VOID *
  77 EFIAPI
  78 InvalidateInstructionCacheRange (
  79   IN       VOID   *Address,
  80   IN       UINTN  Length
  81   )
  82 {
  83   AsmInstructionBarrierLoongArch ();
  84   return Address;
  85 }
  86
  87 /**
  88   Writes Back and Invalidates the entire data cache in cache coherency domain
  89   of the calling CPU.
  90
  91   Writes Back and Invalidates the entire data cache in cache coherency domain
  92   of the calling CPU. This function guarantees that all dirty cache lines are
  93   written back to system memory, and also invalidates all the data cache lines
  94   in the cache coherency domain of the calling CPU.
  95
  96 **/
  97 VOID
  98 EFIAPI
  99 WriteBackInvalidateDataCache (
 100   VOID
 101   )
 102 {
 103   DEBUG ((DEBUG_ERROR, "%a: Not currently implemented on LoongArch.\n", __FUNCTION__));
 104 }
 105
 106 /**
 107   Writes Back and Invalidates a range of data cache lines in the cache
 108   coherency domain of the calling CPU.
 109
 110   Writes Back and Invalidate the data cache lines specified by Address and
 111   Length. If Address is not aligned on a cache line boundary, then entire data
 112   cache line containing Address is written back and invalidated. If Address +
 113   Length is not aligned on a cache line boundary, then the entire data cache
 114   line containing Address + Length -1 is written back and invalidated. This
 115   function may choose to write back and invalidate the entire data cache if
 116   that is more efficient than writing back and invalidating the specified
 117   range. If Length is 0, the no data cache lines are written back and
 118   invalidated. Address is returned.
 119
 120   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 121
 122   @param[in]  Address The base address of the data cache lines to write back and
 123                   invalidate. If the CPU is in a physical addressing mode, then
 124                   Address is a physical address. If the CPU is in a virtual
 125                   addressing mode, then Address is a virtual address.
 126   @param[in]  Length  The number of bytes to write back and invalidate from the
 127                   data cache.
 128
 129   @return Address of cache invalidation.
 130
 131 **/
 132 VOID *
 133 EFIAPI
 134 WriteBackInvalidateDataCacheRange (
 135   IN      VOID   *Address,
 136   IN      UINTN  Length
 137   )
 138 {
 139   DEBUG ((DEBUG_ERROR, "%a: Not currently implemented on LoongArch.\n", __FUNCTION__));
 140   return Address;
 141 }
 142
 143 /**
 144   Writes Back the entire data cache in cache coherency domain of the calling
 145   CPU.
 146
 147   Writes Back the entire data cache in cache coherency domain of the calling
 148   CPU. This function guarantees that all dirty cache lines are written back to
 149   system memory. This function may also invalidate all the data cache lines in
 150   the cache coherency domain of the calling CPU.
 151
 152 **/
 153 VOID
 154 EFIAPI
 155 WriteBackDataCache (
 156   VOID
 157   )
 158 {
 159   WriteBackInvalidateDataCache ();
 160 }
 161
 162 /**
 163   Writes Back a range of data cache lines in the cache coherency domain of the
 164   calling CPU.
 165
 166   Writes Back the data cache lines specified by Address and Length. If Address
 167   is not aligned on a cache line boundary, then entire data cache line
 168   containing Address is written back. If Address + Length is not aligned on a
 169   cache line boundary, then the entire data cache line containing Address +
 170   Length -1 is written back. This function may choose to write back the entire
 171   data cache if that is more efficient than writing back the specified range.
 172   If Length is 0, the no data cache lines are written back. This function may
 173   also invalidate all the data cache lines in the specified range of the cache
 174   coherency domain of the calling CPU. Address is returned.
 175
 176   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 177
 178   @param[in]  Address The base address of the data cache lines to write back. If
 179                   the CPU is in a physical addressing mode, then Address is a
 180                   physical address. If the CPU is in a virtual addressing
 181                   mode, then Address is a virtual address.
 182   @param[in]  Length  The number of bytes to write back from the data cache.
 183
 184   @return Address of cache written in main memory.
 185
 186 **/
 187 VOID *
 188 EFIAPI
 189 WriteBackDataCacheRange (
 190   IN      VOID   *Address,
 191   IN      UINTN  Length
 192   )
 193 {
 194   DEBUG ((DEBUG_ERROR, "%a: Not currently implemented on LoongArch.\n", __FUNCTION__));
 195   return Address;
 196 }
 197
 198 /**
 199   Invalidates the entire data cache in cache coherency domain of the calling
 200   CPU.
 201
 202   Invalidates the entire data cache in cache coherency domain of the calling
 203   CPU. This function must be used with care because dirty cache lines are not
 204   written back to system memory. It is typically used for cache diagnostics. If
 205   the CPU does not support invalidation of the entire data cache, then a write
 206   back and invalidate operation should be performed on the entire data cache.
 207
 208 **/
 209 VOID
 210 EFIAPI
 211 InvalidateDataCache (
 212   VOID
 213   )
 214 {
 215   AsmDataBarrierLoongArch ();
 216 }
 217
 218 /**
 219   Invalidates a range of data cache lines in the cache coherency domain of the
 220   calling CPU.
 221
 222   Invalidates the data cache lines specified by Address and Length. If Address
 223   is not aligned on a cache line boundary, then entire data cache line
 224   containing Address is invalidated. If Address + Length is not aligned on a
 225   cache line boundary, then the entire data cache line containing Address +
 226   Length -1 is invalidated. This function must never invalidate any cache lines
 227   outside the specified range. If Length is 0, the no data cache lines are
 228   invalidated. Address is returned. This function must be used with care
 229   because dirty cache lines are not written back to system memory. It is
 230   typically used for cache diagnostics. If the CPU does not support
 231   invalidation of a data cache range, then a write back and invalidate
 232   operation should be performed on the data cache range.
 233
 234   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 235
 236   @param[in]  Address The base address of the data cache lines to invalidate. If
 237                   the CPU is in a physical addressing mode, then Address is a
 238                   physical address. If the CPU is in a virtual addressing mode,
 239                   then Address is a virtual address.
 240   @param[in]  Length  The number of bytes to invalidate from the data cache.
 241
 242   @return Address.
 243
 244 **/
 245 VOID *
 246 EFIAPI
 247 InvalidateDataCacheRange (
 248   IN      VOID   *Address,
 249   IN      UINTN  Length
 250   )
 251 {
 252   AsmDataBarrierLoongArch ();
 253   return Address;
 254 }