MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c

   1 /** @file
   2   RISC-V specific functionality for cache.
   3
   4   Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
   5
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7 **/
   8
   9 #include <Base.h>
  10 #include <Library/BaseLib.h>
  11 #include <Library/DebugLib.h>
  12
  13 /**
  14   RISC-V invalidate instruction cache.
  15
  16 **/
  17 VOID
  18 EFIAPI
  19 RiscVInvalidateInstCacheAsm (
  20   VOID
  21   );
  22
  23 /**
  24   RISC-V invalidate data cache.
  25
  26 **/
  27 VOID
  28 EFIAPI
  29 RiscVInvalidateDataCacheAsm (
  30   VOID
  31   );
  32
  33 /**
  34   Invalidates the entire instruction cache in cache coherency domain of the
  35   calling CPU.
  36
  37 **/
  38 VOID
  39 EFIAPI
  40 InvalidateInstructionCache (
  41   VOID
  42   )
  43 {
  44   RiscVInvalidateInstCacheAsm ();
  45 }
  46
  47 /**
  48   Invalidates a range of instruction cache lines in the cache coherency domain
  49   of the calling CPU.
  50
  51   Invalidates the instruction cache lines specified by Address and Length. If
  52   Address is not aligned on a cache line boundary, then entire instruction
  53   cache line containing Address is invalidated. If Address + Length is not
  54   aligned on a cache line boundary, then the entire instruction cache line
  55   containing Address + Length -1 is invalidated. This function may choose to
  56   invalidate the entire instruction cache if that is more efficient than
  57   invalidating the specified range. If Length is 0, then no instruction cache
  58   lines are invalidated. Address is returned.
  59
  60   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  61
  62   @param  Address The base address of the instruction cache lines to
  63                   invalidate. If the CPU is in a physical addressing mode, then
  64                   Address is a physical address. If the CPU is in a virtual
  65                   addressing mode, then Address is a virtual address.
  66
  67   @param  Length  The number of bytes to invalidate from the instruction cache.
  68
  69   @return Address.
  70
  71 **/
  72 VOID *
  73 EFIAPI
  74 InvalidateInstructionCacheRange (
  75   IN VOID   *Address,
  76   IN UINTN  Length
  77   )
  78 {
  79   DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
  80   return Address;
  81 }
  82
  83 /**
  84   Writes back and invalidates the entire data cache in cache coherency domain
  85   of the calling CPU.
  86
  87   Writes back and invalidates the entire data cache in cache coherency domain
  88   of the calling CPU. This function guarantees that all dirty cache lines are
  89   written back to system memory, and also invalidates all the data cache lines
  90   in the cache coherency domain of the calling CPU.
  91
  92 **/
  93 VOID
  94 EFIAPI
  95 WriteBackInvalidateDataCache (
  96   VOID
  97   )
  98 {
  99   DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
 100 }
 101
 102 /**
 103   Writes back and invalidates a range of data cache lines in the cache
 104   coherency domain of the calling CPU.
 105
 106   Writes back and invalidates the data cache lines specified by Address and
 107   Length. If Address is not aligned on a cache line boundary, then entire data
 108   cache line containing Address is written back and invalidated. If Address +
 109   Length is not aligned on a cache line boundary, then the entire data cache
 110   line containing Address + Length -1 is written back and invalidated. This
 111   function may choose to write back and invalidate the entire data cache if
 112   that is more efficient than writing back and invalidating the specified
 113   range. If Length is 0, then no data cache lines are written back and
 114   invalidated. Address is returned.
 115
 116   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 117
 118   @param  Address The base address of the data cache lines to write back and
 119                   invalidate. If the CPU is in a physical addressing mode, then
 120                   Address is a physical address. If the CPU is in a virtual
 121                   addressing mode, then Address is a virtual address.
 122   @param  Length  The number of bytes to write back and invalidate from the
 123                   data cache.
 124
 125   @return Address of cache invalidation.
 126
 127 **/
 128 VOID *
 129 EFIAPI
 130 WriteBackInvalidateDataCacheRange (
 131   IN      VOID   *Address,
 132   IN      UINTN  Length
 133   )
 134 {
 135   DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
 136   return Address;
 137 }
 138
 139 /**
 140   Writes back the entire data cache in cache coherency domain of the calling
 141   CPU.
 142
 143   Writes back the entire data cache in cache coherency domain of the calling
 144   CPU. This function guarantees that all dirty cache lines are written back to
 145   system memory. This function may also invalidate all the data cache lines in
 146   the cache coherency domain of the calling CPU.
 147
 148 **/
 149 VOID
 150 EFIAPI
 151 WriteBackDataCache (
 152   VOID
 153   )
 154 {
 155   DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
 156 }
 157
 158 /**
 159   Writes back a range of data cache lines in the cache coherency domain of the
 160   calling CPU.
 161
 162   Writes back the data cache lines specified by Address and Length. If Address
 163   is not aligned on a cache line boundary, then entire data cache line
 164   containing Address is written back. If Address + Length is not aligned on a
 165   cache line boundary, then the entire data cache line containing Address +
 166   Length -1 is written back. This function may choose to write back the entire
 167   data cache if that is more efficient than writing back the specified range.
 168   If Length is 0, then no data cache lines are written back. This function may
 169   also invalidate all the data cache lines in the specified range of the cache
 170   coherency domain of the calling CPU. Address is returned.
 171
 172   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 173
 174   @param  Address The base address of the data cache lines to write back. If
 175                   the CPU is in a physical addressing mode, then Address is a
 176                   physical address. If the CPU is in a virtual addressing
 177                   mode, then Address is a virtual address.
 178   @param  Length  The number of bytes to write back from the data cache.
 179
 180   @return Address of cache written in main memory.
 181
 182 **/
 183 VOID *
 184 EFIAPI
 185 WriteBackDataCacheRange (
 186   IN      VOID   *Address,
 187   IN      UINTN  Length
 188   )
 189 {
 190   DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
 191   return Address;
 192 }
 193
 194 /**
 195   Invalidates the entire data cache in cache coherency domain of the calling
 196   CPU.
 197
 198   Invalidates the entire data cache in cache coherency domain of the calling
 199   CPU. This function must be used with care because dirty cache lines are not
 200   written back to system memory. It is typically used for cache diagnostics. If
 201   the CPU does not support invalidation of the entire data cache, then a write
 202   back and invalidate operation should be performed on the entire data cache.
 203
 204 **/
 205 VOID
 206 EFIAPI
 207 InvalidateDataCache (
 208   VOID
 209   )
 210 {
 211   RiscVInvalidateDataCacheAsm ();
 212 }
 213
 214 /**
 215   Invalidates a range of data cache lines in the cache coherency domain of the
 216   calling CPU.
 217
 218   Invalidates the data cache lines specified by Address and Length. If Address
 219   is not aligned on a cache line boundary, then entire data cache line
 220   containing Address is invalidated. If Address + Length is not aligned on a
 221   cache line boundary, then the entire data cache line containing Address +
 222   Length -1 is invalidated. This function must never invalidate any cache lines
 223   outside the specified range. If Length is 0, then no data cache lines are
 224   invalidated. Address is returned. This function must be used with care
 225   because dirty cache lines are not written back to system memory. It is
 226   typically used for cache diagnostics. If the CPU does not support
 227   invalidation of a data cache range, then a write back and invalidate
 228   operation should be performed on the data cache range.
 229
 230   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 231
 232   @param  Address The base address of the data cache lines to invalidate. If
 233                   the CPU is in a physical addressing mode, then Address is a
 234                   physical address. If the CPU is in a virtual addressing mode,
 235                   then Address is a virtual address.
 236   @param  Length  The number of bytes to invalidate from the data cache.
 237
 238   @return Address.
 239
 240 **/
 241 VOID *
 242 EFIAPI
 243 InvalidateDataCacheRange (
 244   IN      VOID   *Address,
 245   IN      UINTN  Length
 246   )
 247 {
 248   DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
 249   return Address;
 250 }