MdePkg/Library/BaseCacheMaintenanceLib/X86Cache.c

   1 /** @file
   2   Cache Maintenance Functions.
   3
   4   Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8 **/
   9
  10 #include <Base.h>
  11 #include <Library/BaseLib.h>
  12 #include <Library/DebugLib.h>
  13
  14 /**
  15   Invalidates the entire instruction cache in cache coherency domain of the
  16   calling CPU.
  17
  18 **/
  19 VOID
  20 EFIAPI
  21 InvalidateInstructionCache (
  22   VOID
  23   )
  24 {
  25 }
  26
  27 /**
  28   Invalidates a range of instruction cache lines in the cache coherency domain
  29   of the calling CPU.
  30
  31   Invalidates the instruction cache lines specified by Address and Length. If
  32   Address is not aligned on a cache line boundary, then entire instruction
  33   cache line containing Address is invalidated. If Address + Length is not
  34   aligned on a cache line boundary, then the entire instruction cache line
  35   containing Address + Length -1 is invalidated. This function may choose to
  36   invalidate the entire instruction cache if that is more efficient than
  37   invalidating the specified range. If Length is 0, then no instruction cache
  38   lines are invalidated. Address is returned.
  39
  40   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  41
  42   @param  Address The base address of the instruction cache lines to
  43                   invalidate. If the CPU is in a physical addressing mode, then
  44                   Address is a physical address. If the CPU is in a virtual
  45                   addressing mode, then Address is a virtual address.
  46
  47   @param  Length  The number of bytes to invalidate from the instruction cache.
  48
  49   @return Address.
  50
  51 **/
  52 VOID *
  53 EFIAPI
  54 InvalidateInstructionCacheRange (
  55   IN      VOID   *Address,
  56   IN      UINTN  Length
  57   )
  58 {
  59   if (Length == 0) {
  60     return Address;
  61   }
  62
  63   ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
  64   return Address;
  65 }
  66
  67 /**
  68   Writes back and invalidates the entire data cache in cache coherency domain
  69   of the calling CPU.
  70
  71   Writes back and invalidates the entire data cache in cache coherency domain
  72   of the calling CPU. This function guarantees that all dirty cache lines are
  73   written back to system memory, and also invalidates all the data cache lines
  74   in the cache coherency domain of the calling CPU.
  75
  76 **/
  77 VOID
  78 EFIAPI
  79 WriteBackInvalidateDataCache (
  80   VOID
  81   )
  82 {
  83   AsmWbinvd ();
  84 }
  85
  86 /**
  87   Writes back and invalidates a range of data cache lines in the cache
  88   coherency domain of the calling CPU.
  89
  90   Writes back and invalidates the data cache lines specified by Address and
  91   Length. If Address is not aligned on a cache line boundary, then entire data
  92   cache line containing Address is written back and invalidated. If Address +
  93   Length is not aligned on a cache line boundary, then the entire data cache
  94   line containing Address + Length -1 is written back and invalidated. This
  95   function may choose to write back and invalidate the entire data cache if
  96   that is more efficient than writing back and invalidating the specified
  97   range. If Length is 0, then no data cache lines are written back and
  98   invalidated. Address is returned.
  99
 100   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 101
 102   @param  Address The base address of the data cache lines to write back and
 103                   invalidate. If the CPU is in a physical addressing mode, then
 104                   Address is a physical address. If the CPU is in a virtual
 105                   addressing mode, then Address is a virtual address.
 106   @param  Length  The number of bytes to write back and invalidate from the
 107                   data cache.
 108
 109   @return Address of cache invalidation.
 110
 111 **/
 112 VOID *
 113 EFIAPI
 114 WriteBackInvalidateDataCacheRange (
 115   IN      VOID   *Address,
 116   IN      UINTN  Length
 117   )
 118 {
 119   UINT32  RegEbx;
 120   UINT32  RegEdx;
 121   UINTN   CacheLineSize;
 122   UINTN   Start;
 123   UINTN   End;
 124
 125   if (Length == 0) {
 126     return Address;
 127   }
 128
 129   ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
 130
 131   //
 132   // If the CPU does not support CLFLUSH instruction,
 133   // then promote flush range to flush entire cache.
 134   //
 135   AsmCpuid (0x01, NULL, &RegEbx, NULL, &RegEdx);
 136   if ((RegEdx & BIT19) == 0) {
 137     AsmWbinvd ();
 138     return Address;
 139   }
 140
 141   //
 142   // Cache line size is 8 * Bits 15-08 of EBX returned from CPUID 01H
 143   //
 144   CacheLineSize = (RegEbx & 0xff00) >> 5;
 145
 146   Start = (UINTN)Address;
 147   //
 148   // Calculate the cache line alignment
 149   //
 150   End    = (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1);
 151   Start &= ~((UINTN)CacheLineSize - 1);
 152
 153   do {
 154     Start = (UINTN)AsmFlushCacheLine ((VOID *)Start) + CacheLineSize;
 155   } while (Start != End);
 156
 157   return Address;
 158 }
 159
 160 /**
 161   Writes back the entire data cache in cache coherency domain of the calling
 162   CPU.
 163
 164   Writes back the entire data cache in cache coherency domain of the calling
 165   CPU. This function guarantees that all dirty cache lines are written back to
 166   system memory. This function may also invalidate all the data cache lines in
 167   the cache coherency domain of the calling CPU.
 168
 169 **/
 170 VOID
 171 EFIAPI
 172 WriteBackDataCache (
 173   VOID
 174   )
 175 {
 176   WriteBackInvalidateDataCache ();
 177 }
 178
 179 /**
 180   Writes back a range of data cache lines in the cache coherency domain of the
 181   calling CPU.
 182
 183   Writes back the data cache lines specified by Address and Length. If Address
 184   is not aligned on a cache line boundary, then entire data cache line
 185   containing Address is written back. If Address + Length is not aligned on a
 186   cache line boundary, then the entire data cache line containing Address +
 187   Length -1 is written back. This function may choose to write back the entire
 188   data cache if that is more efficient than writing back the specified range.
 189   If Length is 0, then no data cache lines are written back. This function may
 190   also invalidate all the data cache lines in the specified range of the cache
 191   coherency domain of the calling CPU. Address is returned.
 192
 193   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 194
 195   @param  Address The base address of the data cache lines to write back. If
 196                   the CPU is in a physical addressing mode, then Address is a
 197                   physical address. If the CPU is in a virtual addressing
 198                   mode, then Address is a virtual address.
 199   @param  Length  The number of bytes to write back from the data cache.
 200
 201   @return Address of cache written in main memory.
 202
 203 **/
 204 VOID *
 205 EFIAPI
 206 WriteBackDataCacheRange (
 207   IN      VOID   *Address,
 208   IN      UINTN  Length
 209   )
 210 {
 211   return WriteBackInvalidateDataCacheRange (Address, Length);
 212 }
 213
 214 /**
 215   Invalidates the entire data cache in cache coherency domain of the calling
 216   CPU.
 217
 218   Invalidates the entire data cache in cache coherency domain of the calling
 219   CPU. This function must be used with care because dirty cache lines are not
 220   written back to system memory. It is typically used for cache diagnostics. If
 221   the CPU does not support invalidation of the entire data cache, then a write
 222   back and invalidate operation should be performed on the entire data cache.
 223
 224 **/
 225 VOID
 226 EFIAPI
 227 InvalidateDataCache (
 228   VOID
 229   )
 230 {
 231   AsmInvd ();
 232 }
 233
 234 /**
 235   Invalidates a range of data cache lines in the cache coherency domain of the
 236   calling CPU.
 237
 238   Invalidates the data cache lines specified by Address and Length. If Address
 239   is not aligned on a cache line boundary, then entire data cache line
 240   containing Address is invalidated. If Address + Length is not aligned on a
 241   cache line boundary, then the entire data cache line containing Address +
 242   Length -1 is invalidated. This function must never invalidate any cache lines
 243   outside the specified range. If Length is 0, then no data cache lines are
 244   invalidated. Address is returned. This function must be used with care
 245   because dirty cache lines are not written back to system memory. It is
 246   typically used for cache diagnostics. If the CPU does not support
 247   invalidation of a data cache range, then a write back and invalidate
 248   operation should be performed on the data cache range.
 249
 250   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 251
 252   @param  Address The base address of the data cache lines to invalidate. If
 253                   the CPU is in a physical addressing mode, then Address is a
 254                   physical address. If the CPU is in a virtual addressing mode,
 255                   then Address is a virtual address.
 256   @param  Length  The number of bytes to invalidate from the data cache.
 257
 258   @return Address.
 259
 260 **/
 261 VOID *
 262 EFIAPI
 263 InvalidateDataCacheRange (
 264   IN      VOID   *Address,
 265   IN      UINTN  Length
 266   )
 267 {
 268   //
 269   // Invalidation of a data cache range without writing back is not supported on
 270   // x86 architecture, so write back and invalidate operation is performed.
 271   //
 272   return WriteBackInvalidateDataCacheRange (Address, Length);
 273 }