MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c

   1 /** @file
   2   Cache Maintenance Functions.
   3
   4   Copyright (c) 2006, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14 **/
  15
  16 //
  17 // Include common header file for this module.
  18 //
  19 #include <Base.h>
  20 #include <Library/BaseLib.h>
  21 #include <Library/DebugLib.h>
  22
  23 //
  24 // This size must be at or below the smallest cache size possible among all
  25 // supported processors
  26 //
  27 #define CACHE_LINE_SIZE             0x20
  28
  29 /**
  30   Invalidates the entire instruction cache in cache coherency domain of the
  31   calling CPU.
  32
  33   Invalidates the entire instruction cache in cache coherency domain of the
  34   calling CPU.
  35
  36 **/
  37 VOID
  38 EFIAPI
  39 InvalidateInstructionCache (
  40   VOID
  41   )
  42 {
  43 }
  44
  45 /**
  46   Invalidates a range of instruction cache lines in the cache coherency domain
  47   of the calling CPU.
  48
  49   Invalidates the instruction cache lines specified by Address and Length. If
  50   Address is not aligned on a cache line boundary, then entire instruction
  51   cache line containing Address is invalidated. If Address + Length is not
  52   aligned on a cache line boundary, then the entire instruction cache line
  53   containing Address + Length -1 is invalidated. This function may choose to
  54   invalidate the entire instruction cache if that is more efficient than
  55   invalidating the specified range. If Length is 0, the no instruction cache
  56   lines are invalidated. Address is returned.
  57
  58   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  59
  60   @param  Address The base address of the instruction cache lines to
  61                   invalidate. If the CPU is in a physical addressing mode, then
  62                   Address is a physical address. If the CPU is in a virtual
  63                   addressing mode, then Address is a virtual address.
  64
  65   @param  Length  The number of bytes to invalidate from the instruction cache.
  66
  67   @return Address of cache invalidation.
  68
  69 **/
  70 VOID *
  71 EFIAPI
  72 InvalidateInstructionCacheRange (
  73   IN      VOID                      *Address,
  74   IN      UINTN                     Length
  75   )
  76 {
  77   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
  78   return Address;
  79 }
  80
  81 /**
  82   Writes Back and Invalidates the entire data cache in cache coherency domain
  83   of the calling CPU.
  84
  85   Writes Back and Invalidates the entire data cache in cache coherency domain
  86   of the calling CPU. This function guarantees that all dirty cache lines are
  87   written back to system memory, and also invalidates all the data cache lines
  88   in the cache coherency domain of the calling CPU.
  89
  90 **/
  91 VOID
  92 EFIAPI
  93 WriteBackInvalidateDataCache (
  94   VOID
  95   )
  96 {
  97   AsmWbinvd ();
  98 }
  99
 100 /**
 101   Writes Back and Invalidates a range of data cache lines in the cache
 102   coherency domain of the calling CPU.
 103
 104   Writes Back and Invalidate the data cache lines specified by Address and
 105   Length. If Address is not aligned on a cache line boundary, then entire data
 106   cache line containing Address is written back and invalidated. If Address +
 107   Length is not aligned on a cache line boundary, then the entire data cache
 108   line containing Address + Length -1 is written back and invalidated. This
 109   function may choose to write back and invalidate the entire data cache if
 110   that is more efficient than writing back and invalidating the specified
 111   range. If Length is 0, the no data cache lines are written back and
 112   invalidated. Address is returned.
 113
 114   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 115
 116   @param  Address The base address of the data cache lines to write back and
 117                   invalidate. If the CPU is in a physical addressing mode, then
 118                   Address is a physical address. If the CPU is in a virtual
 119                   addressing mode, then Address is a virtual address.
 120   @param  Length  The number of bytes to write back and invalidate from the
 121                   data cache.
 122
 123   @return Address of cache invalidation.
 124
 125 **/
 126 VOID *
 127 EFIAPI
 128 WriteBackInvalidateDataCacheRange (
 129   IN      VOID                      *Address,
 130   IN      UINTN                     Length
 131   )
 132 {
 133   UINTN                             Start, End;
 134
 135   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 136
 137   if (Length == 0) {
 138     return Address;
 139   }
 140
 141   Start = (UINTN)Address;
 142   //
 143   // Calculate the cache line alignment
 144   //
 145   End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);
 146   Start &= ~(CACHE_LINE_SIZE - 1);
 147
 148   do {
 149     Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;
 150   } while (Start != End);
 151   return Address;
 152 }
 153
 154 /**
 155   Writes Back the entire data cache in cache coherency domain of the calling
 156   CPU.
 157
 158   Writes Back the entire data cache in cache coherency domain of the calling
 159   CPU. This function guarantees that all dirty cache lines are written back to
 160   system memory. This function may also invalidate all the data cache lines in
 161   the cache coherency domain of the calling CPU.
 162
 163 **/
 164 VOID
 165 EFIAPI
 166 WriteBackDataCache (
 167   VOID
 168   )
 169 {
 170   WriteBackInvalidateDataCache ();
 171 }
 172
 173 /**
 174   Writes Back a range of data cache lines in the cache coherency domain of the
 175   calling CPU.
 176
 177   Writes Back the data cache lines specified by Address and Length. If Address
 178   is not aligned on a cache line boundary, then entire data cache line
 179   containing Address is written back. If Address + Length is not aligned on a
 180   cache line boundary, then the entire data cache line containing Address +
 181   Length -1 is written back. This function may choose to write back the entire
 182   data cache if that is more efficient than writing back the specified range.
 183   If Length is 0, the no data cache lines are written back. This function may
 184   also invalidate all the data cache lines in the specified range of the cache
 185   coherency domain of the calling CPU. Address is returned.
 186
 187   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 188
 189   @param  Address The base address of the data cache lines to write back. If
 190                   the CPU is in a physical addressing mode, then Address is a
 191                   physical address. If the CPU is in a virtual addressing
 192                   mode, then Address is a virtual address.
 193   @param  Length  The number of bytes to write back from the data cache.
 194
 195   @return Address of cache wrote in main memory.
 196
 197 **/
 198 VOID *
 199 EFIAPI
 200 WriteBackDataCacheRange (
 201   IN      VOID                      *Address,
 202   IN      UINTN                     Length
 203   )
 204 {
 205   return WriteBackInvalidateDataCacheRange (Address, Length);
 206 }
 207
 208 /**
 209   Invalidates the entire data cache in cache coherency domain of the calling
 210   CPU.
 211
 212   Invalidates the entire data cache in cache coherency domain of the calling
 213   CPU. This function must be used with care because dirty cache lines are not
 214   written back to system memory. It is typically used for cache diagnostics. If
 215   the CPU does not support invalidation of the entire data cache, then a write
 216   back and invalidate operation should be performed on the entire data cache.
 217
 218 **/
 219 VOID
 220 EFIAPI
 221 InvalidateDataCache (
 222   VOID
 223   )
 224 {
 225   AsmInvd ();
 226 }
 227
 228 /**
 229   Invalidates a range of data cache lines in the cache coherency domain of the
 230   calling CPU.
 231
 232   Invalidates the data cache lines specified by Address and Length. If Address
 233   is not aligned on a cache line boundary, then entire data cache line
 234   containing Address is invalidated. If Address + Length is not aligned on a
 235   cache line boundary, then the entire data cache line containing Address +
 236   Length -1 is invalidated. This function must never invalidate any cache lines
 237   outside the specified range. If Length is 0, the no data cache lines are
 238   invalidated. Address is returned. This function must be used with care
 239   because dirty cache lines are not written back to system memory. It is
 240   typically used for cache diagnostics. If the CPU does not support
 241   invalidation of a data cache range, then a write back and invalidate
 242   operation should be performed on the data cache range.
 243
 244   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 245
 246   @param  Address The base address of the data cache lines to invalidate. If
 247                   the CPU is in a physical addressing mode, then Address is a
 248                   physical address. If the CPU is in a virtual addressing mode,
 249                   then Address is a virtual address.
 250   @param  Length  The number of bytes to invalidate from the data cache.
 251
 252   @return Address of cache invalidation.
 253
 254 **/
 255 VOID *
 256 EFIAPI
 257 InvalidateDataCacheRange (
 258   IN      VOID                      *Address,
 259   IN      UINTN                     Length
 260   )
 261 {
 262   return WriteBackInvalidateDataCacheRange (Address, Length);
 263 }