MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c

   1 /** @file
   2   Cache Maintenance Functions.
   3
   4   Copyright (c) 2006, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13   Module Name:  x86Cache.c
  14
  15 **/
  16
  17 //
  18 // Include common header file for this module.
  19 //
  20 #include "CommonHeader.h"
  21
  22 //
  23 // This size must be at or below the smallest cache size possible among all
  24 // supported processors
  25 //
  26 #define CACHE_LINE_SIZE             0x20
  27
  28 /**
  29   Invalidates the entire instruction cache in cache coherency domain of the
  30   calling CPU.
  31
  32   Invalidates the entire instruction cache in cache coherency domain of the
  33   calling CPU.
  34
  35 **/
  36 VOID
  37 EFIAPI
  38 InvalidateInstructionCache (
  39   VOID
  40   )
  41 {
  42 }
  43
  44 /**
  45   Invalidates a range of instruction cache lines in the cache coherency domain
  46   of the calling CPU.
  47
  48   Invalidates the instruction cache lines specified by Address and Length. If
  49   Address is not aligned on a cache line boundary, then entire instruction
  50   cache line containing Address is invalidated. If Address + Length is not
  51   aligned on a cache line boundary, then the entire instruction cache line
  52   containing Address + Length -1 is invalidated. This function may choose to
  53   invalidate the entire instruction cache if that is more efficient than
  54   invalidating the specified range. If Length is 0, the no instruction cache
  55   lines are invalidated. Address is returned.
  56
  57   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  58
  59   @param  Address The base address of the instruction cache lines to
  60                   invalidate. If the CPU is in a physical addressing mode, then
  61                   Address is a physical address. If the CPU is in a virtual
  62                   addressing mode, then Address is a virtual address.
  63
  64   @param  Length  The number of bytes to invalidate from the instruction cache.
  65
  66   @return Address
  67
  68 **/
  69 VOID *
  70 EFIAPI
  71 InvalidateInstructionCacheRange (
  72   IN      VOID                      *Address,
  73   IN      UINTN                     Length
  74   )
  75 {
  76   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
  77   return Address;
  78 }
  79
  80 /**
  81   Writes Back and Invalidates the entire data cache in cache coherency domain
  82   of the calling CPU.
  83
  84   Writes Back and Invalidates the entire data cache in cache coherency domain
  85   of the calling CPU. This function guarantees that all dirty cache lines are
  86   written back to system memory, and also invalidates all the data cache lines
  87   in the cache coherency domain of the calling CPU.
  88
  89 **/
  90 VOID
  91 EFIAPI
  92 WriteBackInvalidateDataCache (
  93   VOID
  94   )
  95 {
  96   AsmWbinvd ();
  97 }
  98
  99 /**
 100   Writes Back and Invalidates a range of data cache lines in the cache
 101   coherency domain of the calling CPU.
 102
 103   Writes Back and Invalidate the data cache lines specified by Address and
 104   Length. If Address is not aligned on a cache line boundary, then entire data
 105   cache line containing Address is written back and invalidated. If Address +
 106   Length is not aligned on a cache line boundary, then the entire data cache
 107   line containing Address + Length -1 is written back and invalidated. This
 108   function may choose to write back and invalidate the entire data cache if
 109   that is more efficient than writing back and invalidating the specified
 110   range. If Length is 0, the no data cache lines are written back and
 111   invalidated. Address is returned.
 112
 113   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 114
 115   @param  Address The base address of the data cache lines to write back and
 116                   invalidate. If the CPU is in a physical addressing mode, then
 117                   Address is a physical address. If the CPU is in a virtual
 118                   addressing mode, then Address is a virtual address.
 119   @param  Length  The number of bytes to write back and invalidate from the
 120                   data cache.
 121
 122   @return Address
 123
 124 **/
 125 VOID *
 126 EFIAPI
 127 WriteBackInvalidateDataCacheRange (
 128   IN      VOID                      *Address,
 129   IN      UINTN                     Length
 130   )
 131 {
 132   UINTN                             Start, End;
 133
 134   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 135
 136   if (Length == 0) {
 137     return Address;
 138   }
 139
 140   Start = (UINTN)Address;
 141   End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);
 142   Start &= ~(CACHE_LINE_SIZE - 1);
 143
 144   do {
 145     Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;
 146   } while (Start != End);
 147   return Address;
 148 }
 149
 150 /**
 151   Writes Back the entire data cache in cache coherency domain of the calling
 152   CPU.
 153
 154   Writes Back the entire data cache in cache coherency domain of the calling
 155   CPU. This function guarantees that all dirty cache lines are written back to
 156   system memory. This function may also invalidate all the data cache lines in
 157   the cache coherency domain of the calling CPU.
 158
 159 **/
 160 VOID
 161 EFIAPI
 162 WriteBackDataCache (
 163   VOID
 164   )
 165 {
 166   WriteBackInvalidateDataCache ();
 167 }
 168
 169 /**
 170   Writes Back a range of data cache lines in the cache coherency domain of the
 171   calling CPU.
 172
 173   Writes Back the data cache lines specified by Address and Length. If Address
 174   is not aligned on a cache line boundary, then entire data cache line
 175   containing Address is written back. If Address + Length is not aligned on a
 176   cache line boundary, then the entire data cache line containing Address +
 177   Length -1 is written back. This function may choose to write back the entire
 178   data cache if that is more efficient than writing back the specified range.
 179   If Length is 0, the no data cache lines are written back. This function may
 180   also invalidate all the data cache lines in the specified range of the cache
 181   coherency domain of the calling CPU. Address is returned.
 182
 183   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 184
 185   @param  Address The base address of the data cache lines to write back. If
 186                   the CPU is in a physical addressing mode, then Address is a
 187                   physical address. If the CPU is in a virtual addressing
 188                   mode, then Address is a virtual address.
 189   @param  Length  The number of bytes to write back from the data cache.
 190
 191   @return Address
 192
 193 **/
 194 VOID *
 195 EFIAPI
 196 WriteBackDataCacheRange (
 197   IN      VOID                      *Address,
 198   IN      UINTN                     Length
 199   )
 200 {
 201   return WriteBackInvalidateDataCacheRange (Address, Length);
 202 }
 203
 204 /**
 205   Invalidates the entire data cache in cache coherency domain of the calling
 206   CPU.
 207
 208   Invalidates the entire data cache in cache coherency domain of the calling
 209   CPU. This function must be used with care because dirty cache lines are not
 210   written back to system memory. It is typically used for cache diagnostics. If
 211   the CPU does not support invalidation of the entire data cache, then a write
 212   back and invalidate operation should be performed on the entire data cache.
 213
 214 **/
 215 VOID
 216 EFIAPI
 217 InvalidateDataCache (
 218   VOID
 219   )
 220 {
 221   AsmInvd ();
 222 }
 223
 224 /**
 225   Invalidates a range of data cache lines in the cache coherency domain of the
 226   calling CPU.
 227
 228   Invalidates the data cache lines specified by Address and Length. If Address
 229   is not aligned on a cache line boundary, then entire data cache line
 230   containing Address is invalidated. If Address + Length is not aligned on a
 231   cache line boundary, then the entire data cache line containing Address +
 232   Length -1 is invalidated. This function must never invalidate any cache lines
 233   outside the specified range. If Length is 0, the no data cache lines are
 234   invalidated. Address is returned. This function must be used with care
 235   because dirty cache lines are not written back to system memory. It is
 236   typically used for cache diagnostics. If the CPU does not support
 237   invalidation of a data cache range, then a write back and invalidate
 238   operation should be performed on the data cache range.
 239
 240   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 241
 242   @param  Address The base address of the data cache lines to invalidate. If
 243                   the CPU is in a physical addressing mode, then Address is a
 244                   physical address. If the CPU is in a virtual addressing mode,
 245                   then Address is a virtual address.
 246   @param  Length  The number of bytes to invalidate from the data cache.
 247
 248   @return Address
 249
 250 **/
 251 VOID *
 252 EFIAPI
 253 InvalidateDataCacheRange (
 254   IN      VOID                      *Address,
 255   IN      UINTN                     Length
 256   )
 257 {
 258   return WriteBackInvalidateDataCacheRange (Address, Length);
 259 }