2 IA32/X64 specific Unit Test Host functions.
4 Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
9 #include "UnitTestHost.h"
12 /// Defines for mUnitTestHostBaseLibSegment indexes
14 #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS 0
15 #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS 1
16 #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES 2
17 #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS 3
18 #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS 4
19 #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS 5
20 #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR 6
21 #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR 7
24 /// Module global variables for simple system emulation of MSRs, CRx, DRx,
25 /// GDTR, IDTR, and Segment Selectors.
27 STATIC UINT64 mUnitTestHostBaseLibMsr
[2][0x1000];
28 STATIC UINTN mUnitTestHostBaseLibCr
[5];
29 STATIC UINTN mUnitTestHostBaseLibDr
[8];
30 STATIC UINT16 mUnitTestHostBaseLibSegment
[8];
31 STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibGdtr
;
32 STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibIdtr
;
35 Retrieves CPUID information.
37 Executes the CPUID instruction with EAX set to the value specified by Index.
38 This function always returns Index.
39 If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
40 If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
41 If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
42 If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
43 This function is only available on IA-32 and x64.
45 @param Index The 32-bit value to load into EAX prior to invoking the CPUID
47 @param Eax The pointer to the 32-bit EAX value returned by the CPUID
48 instruction. This is an optional parameter that may be NULL.
49 @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
50 instruction. This is an optional parameter that may be NULL.
51 @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
52 instruction. This is an optional parameter that may be NULL.
53 @param Edx The pointer to the 32-bit EDX value returned by the CPUID
54 instruction. This is an optional parameter that may be NULL.
61 UnitTestHostBaseLibAsmCpuid (
63 OUT UINT32
*Eax
, OPTIONAL
64 OUT UINT32
*Ebx
, OPTIONAL
65 OUT UINT32
*Ecx
, OPTIONAL
66 OUT UINT32
*Edx OPTIONAL
85 Retrieves CPUID information using an extended leaf identifier.
87 Executes the CPUID instruction with EAX set to the value specified by Index
88 and ECX set to the value specified by SubIndex. This function always returns
89 Index. This function is only available on IA-32 and x64.
91 If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
92 If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
93 If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
94 If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
96 @param Index The 32-bit value to load into EAX prior to invoking the
98 @param SubIndex The 32-bit value to load into ECX prior to invoking the
100 @param Eax The pointer to the 32-bit EAX value returned by the CPUID
101 instruction. This is an optional parameter that may be
103 @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
104 instruction. This is an optional parameter that may be
106 @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
107 instruction. This is an optional parameter that may be
109 @param Edx The pointer to the 32-bit EDX value returned by the CPUID
110 instruction. This is an optional parameter that may be
118 UnitTestHostBaseLibAsmCpuidEx (
121 OUT UINT32
*Eax
, OPTIONAL
122 OUT UINT32
*Ebx
, OPTIONAL
123 OUT UINT32
*Ecx
, OPTIONAL
124 OUT UINT32
*Edx OPTIONAL
143 Set CD bit and clear NW bit of CR0 followed by a WBINVD.
145 Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,
146 and executing a WBINVD instruction. This function is only available on IA-32 and x64.
151 UnitTestHostBaseLibAsmDisableCache (
158 Perform a WBINVD and clear both the CD and NW bits of CR0.
160 Enables the caches by executing a WBINVD instruction and then clear both the CD and NW
161 bits of CR0 to 0. This function is only available on IA-32 and x64.
166 UnitTestHostBaseLibAsmEnableCache (
173 Returns a 64-bit Machine Specific Register(MSR).
175 Reads and returns the 64-bit MSR specified by Index. No parameter checking is
176 performed on Index, and some Index values may cause CPU exceptions. The
177 caller must either guarantee that Index is valid, or the caller must set up
178 exception handlers to catch the exceptions. This function is only available
181 @param Index The 32-bit MSR index to read.
183 @return The value of the MSR identified by Index.
188 UnitTestHostBaseLibAsmReadMsr64 (
192 if (Index
< 0x1000) {
193 return mUnitTestHostBaseLibMsr
[0][Index
];
195 if (Index
>= 0xC0000000 && Index
< 0xC0001000) {
196 return mUnitTestHostBaseLibMsr
[1][Index
];
202 Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
205 Writes the 64-bit value specified by Value to the MSR specified by Index. The
206 64-bit value written to the MSR is returned. No parameter checking is
207 performed on Index or Value, and some of these may cause CPU exceptions. The
208 caller must either guarantee that Index and Value are valid, or the caller
209 must establish proper exception handlers. This function is only available on
212 @param Index The 32-bit MSR index to write.
213 @param Value The 64-bit value to write to the MSR.
220 UnitTestHostBaseLibAsmWriteMsr64 (
225 if (Index
< 0x1000) {
226 mUnitTestHostBaseLibMsr
[0][Index
] = Value
;
228 if (Index
>= 0xC0000000 && Index
< 0xC0001000) {
229 mUnitTestHostBaseLibMsr
[1][Index
- 0xC00000000] = Value
;
235 Reads the current value of the Control Register 0 (CR0).
237 Reads and returns the current value of CR0. This function is only available
238 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
241 @return The value of the Control Register 0 (CR0).
246 UnitTestHostBaseLibAsmReadCr0 (
250 return mUnitTestHostBaseLibCr
[0];
254 Reads the current value of the Control Register 2 (CR2).
256 Reads and returns the current value of CR2. This function is only available
257 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
260 @return The value of the Control Register 2 (CR2).
265 UnitTestHostBaseLibAsmReadCr2 (
269 return mUnitTestHostBaseLibCr
[2];
273 Reads the current value of the Control Register 3 (CR3).
275 Reads and returns the current value of CR3. This function is only available
276 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
279 @return The value of the Control Register 3 (CR3).
284 UnitTestHostBaseLibAsmReadCr3 (
288 return mUnitTestHostBaseLibCr
[3];
292 Reads the current value of the Control Register 4 (CR4).
294 Reads and returns the current value of CR4. This function is only available
295 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
298 @return The value of the Control Register 4 (CR4).
303 UnitTestHostBaseLibAsmReadCr4 (
307 return mUnitTestHostBaseLibCr
[4];
311 Writes a value to Control Register 0 (CR0).
313 Writes and returns a new value to CR0. This function is only available on
314 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
316 @param Cr0 The value to write to CR0.
318 @return The value written to CR0.
323 UnitTestHostBaseLibAsmWriteCr0 (
327 mUnitTestHostBaseLibCr
[0] = Cr0
;
332 Writes a value to Control Register 2 (CR2).
334 Writes and returns a new value to CR2. This function is only available on
335 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
337 @param Cr2 The value to write to CR2.
339 @return The value written to CR2.
344 UnitTestHostBaseLibAsmWriteCr2 (
348 mUnitTestHostBaseLibCr
[2] = Cr2
;
353 Writes a value to Control Register 3 (CR3).
355 Writes and returns a new value to CR3. This function is only available on
356 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
358 @param Cr3 The value to write to CR3.
360 @return The value written to CR3.
365 UnitTestHostBaseLibAsmWriteCr3 (
369 mUnitTestHostBaseLibCr
[3] = Cr3
;
374 Writes a value to Control Register 4 (CR4).
376 Writes and returns a new value to CR4. This function is only available on
377 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
379 @param Cr4 The value to write to CR4.
381 @return The value written to CR4.
386 UnitTestHostBaseLibAsmWriteCr4 (
390 mUnitTestHostBaseLibCr
[4] = Cr4
;
395 Reads the current value of Debug Register 0 (DR0).
397 Reads and returns the current value of DR0. This function is only available
398 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
401 @return The value of Debug Register 0 (DR0).
406 UnitTestHostBaseLibAsmReadDr0 (
410 return mUnitTestHostBaseLibDr
[0];
414 Reads the current value of Debug Register 1 (DR1).
416 Reads and returns the current value of DR1. This function is only available
417 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
420 @return The value of Debug Register 1 (DR1).
425 UnitTestHostBaseLibAsmReadDr1 (
429 return mUnitTestHostBaseLibDr
[1];
433 Reads the current value of Debug Register 2 (DR2).
435 Reads and returns the current value of DR2. This function is only available
436 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
439 @return The value of Debug Register 2 (DR2).
444 UnitTestHostBaseLibAsmReadDr2 (
448 return mUnitTestHostBaseLibDr
[2];
452 Reads the current value of Debug Register 3 (DR3).
454 Reads and returns the current value of DR3. This function is only available
455 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
458 @return The value of Debug Register 3 (DR3).
463 UnitTestHostBaseLibAsmReadDr3 (
467 return mUnitTestHostBaseLibDr
[3];
471 Reads the current value of Debug Register 4 (DR4).
473 Reads and returns the current value of DR4. This function is only available
474 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
477 @return The value of Debug Register 4 (DR4).
482 UnitTestHostBaseLibAsmReadDr4 (
486 return mUnitTestHostBaseLibDr
[4];
490 Reads the current value of Debug Register 5 (DR5).
492 Reads and returns the current value of DR5. This function is only available
493 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
496 @return The value of Debug Register 5 (DR5).
501 UnitTestHostBaseLibAsmReadDr5 (
505 return mUnitTestHostBaseLibDr
[5];
509 Reads the current value of Debug Register 6 (DR6).
511 Reads and returns the current value of DR6. This function is only available
512 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
515 @return The value of Debug Register 6 (DR6).
520 UnitTestHostBaseLibAsmReadDr6 (
524 return mUnitTestHostBaseLibDr
[6];
528 Reads the current value of Debug Register 7 (DR7).
530 Reads and returns the current value of DR7. This function is only available
531 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
534 @return The value of Debug Register 7 (DR7).
539 UnitTestHostBaseLibAsmReadDr7 (
543 return mUnitTestHostBaseLibDr
[7];
547 Writes a value to Debug Register 0 (DR0).
549 Writes and returns a new value to DR0. This function is only available on
550 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
552 @param Dr0 The value to write to Dr0.
554 @return The value written to Debug Register 0 (DR0).
559 UnitTestHostBaseLibAsmWriteDr0 (
563 mUnitTestHostBaseLibDr
[0] = Dr0
;
568 Writes a value to Debug Register 1 (DR1).
570 Writes and returns a new value to DR1. This function is only available on
571 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
573 @param Dr1 The value to write to Dr1.
575 @return The value written to Debug Register 1 (DR1).
580 UnitTestHostBaseLibAsmWriteDr1 (
584 mUnitTestHostBaseLibDr
[1] = Dr1
;
589 Writes a value to Debug Register 2 (DR2).
591 Writes and returns a new value to DR2. This function is only available on
592 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
594 @param Dr2 The value to write to Dr2.
596 @return The value written to Debug Register 2 (DR2).
601 UnitTestHostBaseLibAsmWriteDr2 (
605 mUnitTestHostBaseLibDr
[2] = Dr2
;
610 Writes a value to Debug Register 3 (DR3).
612 Writes and returns a new value to DR3. This function is only available on
613 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
615 @param Dr3 The value to write to Dr3.
617 @return The value written to Debug Register 3 (DR3).
622 UnitTestHostBaseLibAsmWriteDr3 (
626 mUnitTestHostBaseLibDr
[3] = Dr3
;
631 Writes a value to Debug Register 4 (DR4).
633 Writes and returns a new value to DR4. This function is only available on
634 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
636 @param Dr4 The value to write to Dr4.
638 @return The value written to Debug Register 4 (DR4).
643 UnitTestHostBaseLibAsmWriteDr4 (
647 mUnitTestHostBaseLibDr
[4] = Dr4
;
652 Writes a value to Debug Register 5 (DR5).
654 Writes and returns a new value to DR5. This function is only available on
655 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
657 @param Dr5 The value to write to Dr5.
659 @return The value written to Debug Register 5 (DR5).
664 UnitTestHostBaseLibAsmWriteDr5 (
668 mUnitTestHostBaseLibDr
[5] = Dr5
;
673 Writes a value to Debug Register 6 (DR6).
675 Writes and returns a new value to DR6. This function is only available on
676 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
678 @param Dr6 The value to write to Dr6.
680 @return The value written to Debug Register 6 (DR6).
685 UnitTestHostBaseLibAsmWriteDr6 (
689 mUnitTestHostBaseLibDr
[6] = Dr6
;
694 Writes a value to Debug Register 7 (DR7).
696 Writes and returns a new value to DR7. This function is only available on
697 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
699 @param Dr7 The value to write to Dr7.
701 @return The value written to Debug Register 7 (DR7).
706 UnitTestHostBaseLibAsmWriteDr7 (
710 mUnitTestHostBaseLibDr
[7] = Dr7
;
715 Reads the current value of Code Segment Register (CS).
717 Reads and returns the current value of CS. This function is only available on
720 @return The current value of CS.
725 UnitTestHostBaseLibAsmReadCs (
729 return mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS
];
733 Reads the current value of Data Segment Register (DS).
735 Reads and returns the current value of DS. This function is only available on
738 @return The current value of DS.
743 UnitTestHostBaseLibAsmReadDs (
747 return mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS
];
751 Reads the current value of Extra Segment Register (ES).
753 Reads and returns the current value of ES. This function is only available on
756 @return The current value of ES.
761 UnitTestHostBaseLibAsmReadEs (
765 return mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES
];
769 Reads the current value of FS Data Segment Register (FS).
771 Reads and returns the current value of FS. This function is only available on
774 @return The current value of FS.
779 UnitTestHostBaseLibAsmReadFs (
783 return mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS
];
787 Reads the current value of GS Data Segment Register (GS).
789 Reads and returns the current value of GS. This function is only available on
792 @return The current value of GS.
797 UnitTestHostBaseLibAsmReadGs (
801 return mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS
];
805 Reads the current value of Stack Segment Register (SS).
807 Reads and returns the current value of SS. This function is only available on
810 @return The current value of SS.
815 UnitTestHostBaseLibAsmReadSs (
819 return mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS
];
823 Reads the current value of Task Register (TR).
825 Reads and returns the current value of TR. This function is only available on
828 @return The current value of TR.
833 UnitTestHostBaseLibAsmReadTr (
837 return mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR
];
841 Reads the current Global Descriptor Table Register(GDTR) descriptor.
843 Reads and returns the current GDTR descriptor and returns it in Gdtr. This
844 function is only available on IA-32 and x64.
846 If Gdtr is NULL, then ASSERT().
848 @param Gdtr The pointer to a GDTR descriptor.
853 UnitTestHostBaseLibAsmReadGdtr (
854 OUT IA32_DESCRIPTOR
*Gdtr
857 Gdtr
= &mUnitTestHostBaseLibGdtr
;
861 Writes the current Global Descriptor Table Register (GDTR) descriptor.
863 Writes and the current GDTR descriptor specified by Gdtr. This function is
864 only available on IA-32 and x64.
866 If Gdtr is NULL, then ASSERT().
868 @param Gdtr The pointer to a GDTR descriptor.
873 UnitTestHostBaseLibAsmWriteGdtr (
874 IN CONST IA32_DESCRIPTOR
*Gdtr
877 CopyMem (&mUnitTestHostBaseLibGdtr
, Gdtr
, sizeof (IA32_DESCRIPTOR
));
881 Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.
883 Reads and returns the current IDTR descriptor and returns it in Idtr. This
884 function is only available on IA-32 and x64.
886 If Idtr is NULL, then ASSERT().
888 @param Idtr The pointer to a IDTR descriptor.
893 UnitTestHostBaseLibAsmReadIdtr (
894 OUT IA32_DESCRIPTOR
*Idtr
897 Idtr
= &mUnitTestHostBaseLibIdtr
;
901 Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.
903 Writes the current IDTR descriptor and returns it in Idtr. This function is
904 only available on IA-32 and x64.
906 If Idtr is NULL, then ASSERT().
908 @param Idtr The pointer to a IDTR descriptor.
913 UnitTestHostBaseLibAsmWriteIdtr (
914 IN CONST IA32_DESCRIPTOR
*Idtr
917 CopyMem (&mUnitTestHostBaseLibIdtr
, Idtr
, sizeof (IA32_DESCRIPTOR
));
921 Reads the current Local Descriptor Table Register(LDTR) selector.
923 Reads and returns the current 16-bit LDTR descriptor value. This function is
924 only available on IA-32 and x64.
926 @return The current selector of LDT.
931 UnitTestHostBaseLibAsmReadLdtr (
935 return mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR
];
939 Writes the current Local Descriptor Table Register (LDTR) selector.
941 Writes and the current LDTR descriptor specified by Ldtr. This function is
942 only available on IA-32 and x64.
944 @param Ldtr 16-bit LDTR selector value.
949 UnitTestHostBaseLibAsmWriteLdtr (
953 mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR
] = Ldtr
;
957 Reads the current value of a Performance Counter (PMC).
959 Reads and returns the current value of performance counter specified by
960 Index. This function is only available on IA-32 and x64.
962 @param Index The 32-bit Performance Counter index to read.
964 @return The value of the PMC specified by Index.
969 UnitTestHostBaseLibAsmReadPmc (
977 Sets up a monitor buffer that is used by AsmMwait().
979 Executes a MONITOR instruction with the register state specified by Eax, Ecx
980 and Edx. Returns Eax. This function is only available on IA-32 and x64.
982 @param Eax The value to load into EAX or RAX before executing the MONITOR
984 @param Ecx The value to load into ECX or RCX before executing the MONITOR
986 @param Edx The value to load into EDX or RDX before executing the MONITOR
994 UnitTestHostBaseLibAsmMonitor (
1004 Executes an MWAIT instruction.
1006 Executes an MWAIT instruction with the register state specified by Eax and
1007 Ecx. Returns Eax. This function is only available on IA-32 and x64.
1009 @param Eax The value to load into EAX or RAX before executing the MONITOR
1011 @param Ecx The value to load into ECX or RCX before executing the MONITOR
1019 UnitTestHostBaseLibAsmMwait (
1028 Executes a WBINVD instruction.
1030 Executes a WBINVD instruction. This function is only available on IA-32 and
1036 UnitTestHostBaseLibAsmWbinvd (
1043 Executes a INVD instruction.
1045 Executes a INVD instruction. This function is only available on IA-32 and
1051 UnitTestHostBaseLibAsmInvd (
1058 Flushes a cache line from all the instruction and data caches within the
1059 coherency domain of the CPU.
1061 Flushed the cache line specified by LinearAddress, and returns LinearAddress.
1062 This function is only available on IA-32 and x64.
1064 @param LinearAddress The address of the cache line to flush. If the CPU is
1065 in a physical addressing mode, then LinearAddress is a
1066 physical address. If the CPU is in a virtual
1067 addressing mode, then LinearAddress is a virtual
1070 @return LinearAddress.
1074 UnitTestHostBaseLibAsmFlushCacheLine (
1075 IN VOID
*LinearAddress
1078 return LinearAddress
;
1082 Enables the 32-bit paging mode on the CPU.
1084 Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
1085 must be properly initialized prior to calling this service. This function
1086 assumes the current execution mode is 32-bit protected mode. This function is
1087 only available on IA-32. After the 32-bit paging mode is enabled, control is
1088 transferred to the function specified by EntryPoint using the new stack
1089 specified by NewStack and passing in the parameters specified by Context1 and
1090 Context2. Context1 and Context2 are optional and may be NULL. The function
1091 EntryPoint must never return.
1093 If the current execution mode is not 32-bit protected mode, then ASSERT().
1094 If EntryPoint is NULL, then ASSERT().
1095 If NewStack is NULL, then ASSERT().
1097 There are a number of constraints that must be followed before calling this
1099 1) Interrupts must be disabled.
1100 2) The caller must be in 32-bit protected mode with flat descriptors. This
1101 means all descriptors must have a base of 0 and a limit of 4GB.
1102 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat
1104 4) CR3 must point to valid page tables that will be used once the transition
1105 is complete, and those page tables must guarantee that the pages for this
1106 function and the stack are identity mapped.
1108 @param EntryPoint A pointer to function to call with the new stack after
1110 @param Context1 A pointer to the context to pass into the EntryPoint
1111 function as the first parameter after paging is enabled.
1112 @param Context2 A pointer to the context to pass into the EntryPoint
1113 function as the second parameter after paging is enabled.
1114 @param NewStack A pointer to the new stack to use for the EntryPoint
1115 function after paging is enabled.
1120 UnitTestHostBaseLibAsmEnablePaging32 (
1121 IN SWITCH_STACK_ENTRY_POINT EntryPoint
,
1122 IN VOID
*Context1
, OPTIONAL
1123 IN VOID
*Context2
, OPTIONAL
1127 EntryPoint (Context1
, Context2
);
1131 Disables the 32-bit paging mode on the CPU.
1133 Disables the 32-bit paging mode on the CPU and returns to 32-bit protected
1134 mode. This function assumes the current execution mode is 32-paged protected
1135 mode. This function is only available on IA-32. After the 32-bit paging mode
1136 is disabled, control is transferred to the function specified by EntryPoint
1137 using the new stack specified by NewStack and passing in the parameters
1138 specified by Context1 and Context2. Context1 and Context2 are optional and
1139 may be NULL. The function EntryPoint must never return.
1141 If the current execution mode is not 32-bit paged mode, then ASSERT().
1142 If EntryPoint is NULL, then ASSERT().
1143 If NewStack is NULL, then ASSERT().
1145 There are a number of constraints that must be followed before calling this
1147 1) Interrupts must be disabled.
1148 2) The caller must be in 32-bit paged mode.
1149 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.
1150 4) CR3 must point to valid page tables that guarantee that the pages for
1151 this function and the stack are identity mapped.
1153 @param EntryPoint A pointer to function to call with the new stack after
1155 @param Context1 A pointer to the context to pass into the EntryPoint
1156 function as the first parameter after paging is disabled.
1157 @param Context2 A pointer to the context to pass into the EntryPoint
1158 function as the second parameter after paging is
1160 @param NewStack A pointer to the new stack to use for the EntryPoint
1161 function after paging is disabled.
1166 UnitTestHostBaseLibAsmDisablePaging32 (
1167 IN SWITCH_STACK_ENTRY_POINT EntryPoint
,
1168 IN VOID
*Context1
, OPTIONAL
1169 IN VOID
*Context2
, OPTIONAL
1173 EntryPoint (Context1
, Context2
);
1177 Enables the 64-bit paging mode on the CPU.
1179 Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
1180 must be properly initialized prior to calling this service. This function
1181 assumes the current execution mode is 32-bit protected mode with flat
1182 descriptors. This function is only available on IA-32. After the 64-bit
1183 paging mode is enabled, control is transferred to the function specified by
1184 EntryPoint using the new stack specified by NewStack and passing in the
1185 parameters specified by Context1 and Context2. Context1 and Context2 are
1186 optional and may be 0. The function EntryPoint must never return.
1188 If the current execution mode is not 32-bit protected mode with flat
1189 descriptors, then ASSERT().
1190 If EntryPoint is 0, then ASSERT().
1191 If NewStack is 0, then ASSERT().
1193 @param Cs The 16-bit selector to load in the CS before EntryPoint
1194 is called. The descriptor in the GDT that this selector
1195 references must be setup for long mode.
1196 @param EntryPoint The 64-bit virtual address of the function to call with
1197 the new stack after paging is enabled.
1198 @param Context1 The 64-bit virtual address of the context to pass into
1199 the EntryPoint function as the first parameter after
1201 @param Context2 The 64-bit virtual address of the context to pass into
1202 the EntryPoint function as the second parameter after
1204 @param NewStack The 64-bit virtual address of the new stack to use for
1205 the EntryPoint function after paging is enabled.
1210 UnitTestHostBaseLibAsmEnablePaging64 (
1212 IN UINT64 EntryPoint
,
1213 IN UINT64 Context1
, OPTIONAL
1214 IN UINT64 Context2
, OPTIONAL
1218 SWITCH_STACK_ENTRY_POINT NewEntryPoint
;
1220 NewEntryPoint
= (SWITCH_STACK_ENTRY_POINT
)(UINTN
)(EntryPoint
);
1221 NewEntryPoint ((VOID
*)(UINTN
)Context1
, (VOID
*)(UINTN
)Context2
);
1225 Disables the 64-bit paging mode on the CPU.
1227 Disables the 64-bit paging mode on the CPU and returns to 32-bit protected
1228 mode. This function assumes the current execution mode is 64-paging mode.
1229 This function is only available on x64. After the 64-bit paging mode is
1230 disabled, control is transferred to the function specified by EntryPoint
1231 using the new stack specified by NewStack and passing in the parameters
1232 specified by Context1 and Context2. Context1 and Context2 are optional and
1233 may be 0. The function EntryPoint must never return.
1235 If the current execution mode is not 64-bit paged mode, then ASSERT().
1236 If EntryPoint is 0, then ASSERT().
1237 If NewStack is 0, then ASSERT().
1239 @param Cs The 16-bit selector to load in the CS before EntryPoint
1240 is called. The descriptor in the GDT that this selector
1241 references must be setup for 32-bit protected mode.
1242 @param EntryPoint The 64-bit virtual address of the function to call with
1243 the new stack after paging is disabled.
1244 @param Context1 The 64-bit virtual address of the context to pass into
1245 the EntryPoint function as the first parameter after
1247 @param Context2 The 64-bit virtual address of the context to pass into
1248 the EntryPoint function as the second parameter after
1250 @param NewStack The 64-bit virtual address of the new stack to use for
1251 the EntryPoint function after paging is disabled.
1256 UnitTestHostBaseLibAsmDisablePaging64 (
1258 IN UINT32 EntryPoint
,
1259 IN UINT32 Context1
, OPTIONAL
1260 IN UINT32 Context2
, OPTIONAL
1264 SWITCH_STACK_ENTRY_POINT NewEntryPoint
;
1266 NewEntryPoint
= (SWITCH_STACK_ENTRY_POINT
)(UINTN
)(EntryPoint
);
1267 NewEntryPoint ((VOID
*)(UINTN
)Context1
, (VOID
*)(UINTN
)Context2
);
1271 Retrieves the properties for 16-bit thunk functions.
1273 Computes the size of the buffer and stack below 1MB required to use the
1274 AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This
1275 buffer size is returned in RealModeBufferSize, and the stack size is returned
1276 in ExtraStackSize. If parameters are passed to the 16-bit real mode code,
1277 then the actual minimum stack size is ExtraStackSize plus the maximum number
1278 of bytes that need to be passed to the 16-bit real mode code.
1280 If RealModeBufferSize is NULL, then ASSERT().
1281 If ExtraStackSize is NULL, then ASSERT().
1283 @param RealModeBufferSize A pointer to the size of the buffer below 1MB
1284 required to use the 16-bit thunk functions.
1285 @param ExtraStackSize A pointer to the extra size of stack below 1MB
1286 that the 16-bit thunk functions require for
1287 temporary storage in the transition to and from
1293 UnitTestHostBaseLibAsmGetThunk16Properties (
1294 OUT UINT32
*RealModeBufferSize
,
1295 OUT UINT32
*ExtraStackSize
1298 *RealModeBufferSize
= 0;
1299 *ExtraStackSize
= 0;
1303 Prepares all structures a code required to use AsmThunk16().
1305 Prepares all structures and code required to use AsmThunk16().
1307 This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
1308 virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
1310 If ThunkContext is NULL, then ASSERT().
1312 @param ThunkContext A pointer to the context structure that describes the
1313 16-bit real mode code to call.
1318 UnitTestHostBaseLibAsmPrepareThunk16 (
1319 IN OUT THUNK_CONTEXT
*ThunkContext
1325 Transfers control to a 16-bit real mode entry point and returns the results.
1327 Transfers control to a 16-bit real mode entry point and returns the results.
1328 AsmPrepareThunk16() must be called with ThunkContext before this function is used.
1329 This function must be called with interrupts disabled.
1331 The register state from the RealModeState field of ThunkContext is restored just prior
1332 to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState,
1333 which is used to set the interrupt state when a 16-bit real mode entry point is called.
1334 Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.
1335 The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to
1336 the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.
1337 The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,
1338 so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment
1339 and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry
1340 point must exit with a RETF instruction. The register state is captured into RealModeState immediately
1341 after the RETF instruction is executed.
1343 If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
1344 or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure
1345 the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.
1347 If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
1348 then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.
1349 This includes the base vectors, the interrupt masks, and the edge/level trigger mode.
1351 If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code
1352 is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.
1354 If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
1355 ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to
1356 disable the A20 mask.
1358 If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in
1359 ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails,
1360 then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
1362 If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in
1363 ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
1365 If ThunkContext is NULL, then ASSERT().
1366 If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().
1367 If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
1368 ThunkAttributes, then ASSERT().
1370 This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
1371 virtual to physical mappings for ThunkContext.RealModeBuffer are mapped 1:1.
1373 @param ThunkContext A pointer to the context structure that describes the
1374 16-bit real mode code to call.
1379 UnitTestHostBaseLibAsmThunk16 (
1380 IN OUT THUNK_CONTEXT
*ThunkContext
1386 Prepares all structures and code for a 16-bit real mode thunk, transfers
1387 control to a 16-bit real mode entry point, and returns the results.
1389 Prepares all structures and code for a 16-bit real mode thunk, transfers
1390 control to a 16-bit real mode entry point, and returns the results. If the
1391 caller only need to perform a single 16-bit real mode thunk, then this
1392 service should be used. If the caller intends to make more than one 16-bit
1393 real mode thunk, then it is more efficient if AsmPrepareThunk16() is called
1394 once and AsmThunk16() can be called for each 16-bit real mode thunk.
1396 This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
1397 virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
1399 See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.
1401 @param ThunkContext A pointer to the context structure that describes the
1402 16-bit real mode code to call.
1407 UnitTestHostBaseLibAsmPrepareAndThunk16 (
1408 IN OUT THUNK_CONTEXT
*ThunkContext
1414 Load given selector into TR register.
1416 @param[in] Selector Task segment selector
1420 UnitTestHostBaseLibAsmWriteTr (
1424 mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR
] = Selector
;
1428 Performs a serializing operation on all load-from-memory instructions that
1429 were issued prior the AsmLfence function.
1431 Executes a LFENCE instruction. This function is only available on IA-32 and x64.
1436 UnitTestHostBaseLibAsmLfence (
1443 Patch the immediate operand of an IA32 or X64 instruction such that the byte,
1444 word, dword or qword operand is encoded at the end of the instruction's
1445 binary representation.
1447 This function should be used to update object code that was compiled with
1448 NASM from assembly source code. Example:
1452 mov eax, strict dword 0 ; the imm32 zero operand will be patched
1458 X86_ASSEMBLY_PATCH_LABEL gPatchCr3;
1459 PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);
1461 @param[out] InstructionEnd Pointer right past the instruction to patch. The
1462 immediate operand to patch is expected to
1463 comprise the trailing bytes of the instruction.
1464 If InstructionEnd is closer to address 0 than
1465 ValueSize permits, then ASSERT().
1467 @param[in] PatchValue The constant to write to the immediate operand.
1468 The caller is responsible for ensuring that
1469 PatchValue can be represented in the byte, word,
1470 dword or qword operand (as indicated through
1471 ValueSize); otherwise ASSERT().
1473 @param[in] ValueSize The size of the operand in bytes; must be 1, 2,
1474 4, or 8. ASSERT() otherwise.
1478 UnitTestHostBaseLibPatchInstructionX86 (
1479 OUT X86_ASSEMBLY_PATCH_LABEL
*InstructionEnd
,
1480 IN UINT64 PatchValue
,
1487 Retrieves CPUID information.
1489 Executes the CPUID instruction with EAX set to the value specified by Index.
1490 This function always returns Index.
1491 If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
1492 If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
1493 If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
1494 If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
1495 This function is only available on IA-32 and x64.
1497 @param Index The 32-bit value to load into EAX prior to invoking the CPUID
1499 @param Eax The pointer to the 32-bit EAX value returned by the CPUID
1500 instruction. This is an optional parameter that may be NULL.
1501 @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
1502 instruction. This is an optional parameter that may be NULL.
1503 @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
1504 instruction. This is an optional parameter that may be NULL.
1505 @param Edx The pointer to the 32-bit EDX value returned by the CPUID
1506 instruction. This is an optional parameter that may be NULL.
1515 OUT UINT32
*Eax
, OPTIONAL
1516 OUT UINT32
*Ebx
, OPTIONAL
1517 OUT UINT32
*Ecx
, OPTIONAL
1518 OUT UINT32
*Edx OPTIONAL
1521 return gUnitTestHostBaseLib
.X86
->AsmCpuid (Index
, Eax
, Ebx
, Ecx
, Edx
);
1525 Retrieves CPUID information using an extended leaf identifier.
1527 Executes the CPUID instruction with EAX set to the value specified by Index
1528 and ECX set to the value specified by SubIndex. This function always returns
1529 Index. This function is only available on IA-32 and x64.
1531 If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
1532 If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
1533 If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
1534 If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
1536 @param Index The 32-bit value to load into EAX prior to invoking the
1538 @param SubIndex The 32-bit value to load into ECX prior to invoking the
1540 @param Eax The pointer to the 32-bit EAX value returned by the CPUID
1541 instruction. This is an optional parameter that may be
1543 @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
1544 instruction. This is an optional parameter that may be
1546 @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
1547 instruction. This is an optional parameter that may be
1549 @param Edx The pointer to the 32-bit EDX value returned by the CPUID
1550 instruction. This is an optional parameter that may be
1561 OUT UINT32
*Eax
, OPTIONAL
1562 OUT UINT32
*Ebx
, OPTIONAL
1563 OUT UINT32
*Ecx
, OPTIONAL
1564 OUT UINT32
*Edx OPTIONAL
1567 return gUnitTestHostBaseLib
.X86
->AsmCpuidEx (Index
, SubIndex
, Eax
, Ebx
, Ecx
, Edx
);
1571 Set CD bit and clear NW bit of CR0 followed by a WBINVD.
1573 Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,
1574 and executing a WBINVD instruction. This function is only available on IA-32 and x64.
1583 gUnitTestHostBaseLib
.X86
->AsmDisableCache ();
1587 Perform a WBINVD and clear both the CD and NW bits of CR0.
1589 Enables the caches by executing a WBINVD instruction and then clear both the CD and NW
1590 bits of CR0 to 0. This function is only available on IA-32 and x64.
1599 gUnitTestHostBaseLib
.X86
->AsmEnableCache ();
1603 Returns a 64-bit Machine Specific Register(MSR).
1605 Reads and returns the 64-bit MSR specified by Index. No parameter checking is
1606 performed on Index, and some Index values may cause CPU exceptions. The
1607 caller must either guarantee that Index is valid, or the caller must set up
1608 exception handlers to catch the exceptions. This function is only available
1611 @param Index The 32-bit MSR index to read.
1613 @return The value of the MSR identified by Index.
1622 return gUnitTestHostBaseLib
.X86
->AsmReadMsr64 (Index
);
1626 Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
1629 Writes the 64-bit value specified by Value to the MSR specified by Index. The
1630 64-bit value written to the MSR is returned. No parameter checking is
1631 performed on Index or Value, and some of these may cause CPU exceptions. The
1632 caller must either guarantee that Index and Value are valid, or the caller
1633 must establish proper exception handlers. This function is only available on
1636 @param Index The 32-bit MSR index to write.
1637 @param Value The 64-bit value to write to the MSR.
1649 return gUnitTestHostBaseLib
.X86
->AsmWriteMsr64 (Index
, Value
);
1653 Reads the current value of the Control Register 0 (CR0).
1655 Reads and returns the current value of CR0. This function is only available
1656 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1659 @return The value of the Control Register 0 (CR0).
1668 return gUnitTestHostBaseLib
.X86
->AsmReadCr0 ();
1672 Reads the current value of the Control Register 2 (CR2).
1674 Reads and returns the current value of CR2. This function is only available
1675 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1678 @return The value of the Control Register 2 (CR2).
1687 return gUnitTestHostBaseLib
.X86
->AsmReadCr2 ();
1691 Reads the current value of the Control Register 3 (CR3).
1693 Reads and returns the current value of CR3. This function is only available
1694 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1697 @return The value of the Control Register 3 (CR3).
1706 return gUnitTestHostBaseLib
.X86
->AsmReadCr3 ();
1710 Reads the current value of the Control Register 4 (CR4).
1712 Reads and returns the current value of CR4. This function is only available
1713 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1716 @return The value of the Control Register 4 (CR4).
1725 return gUnitTestHostBaseLib
.X86
->AsmReadCr4 ();
1729 Writes a value to Control Register 0 (CR0).
1731 Writes and returns a new value to CR0. This function is only available on
1732 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
1734 @param Cr0 The value to write to CR0.
1736 @return The value written to CR0.
1745 return gUnitTestHostBaseLib
.X86
->AsmWriteCr0 (Cr0
);
1749 Writes a value to Control Register 2 (CR2).
1751 Writes and returns a new value to CR2. This function is only available on
1752 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
1754 @param Cr2 The value to write to CR2.
1756 @return The value written to CR2.
1765 return gUnitTestHostBaseLib
.X86
->AsmWriteCr2 (Cr2
);
1769 Writes a value to Control Register 3 (CR3).
1771 Writes and returns a new value to CR3. This function is only available on
1772 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
1774 @param Cr3 The value to write to CR3.
1776 @return The value written to CR3.
1785 return gUnitTestHostBaseLib
.X86
->AsmWriteCr3 (Cr3
);
1789 Writes a value to Control Register 4 (CR4).
1791 Writes and returns a new value to CR4. This function is only available on
1792 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
1794 @param Cr4 The value to write to CR4.
1796 @return The value written to CR4.
1805 return gUnitTestHostBaseLib
.X86
->AsmWriteCr4 (Cr4
);
1809 Reads the current value of Debug Register 0 (DR0).
1811 Reads and returns the current value of DR0. This function is only available
1812 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1815 @return The value of Debug Register 0 (DR0).
1824 return gUnitTestHostBaseLib
.X86
->AsmReadDr0 ();
1828 Reads the current value of Debug Register 1 (DR1).
1830 Reads and returns the current value of DR1. This function is only available
1831 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1834 @return The value of Debug Register 1 (DR1).
1843 return gUnitTestHostBaseLib
.X86
->AsmReadDr1 ();
1847 Reads the current value of Debug Register 2 (DR2).
1849 Reads and returns the current value of DR2. This function is only available
1850 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1853 @return The value of Debug Register 2 (DR2).
1862 return gUnitTestHostBaseLib
.X86
->AsmReadDr2 ();
1866 Reads the current value of Debug Register 3 (DR3).
1868 Reads and returns the current value of DR3. This function is only available
1869 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1872 @return The value of Debug Register 3 (DR3).
1881 return gUnitTestHostBaseLib
.X86
->AsmReadDr3 ();
1885 Reads the current value of Debug Register 4 (DR4).
1887 Reads and returns the current value of DR4. This function is only available
1888 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1891 @return The value of Debug Register 4 (DR4).
1900 return gUnitTestHostBaseLib
.X86
->AsmReadDr4 ();
1904 Reads the current value of Debug Register 5 (DR5).
1906 Reads and returns the current value of DR5. This function is only available
1907 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1910 @return The value of Debug Register 5 (DR5).
1919 return gUnitTestHostBaseLib
.X86
->AsmReadDr5 ();
1923 Reads the current value of Debug Register 6 (DR6).
1925 Reads and returns the current value of DR6. This function is only available
1926 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1929 @return The value of Debug Register 6 (DR6).
1938 return gUnitTestHostBaseLib
.X86
->AsmReadDr6 ();
1942 Reads the current value of Debug Register 7 (DR7).
1944 Reads and returns the current value of DR7. This function is only available
1945 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1948 @return The value of Debug Register 7 (DR7).
1957 return gUnitTestHostBaseLib
.X86
->AsmReadDr7 ();
1961 Writes a value to Debug Register 0 (DR0).
1963 Writes and returns a new value to DR0. This function is only available on
1964 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
1966 @param Dr0 The value to write to Dr0.
1968 @return The value written to Debug Register 0 (DR0).
1977 return gUnitTestHostBaseLib
.X86
->AsmWriteDr0 (Dr0
);
1981 Writes a value to Debug Register 1 (DR1).
1983 Writes and returns a new value to DR1. This function is only available on
1984 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
1986 @param Dr1 The value to write to Dr1.
1988 @return The value written to Debug Register 1 (DR1).
1997 return gUnitTestHostBaseLib
.X86
->AsmWriteDr1 (Dr1
);
2001 Writes a value to Debug Register 2 (DR2).
2003 Writes and returns a new value to DR2. This function is only available on
2004 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
2006 @param Dr2 The value to write to Dr2.
2008 @return The value written to Debug Register 2 (DR2).
2017 return gUnitTestHostBaseLib
.X86
->AsmWriteDr2 (Dr2
);
2021 Writes a value to Debug Register 3 (DR3).
2023 Writes and returns a new value to DR3. This function is only available on
2024 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
2026 @param Dr3 The value to write to Dr3.
2028 @return The value written to Debug Register 3 (DR3).
2037 return gUnitTestHostBaseLib
.X86
->AsmWriteDr3 (Dr3
);
2041 Writes a value to Debug Register 4 (DR4).
2043 Writes and returns a new value to DR4. This function is only available on
2044 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
2046 @param Dr4 The value to write to Dr4.
2048 @return The value written to Debug Register 4 (DR4).
2057 return gUnitTestHostBaseLib
.X86
->AsmWriteDr4 (Dr4
);
2061 Writes a value to Debug Register 5 (DR5).
2063 Writes and returns a new value to DR5. This function is only available on
2064 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
2066 @param Dr5 The value to write to Dr5.
2068 @return The value written to Debug Register 5 (DR5).
2077 return gUnitTestHostBaseLib
.X86
->AsmWriteDr5 (Dr5
);
2081 Writes a value to Debug Register 6 (DR6).
2083 Writes and returns a new value to DR6. This function is only available on
2084 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
2086 @param Dr6 The value to write to Dr6.
2088 @return The value written to Debug Register 6 (DR6).
2097 return gUnitTestHostBaseLib
.X86
->AsmWriteDr6 (Dr6
);
2101 Writes a value to Debug Register 7 (DR7).
2103 Writes and returns a new value to DR7. This function is only available on
2104 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
2106 @param Dr7 The value to write to Dr7.
2108 @return The value written to Debug Register 7 (DR7).
2117 return gUnitTestHostBaseLib
.X86
->AsmWriteDr7 (Dr7
);
2121 Reads the current value of Code Segment Register (CS).
2123 Reads and returns the current value of CS. This function is only available on
2126 @return The current value of CS.
2135 return gUnitTestHostBaseLib
.X86
->AsmReadCs ();
2139 Reads the current value of Data Segment Register (DS).
2141 Reads and returns the current value of DS. This function is only available on
2144 @return The current value of DS.
2153 return gUnitTestHostBaseLib
.X86
->AsmReadDs ();
2157 Reads the current value of Extra Segment Register (ES).
2159 Reads and returns the current value of ES. This function is only available on
2162 @return The current value of ES.
2171 return gUnitTestHostBaseLib
.X86
->AsmReadEs ();
2175 Reads the current value of FS Data Segment Register (FS).
2177 Reads and returns the current value of FS. This function is only available on
2180 @return The current value of FS.
2189 return gUnitTestHostBaseLib
.X86
->AsmReadFs ();
2193 Reads the current value of GS Data Segment Register (GS).
2195 Reads and returns the current value of GS. This function is only available on
2198 @return The current value of GS.
2207 return gUnitTestHostBaseLib
.X86
->AsmReadGs ();
2211 Reads the current value of Stack Segment Register (SS).
2213 Reads and returns the current value of SS. This function is only available on
2216 @return The current value of SS.
2225 return gUnitTestHostBaseLib
.X86
->AsmReadSs ();
2229 Reads the current value of Task Register (TR).
2231 Reads and returns the current value of TR. This function is only available on
2234 @return The current value of TR.
2243 return gUnitTestHostBaseLib
.X86
->AsmReadTr ();
2247 Reads the current Global Descriptor Table Register(GDTR) descriptor.
2249 Reads and returns the current GDTR descriptor and returns it in Gdtr. This
2250 function is only available on IA-32 and x64.
2252 If Gdtr is NULL, then ASSERT().
2254 @param Gdtr The pointer to a GDTR descriptor.
2260 OUT IA32_DESCRIPTOR
*Gdtr
2263 gUnitTestHostBaseLib
.X86
->AsmReadGdtr (Gdtr
);
2267 Writes the current Global Descriptor Table Register (GDTR) descriptor.
2269 Writes and the current GDTR descriptor specified by Gdtr. This function is
2270 only available on IA-32 and x64.
2272 If Gdtr is NULL, then ASSERT().
2274 @param Gdtr The pointer to a GDTR descriptor.
2280 IN CONST IA32_DESCRIPTOR
*Gdtr
2283 gUnitTestHostBaseLib
.X86
->AsmWriteGdtr (Gdtr
);
2287 Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.
2289 Reads and returns the current IDTR descriptor and returns it in Idtr. This
2290 function is only available on IA-32 and x64.
2292 If Idtr is NULL, then ASSERT().
2294 @param Idtr The pointer to a IDTR descriptor.
2300 OUT IA32_DESCRIPTOR
*Idtr
2303 gUnitTestHostBaseLib
.X86
->AsmReadIdtr (Idtr
);
2307 Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.
2309 Writes the current IDTR descriptor and returns it in Idtr. This function is
2310 only available on IA-32 and x64.
2312 If Idtr is NULL, then ASSERT().
2314 @param Idtr The pointer to a IDTR descriptor.
2320 IN CONST IA32_DESCRIPTOR
*Idtr
2323 gUnitTestHostBaseLib
.X86
->AsmWriteIdtr (Idtr
);
2327 Reads the current Local Descriptor Table Register(LDTR) selector.
2329 Reads and returns the current 16-bit LDTR descriptor value. This function is
2330 only available on IA-32 and x64.
2332 @return The current selector of LDT.
2341 return gUnitTestHostBaseLib
.X86
->AsmReadLdtr ();
2345 Writes the current Local Descriptor Table Register (LDTR) selector.
2347 Writes and the current LDTR descriptor specified by Ldtr. This function is
2348 only available on IA-32 and x64.
2350 @param Ldtr 16-bit LDTR selector value.
2359 gUnitTestHostBaseLib
.X86
->AsmWriteLdtr (Ldtr
);
2363 Reads the current value of a Performance Counter (PMC).
2365 Reads and returns the current value of performance counter specified by
2366 Index. This function is only available on IA-32 and x64.
2368 @param Index The 32-bit Performance Counter index to read.
2370 @return The value of the PMC specified by Index.
2379 return gUnitTestHostBaseLib
.X86
->AsmReadPmc (Index
);
2383 Sets up a monitor buffer that is used by AsmMwait().
2385 Executes a MONITOR instruction with the register state specified by Eax, Ecx
2386 and Edx. Returns Eax. This function is only available on IA-32 and x64.
2388 @param Eax The value to load into EAX or RAX before executing the MONITOR
2390 @param Ecx The value to load into ECX or RCX before executing the MONITOR
2392 @param Edx The value to load into EDX or RDX before executing the MONITOR
2406 return gUnitTestHostBaseLib
.X86
->AsmMonitor (Eax
, Ecx
, Edx
);
2410 Executes an MWAIT instruction.
2412 Executes an MWAIT instruction with the register state specified by Eax and
2413 Ecx. Returns Eax. This function is only available on IA-32 and x64.
2415 @param Eax The value to load into EAX or RAX before executing the MONITOR
2417 @param Ecx The value to load into ECX or RCX before executing the MONITOR
2430 return gUnitTestHostBaseLib
.X86
->AsmMwait (Eax
, Ecx
);
2434 Executes a WBINVD instruction.
2436 Executes a WBINVD instruction. This function is only available on IA-32 and
2446 gUnitTestHostBaseLib
.X86
->AsmWbinvd ();
2450 Executes a INVD instruction.
2452 Executes a INVD instruction. This function is only available on IA-32 and
2462 gUnitTestHostBaseLib
.X86
->AsmInvd ();
2466 Flushes a cache line from all the instruction and data caches within the
2467 coherency domain of the CPU.
2469 Flushed the cache line specified by LinearAddress, and returns LinearAddress.
2470 This function is only available on IA-32 and x64.
2472 @param LinearAddress The address of the cache line to flush. If the CPU is
2473 in a physical addressing mode, then LinearAddress is a
2474 physical address. If the CPU is in a virtual
2475 addressing mode, then LinearAddress is a virtual
2478 @return LinearAddress.
2483 IN VOID
*LinearAddress
2486 return gUnitTestHostBaseLib
.X86
->AsmFlushCacheLine (LinearAddress
);
2490 Enables the 32-bit paging mode on the CPU.
2492 Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
2493 must be properly initialized prior to calling this service. This function
2494 assumes the current execution mode is 32-bit protected mode. This function is
2495 only available on IA-32. After the 32-bit paging mode is enabled, control is
2496 transferred to the function specified by EntryPoint using the new stack
2497 specified by NewStack and passing in the parameters specified by Context1 and
2498 Context2. Context1 and Context2 are optional and may be NULL. The function
2499 EntryPoint must never return.
2501 If the current execution mode is not 32-bit protected mode, then ASSERT().
2502 If EntryPoint is NULL, then ASSERT().
2503 If NewStack is NULL, then ASSERT().
2505 There are a number of constraints that must be followed before calling this
2507 1) Interrupts must be disabled.
2508 2) The caller must be in 32-bit protected mode with flat descriptors. This
2509 means all descriptors must have a base of 0 and a limit of 4GB.
2510 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat
2512 4) CR3 must point to valid page tables that will be used once the transition
2513 is complete, and those page tables must guarantee that the pages for this
2514 function and the stack are identity mapped.
2516 @param EntryPoint A pointer to function to call with the new stack after
2518 @param Context1 A pointer to the context to pass into the EntryPoint
2519 function as the first parameter after paging is enabled.
2520 @param Context2 A pointer to the context to pass into the EntryPoint
2521 function as the second parameter after paging is enabled.
2522 @param NewStack A pointer to the new stack to use for the EntryPoint
2523 function after paging is enabled.
2529 IN SWITCH_STACK_ENTRY_POINT EntryPoint
,
2530 IN VOID
*Context1
, OPTIONAL
2531 IN VOID
*Context2
, OPTIONAL
2535 gUnitTestHostBaseLib
.X86
->AsmEnablePaging32 (EntryPoint
, Context1
, Context2
, NewStack
);
2539 Disables the 32-bit paging mode on the CPU.
2541 Disables the 32-bit paging mode on the CPU and returns to 32-bit protected
2542 mode. This function assumes the current execution mode is 32-paged protected
2543 mode. This function is only available on IA-32. After the 32-bit paging mode
2544 is disabled, control is transferred to the function specified by EntryPoint
2545 using the new stack specified by NewStack and passing in the parameters
2546 specified by Context1 and Context2. Context1 and Context2 are optional and
2547 may be NULL. The function EntryPoint must never return.
2549 If the current execution mode is not 32-bit paged mode, then ASSERT().
2550 If EntryPoint is NULL, then ASSERT().
2551 If NewStack is NULL, then ASSERT().
2553 There are a number of constraints that must be followed before calling this
2555 1) Interrupts must be disabled.
2556 2) The caller must be in 32-bit paged mode.
2557 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.
2558 4) CR3 must point to valid page tables that guarantee that the pages for
2559 this function and the stack are identity mapped.
2561 @param EntryPoint A pointer to function to call with the new stack after
2563 @param Context1 A pointer to the context to pass into the EntryPoint
2564 function as the first parameter after paging is disabled.
2565 @param Context2 A pointer to the context to pass into the EntryPoint
2566 function as the second parameter after paging is
2568 @param NewStack A pointer to the new stack to use for the EntryPoint
2569 function after paging is disabled.
2574 AsmDisablePaging32 (
2575 IN SWITCH_STACK_ENTRY_POINT EntryPoint
,
2576 IN VOID
*Context1
, OPTIONAL
2577 IN VOID
*Context2
, OPTIONAL
2581 gUnitTestHostBaseLib
.X86
->AsmDisablePaging32 (EntryPoint
, Context1
, Context2
, NewStack
);
2585 Enables the 64-bit paging mode on the CPU.
2587 Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
2588 must be properly initialized prior to calling this service. This function
2589 assumes the current execution mode is 32-bit protected mode with flat
2590 descriptors. This function is only available on IA-32. After the 64-bit
2591 paging mode is enabled, control is transferred to the function specified by
2592 EntryPoint using the new stack specified by NewStack and passing in the
2593 parameters specified by Context1 and Context2. Context1 and Context2 are
2594 optional and may be 0. The function EntryPoint must never return.
2596 If the current execution mode is not 32-bit protected mode with flat
2597 descriptors, then ASSERT().
2598 If EntryPoint is 0, then ASSERT().
2599 If NewStack is 0, then ASSERT().
2601 @param Cs The 16-bit selector to load in the CS before EntryPoint
2602 is called. The descriptor in the GDT that this selector
2603 references must be setup for long mode.
2604 @param EntryPoint The 64-bit virtual address of the function to call with
2605 the new stack after paging is enabled.
2606 @param Context1 The 64-bit virtual address of the context to pass into
2607 the EntryPoint function as the first parameter after
2609 @param Context2 The 64-bit virtual address of the context to pass into
2610 the EntryPoint function as the second parameter after
2612 @param NewStack The 64-bit virtual address of the new stack to use for
2613 the EntryPoint function after paging is enabled.
2620 IN UINT64 EntryPoint
,
2621 IN UINT64 Context1
, OPTIONAL
2622 IN UINT64 Context2
, OPTIONAL
2626 gUnitTestHostBaseLib
.X86
->AsmEnablePaging64 (Cs
, EntryPoint
, Context1
, Context2
, NewStack
);
2630 Disables the 64-bit paging mode on the CPU.
2632 Disables the 64-bit paging mode on the CPU and returns to 32-bit protected
2633 mode. This function assumes the current execution mode is 64-paging mode.
2634 This function is only available on x64. After the 64-bit paging mode is
2635 disabled, control is transferred to the function specified by EntryPoint
2636 using the new stack specified by NewStack and passing in the parameters
2637 specified by Context1 and Context2. Context1 and Context2 are optional and
2638 may be 0. The function EntryPoint must never return.
2640 If the current execution mode is not 64-bit paged mode, then ASSERT().
2641 If EntryPoint is 0, then ASSERT().
2642 If NewStack is 0, then ASSERT().
2644 @param Cs The 16-bit selector to load in the CS before EntryPoint
2645 is called. The descriptor in the GDT that this selector
2646 references must be setup for 32-bit protected mode.
2647 @param EntryPoint The 64-bit virtual address of the function to call with
2648 the new stack after paging is disabled.
2649 @param Context1 The 64-bit virtual address of the context to pass into
2650 the EntryPoint function as the first parameter after
2652 @param Context2 The 64-bit virtual address of the context to pass into
2653 the EntryPoint function as the second parameter after
2655 @param NewStack The 64-bit virtual address of the new stack to use for
2656 the EntryPoint function after paging is disabled.
2661 AsmDisablePaging64 (
2663 IN UINT32 EntryPoint
,
2664 IN UINT32 Context1
, OPTIONAL
2665 IN UINT32 Context2
, OPTIONAL
2669 gUnitTestHostBaseLib
.X86
->AsmDisablePaging64 (Cs
, EntryPoint
, Context1
, Context2
, NewStack
);
2673 Retrieves the properties for 16-bit thunk functions.
2675 Computes the size of the buffer and stack below 1MB required to use the
2676 AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This
2677 buffer size is returned in RealModeBufferSize, and the stack size is returned
2678 in ExtraStackSize. If parameters are passed to the 16-bit real mode code,
2679 then the actual minimum stack size is ExtraStackSize plus the maximum number
2680 of bytes that need to be passed to the 16-bit real mode code.
2682 If RealModeBufferSize is NULL, then ASSERT().
2683 If ExtraStackSize is NULL, then ASSERT().
2685 @param RealModeBufferSize A pointer to the size of the buffer below 1MB
2686 required to use the 16-bit thunk functions.
2687 @param ExtraStackSize A pointer to the extra size of stack below 1MB
2688 that the 16-bit thunk functions require for
2689 temporary storage in the transition to and from
2695 AsmGetThunk16Properties (
2696 OUT UINT32
*RealModeBufferSize
,
2697 OUT UINT32
*ExtraStackSize
2700 gUnitTestHostBaseLib
.X86
->AsmGetThunk16Properties (RealModeBufferSize
, ExtraStackSize
);
2704 Prepares all structures a code required to use AsmThunk16().
2706 Prepares all structures and code required to use AsmThunk16().
2708 This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
2709 virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
2711 If ThunkContext is NULL, then ASSERT().
2713 @param ThunkContext A pointer to the context structure that describes the
2714 16-bit real mode code to call.
2720 IN OUT THUNK_CONTEXT
*ThunkContext
2723 gUnitTestHostBaseLib
.X86
->AsmPrepareThunk16 (ThunkContext
);
2727 Transfers control to a 16-bit real mode entry point and returns the results.
2729 Transfers control to a 16-bit real mode entry point and returns the results.
2730 AsmPrepareThunk16() must be called with ThunkContext before this function is used.
2731 This function must be called with interrupts disabled.
2733 The register state from the RealModeState field of ThunkContext is restored just prior
2734 to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState,
2735 which is used to set the interrupt state when a 16-bit real mode entry point is called.
2736 Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.
2737 The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to
2738 the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.
2739 The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,
2740 so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment
2741 and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry
2742 point must exit with a RETF instruction. The register state is captured into RealModeState immediately
2743 after the RETF instruction is executed.
2745 If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
2746 or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure
2747 the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.
2749 If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
2750 then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.
2751 This includes the base vectors, the interrupt masks, and the edge/level trigger mode.
2753 If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code
2754 is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.
2756 If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
2757 ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to
2758 disable the A20 mask.
2760 If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in
2761 ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails,
2762 then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
2764 If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in
2765 ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
2767 If ThunkContext is NULL, then ASSERT().
2768 If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().
2769 If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
2770 ThunkAttributes, then ASSERT().
2772 This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
2773 virtual to physical mappings for ThunkContext.RealModeBuffer are mapped 1:1.
2775 @param ThunkContext A pointer to the context structure that describes the
2776 16-bit real mode code to call.
2782 IN OUT THUNK_CONTEXT
*ThunkContext
2785 gUnitTestHostBaseLib
.X86
->AsmThunk16 (ThunkContext
);
2789 Prepares all structures and code for a 16-bit real mode thunk, transfers
2790 control to a 16-bit real mode entry point, and returns the results.
2792 Prepares all structures and code for a 16-bit real mode thunk, transfers
2793 control to a 16-bit real mode entry point, and returns the results. If the
2794 caller only need to perform a single 16-bit real mode thunk, then this
2795 service should be used. If the caller intends to make more than one 16-bit
2796 real mode thunk, then it is more efficient if AsmPrepareThunk16() is called
2797 once and AsmThunk16() can be called for each 16-bit real mode thunk.
2799 This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
2800 virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
2802 See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.
2804 @param ThunkContext A pointer to the context structure that describes the
2805 16-bit real mode code to call.
2810 AsmPrepareAndThunk16 (
2811 IN OUT THUNK_CONTEXT
*ThunkContext
2814 gUnitTestHostBaseLib
.X86
->AsmPrepareAndThunk16 (ThunkContext
);
2818 Load given selector into TR register.
2820 @param[in] Selector Task segment selector
2828 gUnitTestHostBaseLib
.X86
->AsmWriteTr (Selector
);
2832 Performs a serializing operation on all load-from-memory instructions that
2833 were issued prior the AsmLfence function.
2835 Executes a LFENCE instruction. This function is only available on IA-32 and x64.
2844 gUnitTestHostBaseLib
.X86
->AsmLfence ();
2848 Patch the immediate operand of an IA32 or X64 instruction such that the byte,
2849 word, dword or qword operand is encoded at the end of the instruction's
2850 binary representation.
2852 This function should be used to update object code that was compiled with
2853 NASM from assembly source code. Example:
2857 mov eax, strict dword 0 ; the imm32 zero operand will be patched
2863 X86_ASSEMBLY_PATCH_LABEL gPatchCr3;
2864 PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);
2866 @param[out] InstructionEnd Pointer right past the instruction to patch. The
2867 immediate operand to patch is expected to
2868 comprise the trailing bytes of the instruction.
2869 If InstructionEnd is closer to address 0 than
2870 ValueSize permits, then ASSERT().
2872 @param[in] PatchValue The constant to write to the immediate operand.
2873 The caller is responsible for ensuring that
2874 PatchValue can be represented in the byte, word,
2875 dword or qword operand (as indicated through
2876 ValueSize); otherwise ASSERT().
2878 @param[in] ValueSize The size of the operand in bytes; must be 1, 2,
2879 4, or 8. ASSERT() otherwise.
2883 PatchInstructionX86 (
2884 OUT X86_ASSEMBLY_PATCH_LABEL
*InstructionEnd
,
2885 IN UINT64 PatchValue
,
2889 gUnitTestHostBaseLib
.X86
->PatchInstructionX86 (InstructionEnd
, PatchValue
, ValueSize
);
2895 STATIC UNIT_TEST_HOST_BASE_LIB_COMMON mUnitTestHostBaseLibCommon
= {
2896 UnitTestHostBaseLibEnableInterrupts
,
2897 UnitTestHostBaseLibDisableInterrupts
,
2898 UnitTestHostBaseLibEnableDisableInterrupts
,
2899 UnitTestHostBaseLibGetInterruptState
,
2903 /// IA32/X64 services
2905 STATIC UNIT_TEST_HOST_BASE_LIB_X86 mUnitTestHostBaseLibX86
= {
2906 UnitTestHostBaseLibAsmCpuid
,
2907 UnitTestHostBaseLibAsmCpuidEx
,
2908 UnitTestHostBaseLibAsmDisableCache
,
2909 UnitTestHostBaseLibAsmEnableCache
,
2910 UnitTestHostBaseLibAsmReadMsr64
,
2911 UnitTestHostBaseLibAsmWriteMsr64
,
2912 UnitTestHostBaseLibAsmReadCr0
,
2913 UnitTestHostBaseLibAsmReadCr2
,
2914 UnitTestHostBaseLibAsmReadCr3
,
2915 UnitTestHostBaseLibAsmReadCr4
,
2916 UnitTestHostBaseLibAsmWriteCr0
,
2917 UnitTestHostBaseLibAsmWriteCr2
,
2918 UnitTestHostBaseLibAsmWriteCr3
,
2919 UnitTestHostBaseLibAsmWriteCr4
,
2920 UnitTestHostBaseLibAsmReadDr0
,
2921 UnitTestHostBaseLibAsmReadDr1
,
2922 UnitTestHostBaseLibAsmReadDr2
,
2923 UnitTestHostBaseLibAsmReadDr3
,
2924 UnitTestHostBaseLibAsmReadDr4
,
2925 UnitTestHostBaseLibAsmReadDr5
,
2926 UnitTestHostBaseLibAsmReadDr6
,
2927 UnitTestHostBaseLibAsmReadDr7
,
2928 UnitTestHostBaseLibAsmWriteDr0
,
2929 UnitTestHostBaseLibAsmWriteDr1
,
2930 UnitTestHostBaseLibAsmWriteDr2
,
2931 UnitTestHostBaseLibAsmWriteDr3
,
2932 UnitTestHostBaseLibAsmWriteDr4
,
2933 UnitTestHostBaseLibAsmWriteDr5
,
2934 UnitTestHostBaseLibAsmWriteDr6
,
2935 UnitTestHostBaseLibAsmWriteDr7
,
2936 UnitTestHostBaseLibAsmReadCs
,
2937 UnitTestHostBaseLibAsmReadDs
,
2938 UnitTestHostBaseLibAsmReadEs
,
2939 UnitTestHostBaseLibAsmReadFs
,
2940 UnitTestHostBaseLibAsmReadGs
,
2941 UnitTestHostBaseLibAsmReadSs
,
2942 UnitTestHostBaseLibAsmReadTr
,
2943 UnitTestHostBaseLibAsmReadGdtr
,
2944 UnitTestHostBaseLibAsmWriteGdtr
,
2945 UnitTestHostBaseLibAsmReadIdtr
,
2946 UnitTestHostBaseLibAsmWriteIdtr
,
2947 UnitTestHostBaseLibAsmReadLdtr
,
2948 UnitTestHostBaseLibAsmWriteLdtr
,
2949 UnitTestHostBaseLibAsmReadPmc
,
2950 UnitTestHostBaseLibAsmMonitor
,
2951 UnitTestHostBaseLibAsmMwait
,
2952 UnitTestHostBaseLibAsmWbinvd
,
2953 UnitTestHostBaseLibAsmInvd
,
2954 UnitTestHostBaseLibAsmFlushCacheLine
,
2955 UnitTestHostBaseLibAsmEnablePaging32
,
2956 UnitTestHostBaseLibAsmDisablePaging32
,
2957 UnitTestHostBaseLibAsmEnablePaging64
,
2958 UnitTestHostBaseLibAsmDisablePaging64
,
2959 UnitTestHostBaseLibAsmGetThunk16Properties
,
2960 UnitTestHostBaseLibAsmPrepareThunk16
,
2961 UnitTestHostBaseLibAsmThunk16
,
2962 UnitTestHostBaseLibAsmPrepareAndThunk16
,
2963 UnitTestHostBaseLibAsmWriteTr
,
2964 UnitTestHostBaseLibAsmLfence
,
2965 UnitTestHostBaseLibPatchInstructionX86
2969 /// Structure of hook functions for BaseLib functions that can not be used from
2970 /// a host application. A simple emulation of these function is provided by
2971 /// default. A specific unit test can provide its own implementation for any
2972 /// of these functions.
2974 UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib
= {
2975 &mUnitTestHostBaseLibCommon
,
2976 &mUnitTestHostBaseLibX86