]>
git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BasePciExpressLib/PciExpressLib.c
2 Functions in this library instance make use of MMIO functions in IoLib to
3 access memory mapped PCI configuration space.
5 All assertions for I/O operations are handled in MMIO functions in the IoLib
8 Copyright (c) 2006 - 2008, Intel Corporation<BR>
9 All rights reserved. This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 #include <Library/BaseLib.h>
23 #include <Library/PciExpressLib.h>
24 #include <Library/IoLib.h>
25 #include <Library/DebugLib.h>
26 #include <Library/PcdLib.h>
30 Assert the validity of a PCI address. A valid PCI address should contain 1's
31 only in the low 28 bits.
33 @param A The address to validate.
36 #define ASSERT_INVALID_PCI_ADDRESS(A) \
37 ASSERT (((A) & ~0xfffffff) == 0)
40 Register a PCI device so PCI configuration registers may be accessed after
41 SetVirtualAddressMap().
43 If Address > 0x0FFFFFFF, then ASSERT().
45 @param Address Address that encodes the PCI Bus, Device, Function and
48 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
49 @retval RETURN_UNSUPPORTED An attempt was made to call this function
50 after ExitBootServices().
51 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
52 at runtime could not be mapped.
53 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
54 complete the registration.
59 PciExpressRegisterForRuntimeAccess (
63 return RETURN_UNSUPPORTED
;
67 Gets the base address of PCI Express.
69 This internal functions retrieves PCI Express Base Address via a PCD entry
70 PcdPciExpressBaseAddress.
72 @return The base address of PCI Express.
76 GetPciExpressBaseAddress (
80 return (VOID
*)(UINTN
) PcdGet64 (PcdPciExpressBaseAddress
);
84 Reads an 8-bit PCI configuration register.
86 Reads and returns the 8-bit PCI configuration register specified by Address.
87 This function must guarantee that all PCI read and write operations are
90 If Address > 0x0FFFFFFF, then ASSERT().
92 @param Address Address that encodes the PCI Bus, Device, Function and
95 @return The read value from the PCI configuration register.
104 ASSERT_INVALID_PCI_ADDRESS (Address
);
105 return MmioRead8 ((UINTN
) GetPciExpressBaseAddress () + Address
);
109 Writes an 8-bit PCI configuration register.
111 Writes the 8-bit PCI configuration register specified by Address with the
112 value specified by Value. Value is returned. This function must guarantee
113 that all PCI read and write operations are serialized.
115 If Address > 0x0FFFFFFF, then ASSERT().
117 @param Address Address that encodes the PCI Bus, Device, Function and
119 @param Value The value to write.
121 @return The value written to the PCI configuration register.
131 ASSERT_INVALID_PCI_ADDRESS (Address
);
132 return MmioWrite8 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
136 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
139 Reads the 8-bit PCI configuration register specified by Address, performs a
140 bitwise inclusive OR between the read result and the value specified by
141 OrData, and writes the result to the 8-bit PCI configuration register
142 specified by Address. The value written to the PCI configuration register is
143 returned. This function must guarantee that all PCI read and write operations
146 If Address > 0x0FFFFFFF, then ASSERT().
148 @param Address Address that encodes the PCI Bus, Device, Function and
150 @param OrData The value to OR with the PCI configuration register.
152 @return The value written back to the PCI configuration register.
162 ASSERT_INVALID_PCI_ADDRESS (Address
);
163 return MmioOr8 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
167 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
170 Reads the 8-bit PCI configuration register specified by Address, performs a
171 bitwise AND between the read result and the value specified by AndData, and
172 writes the result to the 8-bit PCI configuration register specified by
173 Address. The value written to the PCI configuration register is returned.
174 This function must guarantee that all PCI read and write operations are
177 If Address > 0x0FFFFFFF, then ASSERT().
179 @param Address Address that encodes the PCI Bus, Device, Function and
181 @param AndData The value to AND with the PCI configuration register.
183 @return The value written back to the PCI configuration register.
193 ASSERT_INVALID_PCI_ADDRESS (Address
);
194 return MmioAnd8 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
198 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
199 value, followed a bitwise inclusive OR with another 8-bit value.
201 Reads the 8-bit PCI configuration register specified by Address, performs a
202 bitwise AND between the read result and the value specified by AndData,
203 performs a bitwise inclusive OR between the result of the AND operation and
204 the value specified by OrData, and writes the result to the 8-bit PCI
205 configuration register specified by Address. The value written to the PCI
206 configuration register is returned. This function must guarantee that all PCI
207 read and write operations are serialized.
209 If Address > 0x0FFFFFFF, then ASSERT().
211 @param Address Address that encodes the PCI Bus, Device, Function and
213 @param AndData The value to AND with the PCI configuration register.
214 @param OrData The value to OR with the result of the AND operation.
216 @return The value written back to the PCI configuration register.
221 PciExpressAndThenOr8 (
227 ASSERT_INVALID_PCI_ADDRESS (Address
);
228 return MmioAndThenOr8 (
229 (UINTN
) GetPciExpressBaseAddress () + Address
,
236 Reads a bit field of a PCI configuration register.
238 Reads the bit field in an 8-bit PCI configuration register. The bit field is
239 specified by the StartBit and the EndBit. The value of the bit field is
242 If Address > 0x0FFFFFFF, then ASSERT().
243 If StartBit is greater than 7, then ASSERT().
244 If EndBit is greater than 7, then ASSERT().
245 If EndBit is less than StartBit, then ASSERT().
247 @param Address PCI configuration register to read.
248 @param StartBit The ordinal of the least significant bit in the bit field.
250 @param EndBit The ordinal of the most significant bit in the bit field.
253 @return The value of the bit field read from the PCI configuration register.
258 PciExpressBitFieldRead8 (
264 ASSERT_INVALID_PCI_ADDRESS (Address
);
265 return MmioBitFieldRead8 (
266 (UINTN
) GetPciExpressBaseAddress () + Address
,
273 Writes a bit field to a PCI configuration register.
275 Writes Value to the bit field of the PCI configuration register. The bit
276 field is specified by the StartBit and the EndBit. All other bits in the
277 destination PCI configuration register are preserved. The new value of the
278 8-bit register is returned.
280 If Address > 0x0FFFFFFF, then ASSERT().
281 If StartBit is greater than 7, then ASSERT().
282 If EndBit is greater than 7, then ASSERT().
283 If EndBit is less than StartBit, then ASSERT().
285 @param Address PCI configuration register to write.
286 @param StartBit The ordinal of the least significant bit in the bit field.
288 @param EndBit The ordinal of the most significant bit in the bit field.
290 @param Value New value of the bit field.
292 @return The value written back to the PCI configuration register.
297 PciExpressBitFieldWrite8 (
304 ASSERT_INVALID_PCI_ADDRESS (Address
);
305 return MmioBitFieldWrite8 (
306 (UINTN
) GetPciExpressBaseAddress () + Address
,
314 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
315 writes the result back to the bit field in the 8-bit port.
317 Reads the 8-bit PCI configuration register specified by Address, performs a
318 bitwise inclusive OR between the read result and the value specified by
319 OrData, and writes the result to the 8-bit PCI configuration register
320 specified by Address. The value written to the PCI configuration register is
321 returned. This function must guarantee that all PCI read and write operations
322 are serialized. Extra left bits in OrData are stripped.
324 If Address > 0x0FFFFFFF, then ASSERT().
325 If StartBit is greater than 7, then ASSERT().
326 If EndBit is greater than 7, then ASSERT().
327 If EndBit is less than StartBit, then ASSERT().
329 @param Address PCI configuration register to write.
330 @param StartBit The ordinal of the least significant bit in the bit field.
332 @param EndBit The ordinal of the most significant bit in the bit field.
334 @param OrData The value to OR with the PCI configuration register.
336 @return The value written back to the PCI configuration register.
341 PciExpressBitFieldOr8 (
348 ASSERT_INVALID_PCI_ADDRESS (Address
);
349 return MmioBitFieldOr8 (
350 (UINTN
) GetPciExpressBaseAddress () + Address
,
358 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
359 AND, and writes the result back to the bit field in the 8-bit register.
361 Reads the 8-bit PCI configuration register specified by Address, performs a
362 bitwise AND between the read result and the value specified by AndData, and
363 writes the result to the 8-bit PCI configuration register specified by
364 Address. The value written to the PCI configuration register is returned.
365 This function must guarantee that all PCI read and write operations are
366 serialized. Extra left bits in AndData are stripped.
368 If Address > 0x0FFFFFFF, then ASSERT().
369 If StartBit is greater than 7, then ASSERT().
370 If EndBit is greater than 7, then ASSERT().
371 If EndBit is less than StartBit, then ASSERT().
373 @param Address PCI configuration register to write.
374 @param StartBit The ordinal of the least significant bit in the bit field.
376 @param EndBit The ordinal of the most significant bit in the bit field.
378 @param AndData The value to AND with the PCI configuration register.
380 @return The value written back to the PCI configuration register.
385 PciExpressBitFieldAnd8 (
392 ASSERT_INVALID_PCI_ADDRESS (Address
);
393 return MmioBitFieldAnd8 (
394 (UINTN
) GetPciExpressBaseAddress () + Address
,
402 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
403 bitwise inclusive OR, and writes the result back to the bit field in the
406 Reads the 8-bit PCI configuration register specified by Address, performs a
407 bitwise AND followed by a bitwise inclusive OR between the read result and
408 the value specified by AndData, and writes the result to the 8-bit PCI
409 configuration register specified by Address. The value written to the PCI
410 configuration register is returned. This function must guarantee that all PCI
411 read and write operations are serialized. Extra left bits in both AndData and
414 If Address > 0x0FFFFFFF, then ASSERT().
415 If StartBit is greater than 7, then ASSERT().
416 If EndBit is greater than 7, then ASSERT().
417 If EndBit is less than StartBit, then ASSERT().
419 @param Address PCI configuration register to write.
420 @param StartBit The ordinal of the least significant bit in the bit field.
422 @param EndBit The ordinal of the most significant bit in the bit field.
424 @param AndData The value to AND with the PCI configuration register.
425 @param OrData The value to OR with the result of the AND operation.
427 @return The value written back to the PCI configuration register.
432 PciExpressBitFieldAndThenOr8 (
440 ASSERT_INVALID_PCI_ADDRESS (Address
);
441 return MmioBitFieldAndThenOr8 (
442 (UINTN
) GetPciExpressBaseAddress () + Address
,
451 Reads a 16-bit PCI configuration register.
453 Reads and returns the 16-bit PCI configuration register specified by Address.
454 This function must guarantee that all PCI read and write operations are
457 If Address > 0x0FFFFFFF, then ASSERT().
458 If Address is not aligned on a 16-bit boundary, then ASSERT().
460 @param Address Address that encodes the PCI Bus, Device, Function and
463 @return The read value from the PCI configuration register.
472 ASSERT_INVALID_PCI_ADDRESS (Address
);
473 return MmioRead16 ((UINTN
) GetPciExpressBaseAddress () + Address
);
477 Writes a 16-bit PCI configuration register.
479 Writes the 16-bit PCI configuration register specified by Address with the
480 value specified by Value. Value is returned. This function must guarantee
481 that all PCI read and write operations are serialized.
483 If Address > 0x0FFFFFFF, then ASSERT().
484 If Address is not aligned on a 16-bit boundary, then ASSERT().
486 @param Address Address that encodes the PCI Bus, Device, Function and
488 @param Value The value to write.
490 @return The value written to the PCI configuration register.
500 ASSERT_INVALID_PCI_ADDRESS (Address
);
501 return MmioWrite16 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
505 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
508 Reads the 16-bit PCI configuration register specified by Address, performs a
509 bitwise inclusive OR between the read result and the value specified by
510 OrData, and writes the result to the 16-bit PCI configuration register
511 specified by Address. The value written to the PCI configuration register is
512 returned. This function must guarantee that all PCI read and write operations
515 If Address > 0x0FFFFFFF, then ASSERT().
516 If Address is not aligned on a 16-bit boundary, then ASSERT().
518 @param Address Address that encodes the PCI Bus, Device, Function and
520 @param OrData The value to OR with the PCI configuration register.
522 @return The value written back to the PCI configuration register.
532 ASSERT_INVALID_PCI_ADDRESS (Address
);
533 return MmioOr16 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
537 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
540 Reads the 16-bit PCI configuration register specified by Address, performs a
541 bitwise AND between the read result and the value specified by AndData, and
542 writes the result to the 16-bit PCI configuration register specified by
543 Address. The value written to the PCI configuration register is returned.
544 This function must guarantee that all PCI read and write operations are
547 If Address > 0x0FFFFFFF, then ASSERT().
548 If Address is not aligned on a 16-bit boundary, then ASSERT().
550 @param Address Address that encodes the PCI Bus, Device, Function and
552 @param AndData The value to AND with the PCI configuration register.
554 @return The value written back to the PCI configuration register.
564 ASSERT_INVALID_PCI_ADDRESS (Address
);
565 return MmioAnd16 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
569 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
570 value, followed a bitwise inclusive OR with another 16-bit value.
572 Reads the 16-bit PCI configuration register specified by Address, performs a
573 bitwise AND between the read result and the value specified by AndData,
574 performs a bitwise inclusive OR between the result of the AND operation and
575 the value specified by OrData, and writes the result to the 16-bit PCI
576 configuration register specified by Address. The value written to the PCI
577 configuration register is returned. This function must guarantee that all PCI
578 read and write operations are serialized.
580 If Address > 0x0FFFFFFF, then ASSERT().
581 If Address is not aligned on a 16-bit boundary, then ASSERT().
583 @param Address Address that encodes the PCI Bus, Device, Function and
585 @param AndData The value to AND with the PCI configuration register.
586 @param OrData The value to OR with the result of the AND operation.
588 @return The value written back to the PCI configuration register.
593 PciExpressAndThenOr16 (
599 ASSERT_INVALID_PCI_ADDRESS (Address
);
600 return MmioAndThenOr16 (
601 (UINTN
) GetPciExpressBaseAddress () + Address
,
608 Reads a bit field of a PCI configuration register.
610 Reads the bit field in a 16-bit PCI configuration register. The bit field is
611 specified by the StartBit and the EndBit. The value of the bit field is
614 If Address > 0x0FFFFFFF, then ASSERT().
615 If Address is not aligned on a 16-bit boundary, then ASSERT().
616 If StartBit is greater than 15, then ASSERT().
617 If EndBit is greater than 15, then ASSERT().
618 If EndBit is less than StartBit, then ASSERT().
620 @param Address PCI configuration register to read.
621 @param StartBit The ordinal of the least significant bit in the bit field.
623 @param EndBit The ordinal of the most significant bit in the bit field.
626 @return The value of the bit field read from the PCI configuration register.
631 PciExpressBitFieldRead16 (
637 ASSERT_INVALID_PCI_ADDRESS (Address
);
638 return MmioBitFieldRead16 (
639 (UINTN
) GetPciExpressBaseAddress () + Address
,
646 Writes a bit field to a PCI configuration register.
648 Writes Value to the bit field of the PCI configuration register. The bit
649 field is specified by the StartBit and the EndBit. All other bits in the
650 destination PCI configuration register are preserved. The new value of the
651 16-bit register is returned.
653 If Address > 0x0FFFFFFF, then ASSERT().
654 If Address is not aligned on a 16-bit boundary, then ASSERT().
655 If StartBit is greater than 15, then ASSERT().
656 If EndBit is greater than 15, then ASSERT().
657 If EndBit is less than StartBit, then ASSERT().
659 @param Address PCI configuration register to write.
660 @param StartBit The ordinal of the least significant bit in the bit field.
662 @param EndBit The ordinal of the most significant bit in the bit field.
664 @param Value New value of the bit field.
666 @return The value written back to the PCI configuration register.
671 PciExpressBitFieldWrite16 (
678 ASSERT_INVALID_PCI_ADDRESS (Address
);
679 return MmioBitFieldWrite16 (
680 (UINTN
) GetPciExpressBaseAddress () + Address
,
688 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
689 writes the result back to the bit field in the 16-bit port.
691 Reads the 16-bit PCI configuration register specified by Address, performs a
692 bitwise inclusive OR between the read result and the value specified by
693 OrData, and writes the result to the 16-bit PCI configuration register
694 specified by Address. The value written to the PCI configuration register is
695 returned. This function must guarantee that all PCI read and write operations
696 are serialized. Extra left bits in OrData are stripped.
698 If Address > 0x0FFFFFFF, then ASSERT().
699 If Address is not aligned on a 16-bit boundary, then ASSERT().
700 If StartBit is greater than 15, then ASSERT().
701 If EndBit is greater than 15, then ASSERT().
702 If EndBit is less than StartBit, then ASSERT().
704 @param Address PCI configuration register to write.
705 @param StartBit The ordinal of the least significant bit in the bit field.
707 @param EndBit The ordinal of the most significant bit in the bit field.
709 @param OrData The value to OR with the PCI configuration register.
711 @return The value written back to the PCI configuration register.
716 PciExpressBitFieldOr16 (
723 ASSERT_INVALID_PCI_ADDRESS (Address
);
724 return MmioBitFieldOr16 (
725 (UINTN
) GetPciExpressBaseAddress () + Address
,
733 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
734 AND, and writes the result back to the bit field in the 16-bit register.
736 Reads the 16-bit PCI configuration register specified by Address, performs a
737 bitwise AND between the read result and the value specified by AndData, and
738 writes the result to the 16-bit PCI configuration register specified by
739 Address. The value written to the PCI configuration register is returned.
740 This function must guarantee that all PCI read and write operations are
741 serialized. Extra left bits in AndData are stripped.
743 If Address > 0x0FFFFFFF, then ASSERT().
744 If Address is not aligned on a 16-bit boundary, then ASSERT().
745 If StartBit is greater than 15, then ASSERT().
746 If EndBit is greater than 15, then ASSERT().
747 If EndBit is less than StartBit, then ASSERT().
749 @param Address PCI configuration register to write.
750 @param StartBit The ordinal of the least significant bit in the bit field.
752 @param EndBit The ordinal of the most significant bit in the bit field.
754 @param AndData The value to AND with the PCI configuration register.
756 @return The value written back to the PCI configuration register.
761 PciExpressBitFieldAnd16 (
768 ASSERT_INVALID_PCI_ADDRESS (Address
);
769 return MmioBitFieldAnd16 (
770 (UINTN
) GetPciExpressBaseAddress () + Address
,
778 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
779 bitwise inclusive OR, and writes the result back to the bit field in the
782 Reads the 16-bit PCI configuration register specified by Address, performs a
783 bitwise AND followed by a bitwise inclusive OR between the read result and
784 the value specified by AndData, and writes the result to the 16-bit PCI
785 configuration register specified by Address. The value written to the PCI
786 configuration register is returned. This function must guarantee that all PCI
787 read and write operations are serialized. Extra left bits in both AndData and
790 If Address > 0x0FFFFFFF, then ASSERT().
791 If Address is not aligned on a 16-bit boundary, then ASSERT().
792 If StartBit is greater than 15, then ASSERT().
793 If EndBit is greater than 15, then ASSERT().
794 If EndBit is less than StartBit, then ASSERT().
796 @param Address PCI configuration register to write.
797 @param StartBit The ordinal of the least significant bit in the bit field.
799 @param EndBit The ordinal of the most significant bit in the bit field.
801 @param AndData The value to AND with the PCI configuration register.
802 @param OrData The value to OR with the result of the AND operation.
804 @return The value written back to the PCI configuration register.
809 PciExpressBitFieldAndThenOr16 (
817 ASSERT_INVALID_PCI_ADDRESS (Address
);
818 return MmioBitFieldAndThenOr16 (
819 (UINTN
) GetPciExpressBaseAddress () + Address
,
828 Reads a 32-bit PCI configuration register.
830 Reads and returns the 32-bit PCI configuration register specified by Address.
831 This function must guarantee that all PCI read and write operations are
834 If Address > 0x0FFFFFFF, then ASSERT().
835 If Address is not aligned on a 32-bit boundary, then ASSERT().
837 @param Address Address that encodes the PCI Bus, Device, Function and
840 @return The read value from the PCI configuration register.
849 ASSERT_INVALID_PCI_ADDRESS (Address
);
850 return MmioRead32 ((UINTN
) GetPciExpressBaseAddress () + Address
);
854 Writes a 32-bit PCI configuration register.
856 Writes the 32-bit PCI configuration register specified by Address with the
857 value specified by Value. Value is returned. This function must guarantee
858 that all PCI read and write operations are serialized.
860 If Address > 0x0FFFFFFF, then ASSERT().
861 If Address is not aligned on a 32-bit boundary, then ASSERT().
863 @param Address Address that encodes the PCI Bus, Device, Function and
865 @param Value The value to write.
867 @return The value written to the PCI configuration register.
877 ASSERT_INVALID_PCI_ADDRESS (Address
);
878 return MmioWrite32 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
882 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
885 Reads the 32-bit PCI configuration register specified by Address, performs a
886 bitwise inclusive OR between the read result and the value specified by
887 OrData, and writes the result to the 32-bit PCI configuration register
888 specified by Address. The value written to the PCI configuration register is
889 returned. This function must guarantee that all PCI read and write operations
892 If Address > 0x0FFFFFFF, then ASSERT().
893 If Address is not aligned on a 32-bit boundary, then ASSERT().
895 @param Address Address that encodes the PCI Bus, Device, Function and
897 @param OrData The value to OR with the PCI configuration register.
899 @return The value written back to the PCI configuration register.
909 ASSERT_INVALID_PCI_ADDRESS (Address
);
910 return MmioOr32 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
914 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
917 Reads the 32-bit PCI configuration register specified by Address, performs a
918 bitwise AND between the read result and the value specified by AndData, and
919 writes the result to the 32-bit PCI configuration register specified by
920 Address. The value written to the PCI configuration register is returned.
921 This function must guarantee that all PCI read and write operations are
924 If Address > 0x0FFFFFFF, then ASSERT().
925 If Address is not aligned on a 32-bit boundary, then ASSERT().
927 @param Address Address that encodes the PCI Bus, Device, Function and
929 @param AndData The value to AND with the PCI configuration register.
931 @return The value written back to the PCI configuration register.
941 ASSERT_INVALID_PCI_ADDRESS (Address
);
942 return MmioAnd32 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
946 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
947 value, followed a bitwise inclusive OR with another 32-bit value.
949 Reads the 32-bit PCI configuration register specified by Address, performs a
950 bitwise AND between the read result and the value specified by AndData,
951 performs a bitwise inclusive OR between the result of the AND operation and
952 the value specified by OrData, and writes the result to the 32-bit PCI
953 configuration register specified by Address. The value written to the PCI
954 configuration register is returned. This function must guarantee that all PCI
955 read and write operations are serialized.
957 If Address > 0x0FFFFFFF, then ASSERT().
958 If Address is not aligned on a 32-bit boundary, then ASSERT().
960 @param Address Address that encodes the PCI Bus, Device, Function and
962 @param AndData The value to AND with the PCI configuration register.
963 @param OrData The value to OR with the result of the AND operation.
965 @return The value written back to the PCI configuration register.
970 PciExpressAndThenOr32 (
976 ASSERT_INVALID_PCI_ADDRESS (Address
);
977 return MmioAndThenOr32 (
978 (UINTN
) GetPciExpressBaseAddress () + Address
,
985 Reads a bit field of a PCI configuration register.
987 Reads the bit field in a 32-bit PCI configuration register. The bit field is
988 specified by the StartBit and the EndBit. The value of the bit field is
991 If Address > 0x0FFFFFFF, then ASSERT().
992 If Address is not aligned on a 32-bit boundary, then ASSERT().
993 If StartBit is greater than 31, then ASSERT().
994 If EndBit is greater than 31, then ASSERT().
995 If EndBit is less than StartBit, then ASSERT().
997 @param Address PCI configuration register to read.
998 @param StartBit The ordinal of the least significant bit in the bit field.
1000 @param EndBit The ordinal of the most significant bit in the bit field.
1003 @return The value of the bit field read from the PCI configuration register.
1008 PciExpressBitFieldRead32 (
1014 ASSERT_INVALID_PCI_ADDRESS (Address
);
1015 return MmioBitFieldRead32 (
1016 (UINTN
) GetPciExpressBaseAddress () + Address
,
1023 Writes a bit field to a PCI configuration register.
1025 Writes Value to the bit field of the PCI configuration register. The bit
1026 field is specified by the StartBit and the EndBit. All other bits in the
1027 destination PCI configuration register are preserved. The new value of the
1028 32-bit register is returned.
1030 If Address > 0x0FFFFFFF, then ASSERT().
1031 If Address is not aligned on a 32-bit boundary, then ASSERT().
1032 If StartBit is greater than 31, then ASSERT().
1033 If EndBit is greater than 31, then ASSERT().
1034 If EndBit is less than StartBit, then ASSERT().
1036 @param Address PCI configuration register to write.
1037 @param StartBit The ordinal of the least significant bit in the bit field.
1039 @param EndBit The ordinal of the most significant bit in the bit field.
1041 @param Value New value of the bit field.
1043 @return The value written back to the PCI configuration register.
1048 PciExpressBitFieldWrite32 (
1055 ASSERT_INVALID_PCI_ADDRESS (Address
);
1056 return MmioBitFieldWrite32 (
1057 (UINTN
) GetPciExpressBaseAddress () + Address
,
1065 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1066 writes the result back to the bit field in the 32-bit port.
1068 Reads the 32-bit PCI configuration register specified by Address, performs a
1069 bitwise inclusive OR between the read result and the value specified by
1070 OrData, and writes the result to the 32-bit PCI configuration register
1071 specified by Address. The value written to the PCI configuration register is
1072 returned. This function must guarantee that all PCI read and write operations
1073 are serialized. Extra left bits in OrData are stripped.
1075 If Address > 0x0FFFFFFF, then ASSERT().
1076 If Address is not aligned on a 32-bit boundary, then ASSERT().
1077 If StartBit is greater than 31, then ASSERT().
1078 If EndBit is greater than 31, then ASSERT().
1079 If EndBit is less than StartBit, then ASSERT().
1081 @param Address PCI configuration register to write.
1082 @param StartBit The ordinal of the least significant bit in the bit field.
1084 @param EndBit The ordinal of the most significant bit in the bit field.
1086 @param OrData The value to OR with the PCI configuration register.
1088 @return The value written back to the PCI configuration register.
1093 PciExpressBitFieldOr32 (
1100 ASSERT_INVALID_PCI_ADDRESS (Address
);
1101 return MmioBitFieldOr32 (
1102 (UINTN
) GetPciExpressBaseAddress () + Address
,
1110 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1111 AND, and writes the result back to the bit field in the 32-bit register.
1113 Reads the 32-bit PCI configuration register specified by Address, performs a
1114 bitwise AND between the read result and the value specified by AndData, and
1115 writes the result to the 32-bit PCI configuration register specified by
1116 Address. The value written to the PCI configuration register is returned.
1117 This function must guarantee that all PCI read and write operations are
1118 serialized. Extra left bits in AndData are stripped.
1120 If Address > 0x0FFFFFFF, then ASSERT().
1121 If Address is not aligned on a 32-bit boundary, then ASSERT().
1122 If StartBit is greater than 31, then ASSERT().
1123 If EndBit is greater than 31, then ASSERT().
1124 If EndBit is less than StartBit, then ASSERT().
1126 @param Address PCI configuration register to write.
1127 @param StartBit The ordinal of the least significant bit in the bit field.
1129 @param EndBit The ordinal of the most significant bit in the bit field.
1131 @param AndData The value to AND with the PCI configuration register.
1133 @return The value written back to the PCI configuration register.
1138 PciExpressBitFieldAnd32 (
1145 ASSERT_INVALID_PCI_ADDRESS (Address
);
1146 return MmioBitFieldAnd32 (
1147 (UINTN
) GetPciExpressBaseAddress () + Address
,
1155 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1156 bitwise inclusive OR, and writes the result back to the bit field in the
1159 Reads the 32-bit PCI configuration register specified by Address, performs a
1160 bitwise AND followed by a bitwise inclusive OR between the read result and
1161 the value specified by AndData, and writes the result to the 32-bit PCI
1162 configuration register specified by Address. The value written to the PCI
1163 configuration register is returned. This function must guarantee that all PCI
1164 read and write operations are serialized. Extra left bits in both AndData and
1165 OrData are stripped.
1167 If Address > 0x0FFFFFFF, then ASSERT().
1168 If Address is not aligned on a 32-bit boundary, then ASSERT().
1169 If StartBit is greater than 31, then ASSERT().
1170 If EndBit is greater than 31, then ASSERT().
1171 If EndBit is less than StartBit, then ASSERT().
1173 @param Address PCI configuration register to write.
1174 @param StartBit The ordinal of the least significant bit in the bit field.
1176 @param EndBit The ordinal of the most significant bit in the bit field.
1178 @param AndData The value to AND with the PCI configuration register.
1179 @param OrData The value to OR with the result of the AND operation.
1181 @return The value written back to the PCI configuration register.
1186 PciExpressBitFieldAndThenOr32 (
1194 ASSERT_INVALID_PCI_ADDRESS (Address
);
1195 return MmioBitFieldAndThenOr32 (
1196 (UINTN
) GetPciExpressBaseAddress () + Address
,
1205 Reads a range of PCI configuration registers into a caller supplied buffer.
1207 Reads the range of PCI configuration registers specified by StartAddress and
1208 Size into the buffer specified by Buffer. This function only allows the PCI
1209 configuration registers from a single PCI function to be read. Size is
1210 returned. When possible 32-bit PCI configuration read cycles are used to read
1211 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1212 and 16-bit PCI configuration read cycles may be used at the beginning and the
1215 If StartAddress > 0x0FFFFFFF, then ASSERT().
1216 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1217 If Size > 0 and Buffer is NULL, then ASSERT().
1219 @param StartAddress Starting address that encodes the PCI Bus, Device,
1220 Function and Register.
1221 @param Size Size in bytes of the transfer.
1222 @param Buffer Pointer to a buffer receiving the data read.
1224 @return Size read data from StartAddress.
1229 PciExpressReadBuffer (
1230 IN UINTN StartAddress
,
1237 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1238 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1244 ASSERT (Buffer
!= NULL
);
1247 // Save Size for return
1251 if ((StartAddress
& 1) != 0) {
1253 // Read a byte if StartAddress is byte aligned
1255 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1256 StartAddress
+= sizeof (UINT8
);
1257 Size
-= sizeof (UINT8
);
1258 Buffer
= (UINT8
*)Buffer
+ 1;
1261 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1263 // Read a word if StartAddress is word aligned
1265 WriteUnaligned16 ((UINT16
*) Buffer
, (UINT16
) PciExpressRead16 (StartAddress
));
1267 StartAddress
+= sizeof (UINT16
);
1268 Size
-= sizeof (UINT16
);
1269 Buffer
= (UINT16
*)Buffer
+ 1;
1272 while (Size
>= sizeof (UINT32
)) {
1274 // Read as many double words as possible
1276 WriteUnaligned32 ((UINT32
*) Buffer
, (UINT32
) PciExpressRead32 (StartAddress
));
1278 StartAddress
+= sizeof (UINT32
);
1279 Size
-= sizeof (UINT32
);
1280 Buffer
= (UINT32
*)Buffer
+ 1;
1283 if (Size
>= sizeof (UINT16
)) {
1285 // Read the last remaining word if exist
1287 WriteUnaligned16 ((UINT16
*) Buffer
, (UINT16
) PciExpressRead16 (StartAddress
));
1288 StartAddress
+= sizeof (UINT16
);
1289 Size
-= sizeof (UINT16
);
1290 Buffer
= (UINT16
*)Buffer
+ 1;
1293 if (Size
>= sizeof (UINT8
)) {
1295 // Read the last remaining byte if exist
1297 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1304 Copies the data in a caller supplied buffer to a specified range of PCI
1305 configuration space.
1307 Writes the range of PCI configuration registers specified by StartAddress and
1308 Size from the buffer specified by Buffer. This function only allows the PCI
1309 configuration registers from a single PCI function to be written. Size is
1310 returned. When possible 32-bit PCI configuration write cycles are used to
1311 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1312 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1313 and the end of the range.
1315 If StartAddress > 0x0FFFFFFF, then ASSERT().
1316 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1317 If Size > 0 and Buffer is NULL, then ASSERT().
1319 @param StartAddress Starting address that encodes the PCI Bus, Device,
1320 Function and Register.
1321 @param Size Size in bytes of the transfer.
1322 @param Buffer Pointer to a buffer containing the data to write.
1324 @return Size written to StartAddress.
1329 PciExpressWriteBuffer (
1330 IN UINTN StartAddress
,
1337 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1338 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1344 ASSERT (Buffer
!= NULL
);
1347 // Save Size for return
1351 if ((StartAddress
& 1) != 0) {
1353 // Write a byte if StartAddress is byte aligned
1355 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1356 StartAddress
+= sizeof (UINT8
);
1357 Size
-= sizeof (UINT8
);
1358 Buffer
= (UINT8
*)Buffer
+ 1;
1361 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1363 // Write a word if StartAddress is word aligned
1365 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1366 StartAddress
+= sizeof (UINT16
);
1367 Size
-= sizeof (UINT16
);
1368 Buffer
= (UINT16
*)Buffer
+ 1;
1371 while (Size
>= sizeof (UINT32
)) {
1373 // Write as many double words as possible
1375 PciExpressWrite32 (StartAddress
, ReadUnaligned32 ((UINT32
*)Buffer
));
1376 StartAddress
+= sizeof (UINT32
);
1377 Size
-= sizeof (UINT32
);
1378 Buffer
= (UINT32
*)Buffer
+ 1;
1381 if (Size
>= sizeof (UINT16
)) {
1383 // Write the last remaining word if exist
1385 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1386 StartAddress
+= sizeof (UINT16
);
1387 Size
-= sizeof (UINT16
);
1388 Buffer
= (UINT16
*)Buffer
+ 1;
1391 if (Size
>= sizeof (UINT8
)) {
1393 // Write the last remaining byte if exist
1395 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);