3003613486a9bce2906c1de844a80d543890e8ca
[mirror_edk2.git] / MdePkg / Library / BasePciExpressLib / PciLib.c
1 /** @file
2 PCI Library.
3
4 Functions in this library instance make use of MMIO functions in IoLib to
5 access memory mapped PCI configuration space.
6
7 All assertions for I/O operations are handled in MMIO functions in the IoLib
8 Library.
9
10 Copyright (c) 2006, Intel Corporation<BR>
11 All rights reserved. This program and the accompanying materials
12 are licensed and made available under the terms and conditions of the BSD License
13 which accompanies this distribution. The full text of the license may be found at
14 http://opensource.org/licenses/bsd-license.php
15
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18
19 Module Name: PciLib.c
20
21 **/
22
23 /**
24 Assert the validity of a PCI address. A valid PCI address should contain 1's
25 only in the low 28 bits.
26
27 @param A The address to validate.
28
29 **/
30 #define ASSERT_INVALID_PCI_ADDRESS(A) \
31 ASSERT (((A) & ~0xfffffff) == 0)
32
33
34 UINTN
35 EFIAPI
36 GetPciExpressBaseAddress (
37 VOID
38 )
39 {
40 return (UINTN)PcdGet64 (PcdPciExpressBaseAddress);
41 }
42
43 /**
44 Reads an 8-bit PCI configuration register.
45
46 Reads and returns the 8-bit PCI configuration register specified by Address.
47 This function must guarantee that all PCI read and write operations are
48 serialized.
49
50 If Address > 0x0FFFFFFF, then ASSERT().
51
52 @param Address Address that encodes the PCI Bus, Device, Function and
53 Register.
54
55 @return The read value from the PCI configuration register.
56
57 **/
58 UINT8
59 EFIAPI
60 PciExpressRead8 (
61 IN UINTN Address
62 )
63 {
64 ASSERT_INVALID_PCI_ADDRESS (Address);
65 return MmioRead8 (GetPciExpressBaseAddress () + Address);
66 }
67
68 /**
69 Writes an 8-bit PCI configuration register.
70
71 Writes the 8-bit PCI configuration register specified by Address with the
72 value specified by Value. Value is returned. This function must guarantee
73 that all PCI read and write operations are serialized.
74
75 If Address > 0x0FFFFFFF, then ASSERT().
76
77 @param Address Address that encodes the PCI Bus, Device, Function and
78 Register.
79 @param Value The value to write.
80
81 @return The value written to the PCI configuration register.
82
83 **/
84 UINT8
85 EFIAPI
86 PciExpressWrite8 (
87 IN UINTN Address,
88 IN UINT8 Value
89 )
90 {
91 ASSERT_INVALID_PCI_ADDRESS (Address);
92 return MmioWrite8 (GetPciExpressBaseAddress () + Address, Value);
93 }
94
95 /**
96 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
97 an 8-bit value.
98
99 Reads the 8-bit PCI configuration register specified by Address, performs a
100 bitwise inclusive OR between the read result and the value specified by
101 OrData, and writes the result to the 8-bit PCI configuration register
102 specified by Address. The value written to the PCI configuration register is
103 returned. This function must guarantee that all PCI read and write operations
104 are serialized.
105
106 If Address > 0x0FFFFFFF, then ASSERT().
107
108 @param Address Address that encodes the PCI Bus, Device, Function and
109 Register.
110 @param OrData The value to OR with the PCI configuration register.
111
112 @return The value written back to the PCI configuration register.
113
114 **/
115 UINT8
116 EFIAPI
117 PciExpressOr8 (
118 IN UINTN Address,
119 IN UINT8 OrData
120 )
121 {
122 ASSERT_INVALID_PCI_ADDRESS (Address);
123 return MmioOr8 (GetPciExpressBaseAddress () + Address, OrData);
124 }
125
126 /**
127 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
128 value.
129
130 Reads the 8-bit PCI configuration register specified by Address, performs a
131 bitwise AND between the read result and the value specified by AndData, and
132 writes the result to the 8-bit PCI configuration register specified by
133 Address. The value written to the PCI configuration register is returned.
134 This function must guarantee that all PCI read and write operations are
135 serialized.
136
137 If Address > 0x0FFFFFFF, then ASSERT().
138
139 @param Address Address that encodes the PCI Bus, Device, Function and
140 Register.
141 @param AndData The value to AND with the PCI configuration register.
142
143 @return The value written back to the PCI configuration register.
144
145 **/
146 UINT8
147 EFIAPI
148 PciExpressAnd8 (
149 IN UINTN Address,
150 IN UINT8 AndData
151 )
152 {
153 ASSERT_INVALID_PCI_ADDRESS (Address);
154 return MmioAnd8 (GetPciExpressBaseAddress () + Address, AndData);
155 }
156
157 /**
158 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
159 value, followed a bitwise inclusive OR with another 8-bit value.
160
161 Reads the 8-bit PCI configuration register specified by Address, performs a
162 bitwise AND between the read result and the value specified by AndData,
163 performs a bitwise inclusive OR between the result of the AND operation and
164 the value specified by OrData, and writes the result to the 8-bit PCI
165 configuration register specified by Address. The value written to the PCI
166 configuration register is returned. This function must guarantee that all PCI
167 read and write operations are serialized.
168
169 If Address > 0x0FFFFFFF, then ASSERT().
170
171 @param Address Address that encodes the PCI Bus, Device, Function and
172 Register.
173 @param AndData The value to AND with the PCI configuration register.
174 @param OrData The value to OR with the result of the AND operation.
175
176 @return The value written back to the PCI configuration register.
177
178 **/
179 UINT8
180 EFIAPI
181 PciExpressAndThenOr8 (
182 IN UINTN Address,
183 IN UINT8 AndData,
184 IN UINT8 OrData
185 )
186 {
187 ASSERT_INVALID_PCI_ADDRESS (Address);
188 return MmioAndThenOr8 (
189 GetPciExpressBaseAddress () + Address,
190 AndData,
191 OrData
192 );
193 }
194
195 /**
196 Reads a bit field of a PCI configuration register.
197
198 Reads the bit field in an 8-bit PCI configuration register. The bit field is
199 specified by the StartBit and the EndBit. The value of the bit field is
200 returned.
201
202 If Address > 0x0FFFFFFF, then ASSERT().
203 If StartBit is greater than 7, then ASSERT().
204 If EndBit is greater than 7, then ASSERT().
205 If EndBit is less than or equal to StartBit, then ASSERT().
206
207 @param Address PCI configuration register to read.
208 @param StartBit The ordinal of the least significant bit in the bit field.
209 Range 0..7.
210 @param EndBit The ordinal of the most significant bit in the bit field.
211 Range 0..7.
212
213 @return The value of the bit field read from the PCI configuration register.
214
215 **/
216 UINT8
217 EFIAPI
218 PciExpressBitFieldRead8 (
219 IN UINTN Address,
220 IN UINTN StartBit,
221 IN UINTN EndBit
222 )
223 {
224 ASSERT_INVALID_PCI_ADDRESS (Address);
225 return MmioBitFieldRead8 (
226 GetPciExpressBaseAddress () + Address,
227 StartBit,
228 EndBit
229 );
230 }
231
232 /**
233 Writes a bit field to a PCI configuration register.
234
235 Writes Value to the bit field of the PCI configuration register. The bit
236 field is specified by the StartBit and the EndBit. All other bits in the
237 destination PCI configuration register are preserved. The new value of the
238 8-bit register is returned.
239
240 If Address > 0x0FFFFFFF, then ASSERT().
241 If StartBit is greater than 7, then ASSERT().
242 If EndBit is greater than 7, then ASSERT().
243 If EndBit is less than or equal to StartBit, then ASSERT().
244
245 @param Address PCI configuration register to write.
246 @param StartBit The ordinal of the least significant bit in the bit field.
247 Range 0..7.
248 @param EndBit The ordinal of the most significant bit in the bit field.
249 Range 0..7.
250 @param Value New value of the bit field.
251
252 @return The value written back to the PCI configuration register.
253
254 **/
255 UINT8
256 EFIAPI
257 PciExpressBitFieldWrite8 (
258 IN UINTN Address,
259 IN UINTN StartBit,
260 IN UINTN EndBit,
261 IN UINT8 Value
262 )
263 {
264 ASSERT_INVALID_PCI_ADDRESS (Address);
265 return MmioBitFieldWrite8 (
266 GetPciExpressBaseAddress () + Address,
267 StartBit,
268 EndBit,
269 Value
270 );
271 }
272
273 /**
274 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
275 writes the result back to the bit field in the 8-bit port.
276
277 Reads the 8-bit PCI configuration register specified by Address, performs a
278 bitwise inclusive OR between the read result and the value specified by
279 OrData, and writes the result to the 8-bit PCI configuration register
280 specified by Address. The value written to the PCI configuration register is
281 returned. This function must guarantee that all PCI read and write operations
282 are serialized. Extra left bits in OrData are stripped.
283
284 If Address > 0x0FFFFFFF, then ASSERT().
285 If StartBit is greater than 7, then ASSERT().
286 If EndBit is greater than 7, then ASSERT().
287 If EndBit is less than or equal to StartBit, then ASSERT().
288
289 @param Address PCI configuration register to write.
290 @param StartBit The ordinal of the least significant bit in the bit field.
291 Range 0..7.
292 @param EndBit The ordinal of the most significant bit in the bit field.
293 Range 0..7.
294 @param OrData The value to OR with the PCI configuration register.
295
296 @return The value written back to the PCI configuration register.
297
298 **/
299 UINT8
300 EFIAPI
301 PciExpressBitFieldOr8 (
302 IN UINTN Address,
303 IN UINTN StartBit,
304 IN UINTN EndBit,
305 IN UINT8 OrData
306 )
307 {
308 ASSERT_INVALID_PCI_ADDRESS (Address);
309 return MmioBitFieldOr8 (
310 GetPciExpressBaseAddress () + Address,
311 StartBit,
312 EndBit,
313 OrData
314 );
315 }
316
317 /**
318 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
319 AND, and writes the result back to the bit field in the 8-bit register.
320
321 Reads the 8-bit PCI configuration register specified by Address, performs a
322 bitwise AND between the read result and the value specified by AndData, and
323 writes the result to the 8-bit PCI configuration register specified by
324 Address. The value written to the PCI configuration register is returned.
325 This function must guarantee that all PCI read and write operations are
326 serialized. Extra left bits in AndData are stripped.
327
328 If Address > 0x0FFFFFFF, then ASSERT().
329 If StartBit is greater than 7, then ASSERT().
330 If EndBit is greater than 7, then ASSERT().
331 If EndBit is less than or equal to StartBit, then ASSERT().
332
333 @param Address PCI configuration register to write.
334 @param StartBit The ordinal of the least significant bit in the bit field.
335 Range 0..7.
336 @param EndBit The ordinal of the most significant bit in the bit field.
337 Range 0..7.
338 @param AndData The value to AND with the PCI configuration register.
339
340 @return The value written back to the PCI configuration register.
341
342 **/
343 UINT8
344 EFIAPI
345 PciExpressBitFieldAnd8 (
346 IN UINTN Address,
347 IN UINTN StartBit,
348 IN UINTN EndBit,
349 IN UINT8 AndData
350 )
351 {
352 ASSERT_INVALID_PCI_ADDRESS (Address);
353 return MmioBitFieldAnd8 (
354 GetPciExpressBaseAddress () + Address,
355 StartBit,
356 EndBit,
357 AndData
358 );
359 }
360
361 /**
362 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
363 bitwise inclusive OR, and writes the result back to the bit field in the
364 8-bit port.
365
366 Reads the 8-bit PCI configuration register specified by Address, performs a
367 bitwise AND followed by a bitwise inclusive OR between the read result and
368 the value specified by AndData, and writes the result to the 8-bit PCI
369 configuration register specified by Address. The value written to the PCI
370 configuration register is returned. This function must guarantee that all PCI
371 read and write operations are serialized. Extra left bits in both AndData and
372 OrData are stripped.
373
374 If Address > 0x0FFFFFFF, then ASSERT().
375 If StartBit is greater than 7, then ASSERT().
376 If EndBit is greater than 7, then ASSERT().
377 If EndBit is less than or equal to StartBit, then ASSERT().
378
379 @param Address PCI configuration register to write.
380 @param StartBit The ordinal of the least significant bit in the bit field.
381 Range 0..7.
382 @param EndBit The ordinal of the most significant bit in the bit field.
383 Range 0..7.
384 @param AndData The value to AND with the PCI configuration register.
385 @param OrData The value to OR with the result of the AND operation.
386
387 @return The value written back to the PCI configuration register.
388
389 **/
390 UINT8
391 EFIAPI
392 PciExpressBitFieldAndThenOr8 (
393 IN UINTN Address,
394 IN UINTN StartBit,
395 IN UINTN EndBit,
396 IN UINT8 AndData,
397 IN UINT8 OrData
398 )
399 {
400 ASSERT_INVALID_PCI_ADDRESS (Address);
401 return MmioBitFieldAndThenOr8 (
402 GetPciExpressBaseAddress () + Address,
403 StartBit,
404 EndBit,
405 AndData,
406 OrData
407 );
408 }
409
410 /**
411 Reads a 16-bit PCI configuration register.
412
413 Reads and returns the 16-bit PCI configuration register specified by Address.
414 This function must guarantee that all PCI read and write operations are
415 serialized.
416
417 If Address > 0x0FFFFFFF, then ASSERT().
418 If Address is not aligned on a 16-bit boundary, then ASSERT().
419
420 @param Address Address that encodes the PCI Bus, Device, Function and
421 Register.
422
423 @return The read value from the PCI configuration register.
424
425 **/
426 UINT16
427 EFIAPI
428 PciExpressRead16 (
429 IN UINTN Address
430 )
431 {
432 ASSERT_INVALID_PCI_ADDRESS (Address);
433 return MmioRead16 (GetPciExpressBaseAddress () + Address);
434 }
435
436 /**
437 Writes a 16-bit PCI configuration register.
438
439 Writes the 16-bit PCI configuration register specified by Address with the
440 value specified by Value. Value is returned. This function must guarantee
441 that all PCI read and write operations are serialized.
442
443 If Address > 0x0FFFFFFF, then ASSERT().
444 If Address is not aligned on a 16-bit boundary, then ASSERT().
445
446 @param Address Address that encodes the PCI Bus, Device, Function and
447 Register.
448 @param Value The value to write.
449
450 @return The value written to the PCI configuration register.
451
452 **/
453 UINT16
454 EFIAPI
455 PciExpressWrite16 (
456 IN UINTN Address,
457 IN UINT16 Value
458 )
459 {
460 ASSERT_INVALID_PCI_ADDRESS (Address);
461 return MmioWrite16 (GetPciExpressBaseAddress () + Address, Value);
462 }
463
464 /**
465 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
466 a 16-bit value.
467
468 Reads the 16-bit PCI configuration register specified by Address, performs a
469 bitwise inclusive OR between the read result and the value specified by
470 OrData, and writes the result to the 16-bit PCI configuration register
471 specified by Address. The value written to the PCI configuration register is
472 returned. This function must guarantee that all PCI read and write operations
473 are serialized.
474
475 If Address > 0x0FFFFFFF, then ASSERT().
476 If Address is not aligned on a 16-bit boundary, then ASSERT().
477
478 @param Address Address that encodes the PCI Bus, Device, Function and
479 Register.
480 @param OrData The value to OR with the PCI configuration register.
481
482 @return The value written back to the PCI configuration register.
483
484 **/
485 UINT16
486 EFIAPI
487 PciExpressOr16 (
488 IN UINTN Address,
489 IN UINT16 OrData
490 )
491 {
492 ASSERT_INVALID_PCI_ADDRESS (Address);
493 return MmioOr16 (GetPciExpressBaseAddress () + Address, OrData);
494 }
495
496 /**
497 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
498 value.
499
500 Reads the 16-bit PCI configuration register specified by Address, performs a
501 bitwise AND between the read result and the value specified by AndData, and
502 writes the result to the 16-bit PCI configuration register specified by
503 Address. The value written to the PCI configuration register is returned.
504 This function must guarantee that all PCI read and write operations are
505 serialized.
506
507 If Address > 0x0FFFFFFF, then ASSERT().
508 If Address is not aligned on a 16-bit boundary, then ASSERT().
509
510 @param Address Address that encodes the PCI Bus, Device, Function and
511 Register.
512 @param AndData The value to AND with the PCI configuration register.
513
514 @return The value written back to the PCI configuration register.
515
516 **/
517 UINT16
518 EFIAPI
519 PciExpressAnd16 (
520 IN UINTN Address,
521 IN UINT16 AndData
522 )
523 {
524 ASSERT_INVALID_PCI_ADDRESS (Address);
525 return MmioAnd16 (GetPciExpressBaseAddress () + Address, AndData);
526 }
527
528 /**
529 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
530 value, followed a bitwise inclusive OR with another 16-bit value.
531
532 Reads the 16-bit PCI configuration register specified by Address, performs a
533 bitwise AND between the read result and the value specified by AndData,
534 performs a bitwise inclusive OR between the result of the AND operation and
535 the value specified by OrData, and writes the result to the 16-bit PCI
536 configuration register specified by Address. The value written to the PCI
537 configuration register is returned. This function must guarantee that all PCI
538 read and write operations are serialized.
539
540 If Address > 0x0FFFFFFF, then ASSERT().
541 If Address is not aligned on a 16-bit boundary, then ASSERT().
542
543 @param Address Address that encodes the PCI Bus, Device, Function and
544 Register.
545 @param AndData The value to AND with the PCI configuration register.
546 @param OrData The value to OR with the result of the AND operation.
547
548 @return The value written back to the PCI configuration register.
549
550 **/
551 UINT16
552 EFIAPI
553 PciExpressAndThenOr16 (
554 IN UINTN Address,
555 IN UINT16 AndData,
556 IN UINT16 OrData
557 )
558 {
559 ASSERT_INVALID_PCI_ADDRESS (Address);
560 return MmioAndThenOr16 (
561 GetPciExpressBaseAddress () + Address,
562 AndData,
563 OrData
564 );
565 }
566
567 /**
568 Reads a bit field of a PCI configuration register.
569
570 Reads the bit field in a 16-bit PCI configuration register. The bit field is
571 specified by the StartBit and the EndBit. The value of the bit field is
572 returned.
573
574 If Address > 0x0FFFFFFF, then ASSERT().
575 If Address is not aligned on a 16-bit boundary, then ASSERT().
576 If StartBit is greater than 15, then ASSERT().
577 If EndBit is greater than 15, then ASSERT().
578 If EndBit is less than or equal to StartBit, then ASSERT().
579
580 @param Address PCI configuration register to read.
581 @param StartBit The ordinal of the least significant bit in the bit field.
582 Range 0..15.
583 @param EndBit The ordinal of the most significant bit in the bit field.
584 Range 0..15.
585
586 @return The value of the bit field read from the PCI configuration register.
587
588 **/
589 UINT16
590 EFIAPI
591 PciExpressBitFieldRead16 (
592 IN UINTN Address,
593 IN UINTN StartBit,
594 IN UINTN EndBit
595 )
596 {
597 ASSERT_INVALID_PCI_ADDRESS (Address);
598 return MmioBitFieldRead16 (
599 GetPciExpressBaseAddress () + Address,
600 StartBit,
601 EndBit
602 );
603 }
604
605 /**
606 Writes a bit field to a PCI configuration register.
607
608 Writes Value to the bit field of the PCI configuration register. The bit
609 field is specified by the StartBit and the EndBit. All other bits in the
610 destination PCI configuration register are preserved. The new value of the
611 16-bit register is returned.
612
613 If Address > 0x0FFFFFFF, then ASSERT().
614 If Address is not aligned on a 16-bit boundary, then ASSERT().
615 If StartBit is greater than 15, then ASSERT().
616 If EndBit is greater than 15, then ASSERT().
617 If EndBit is less than or equal to StartBit, then ASSERT().
618
619 @param Address PCI configuration register to write.
620 @param StartBit The ordinal of the least significant bit in the bit field.
621 Range 0..15.
622 @param EndBit The ordinal of the most significant bit in the bit field.
623 Range 0..15.
624 @param Value New value of the bit field.
625
626 @return The value written back to the PCI configuration register.
627
628 **/
629 UINT16
630 EFIAPI
631 PciExpressBitFieldWrite16 (
632 IN UINTN Address,
633 IN UINTN StartBit,
634 IN UINTN EndBit,
635 IN UINT16 Value
636 )
637 {
638 ASSERT_INVALID_PCI_ADDRESS (Address);
639 return MmioBitFieldWrite16 (
640 GetPciExpressBaseAddress () + Address,
641 StartBit,
642 EndBit,
643 Value
644 );
645 }
646
647 /**
648 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
649 writes the result back to the bit field in the 16-bit port.
650
651 Reads the 16-bit PCI configuration register specified by Address, performs a
652 bitwise inclusive OR between the read result and the value specified by
653 OrData, and writes the result to the 16-bit PCI configuration register
654 specified by Address. The value written to the PCI configuration register is
655 returned. This function must guarantee that all PCI read and write operations
656 are serialized. Extra left bits in OrData are stripped.
657
658 If Address > 0x0FFFFFFF, then ASSERT().
659 If Address is not aligned on a 16-bit boundary, then ASSERT().
660 If StartBit is greater than 15, then ASSERT().
661 If EndBit is greater than 15, then ASSERT().
662 If EndBit is less than or equal to StartBit, then ASSERT().
663
664 @param Address PCI configuration register to write.
665 @param StartBit The ordinal of the least significant bit in the bit field.
666 Range 0..15.
667 @param EndBit The ordinal of the most significant bit in the bit field.
668 Range 0..15.
669 @param OrData The value to OR with the PCI configuration register.
670
671 @return The value written back to the PCI configuration register.
672
673 **/
674 UINT16
675 EFIAPI
676 PciExpressBitFieldOr16 (
677 IN UINTN Address,
678 IN UINTN StartBit,
679 IN UINTN EndBit,
680 IN UINT16 OrData
681 )
682 {
683 ASSERT_INVALID_PCI_ADDRESS (Address);
684 return MmioBitFieldOr16 (
685 GetPciExpressBaseAddress () + Address,
686 StartBit,
687 EndBit,
688 OrData
689 );
690 }
691
692 /**
693 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
694 AND, and writes the result back to the bit field in the 16-bit register.
695
696 Reads the 16-bit PCI configuration register specified by Address, performs a
697 bitwise AND between the read result and the value specified by AndData, and
698 writes the result to the 16-bit PCI configuration register specified by
699 Address. The value written to the PCI configuration register is returned.
700 This function must guarantee that all PCI read and write operations are
701 serialized. Extra left bits in AndData are stripped.
702
703 If Address > 0x0FFFFFFF, then ASSERT().
704 If Address is not aligned on a 16-bit boundary, then ASSERT().
705 If StartBit is greater than 15, then ASSERT().
706 If EndBit is greater than 15, then ASSERT().
707 If EndBit is less than or equal to StartBit, then ASSERT().
708
709 @param Address PCI configuration register to write.
710 @param StartBit The ordinal of the least significant bit in the bit field.
711 Range 0..15.
712 @param EndBit The ordinal of the most significant bit in the bit field.
713 Range 0..15.
714 @param AndData The value to AND with the PCI configuration register.
715
716 @return The value written back to the PCI configuration register.
717
718 **/
719 UINT16
720 EFIAPI
721 PciExpressBitFieldAnd16 (
722 IN UINTN Address,
723 IN UINTN StartBit,
724 IN UINTN EndBit,
725 IN UINT16 AndData
726 )
727 {
728 ASSERT_INVALID_PCI_ADDRESS (Address);
729 return MmioBitFieldAnd16 (
730 GetPciExpressBaseAddress () + Address,
731 StartBit,
732 EndBit,
733 AndData
734 );
735 }
736
737 /**
738 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
739 bitwise inclusive OR, and writes the result back to the bit field in the
740 16-bit port.
741
742 Reads the 16-bit PCI configuration register specified by Address, performs a
743 bitwise AND followed by a bitwise inclusive OR between the read result and
744 the value specified by AndData, and writes the result to the 16-bit PCI
745 configuration register specified by Address. The value written to the PCI
746 configuration register is returned. This function must guarantee that all PCI
747 read and write operations are serialized. Extra left bits in both AndData and
748 OrData are stripped.
749
750 If Address > 0x0FFFFFFF, then ASSERT().
751 If Address is not aligned on a 16-bit boundary, then ASSERT().
752 If StartBit is greater than 15, then ASSERT().
753 If EndBit is greater than 15, then ASSERT().
754 If EndBit is less than or equal to StartBit, then ASSERT().
755
756 @param Address PCI configuration register to write.
757 @param StartBit The ordinal of the least significant bit in the bit field.
758 Range 0..15.
759 @param EndBit The ordinal of the most significant bit in the bit field.
760 Range 0..15.
761 @param AndData The value to AND with the PCI configuration register.
762 @param OrData The value to OR with the result of the AND operation.
763
764 @return The value written back to the PCI configuration register.
765
766 **/
767 UINT16
768 EFIAPI
769 PciExpressBitFieldAndThenOr16 (
770 IN UINTN Address,
771 IN UINTN StartBit,
772 IN UINTN EndBit,
773 IN UINT16 AndData,
774 IN UINT16 OrData
775 )
776 {
777 ASSERT_INVALID_PCI_ADDRESS (Address);
778 return MmioBitFieldAndThenOr16 (
779 GetPciExpressBaseAddress () + Address,
780 StartBit,
781 EndBit,
782 AndData,
783 OrData
784 );
785 }
786
787 /**
788 Reads a 32-bit PCI configuration register.
789
790 Reads and returns the 32-bit PCI configuration register specified by Address.
791 This function must guarantee that all PCI read and write operations are
792 serialized.
793
794 If Address > 0x0FFFFFFF, then ASSERT().
795 If Address is not aligned on a 32-bit boundary, then ASSERT().
796
797 @param Address Address that encodes the PCI Bus, Device, Function and
798 Register.
799
800 @return The read value from the PCI configuration register.
801
802 **/
803 UINT32
804 EFIAPI
805 PciExpressRead32 (
806 IN UINTN Address
807 )
808 {
809 ASSERT_INVALID_PCI_ADDRESS (Address);
810 return MmioRead32 (GetPciExpressBaseAddress () + Address);
811 }
812
813 /**
814 Writes a 32-bit PCI configuration register.
815
816 Writes the 32-bit PCI configuration register specified by Address with the
817 value specified by Value. Value is returned. This function must guarantee
818 that all PCI read and write operations are serialized.
819
820 If Address > 0x0FFFFFFF, then ASSERT().
821 If Address is not aligned on a 32-bit boundary, then ASSERT().
822
823 @param Address Address that encodes the PCI Bus, Device, Function and
824 Register.
825 @param Value The value to write.
826
827 @return The value written to the PCI configuration register.
828
829 **/
830 UINT32
831 EFIAPI
832 PciExpressWrite32 (
833 IN UINTN Address,
834 IN UINT32 Value
835 )
836 {
837 ASSERT_INVALID_PCI_ADDRESS (Address);
838 return MmioWrite32 (GetPciExpressBaseAddress () + Address, Value);
839 }
840
841 /**
842 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
843 a 32-bit value.
844
845 Reads the 32-bit PCI configuration register specified by Address, performs a
846 bitwise inclusive OR between the read result and the value specified by
847 OrData, and writes the result to the 32-bit PCI configuration register
848 specified by Address. The value written to the PCI configuration register is
849 returned. This function must guarantee that all PCI read and write operations
850 are serialized.
851
852 If Address > 0x0FFFFFFF, then ASSERT().
853 If Address is not aligned on a 32-bit boundary, then ASSERT().
854
855 @param Address Address that encodes the PCI Bus, Device, Function and
856 Register.
857 @param OrData The value to OR with the PCI configuration register.
858
859 @return The value written back to the PCI configuration register.
860
861 **/
862 UINT32
863 EFIAPI
864 PciExpressOr32 (
865 IN UINTN Address,
866 IN UINT32 OrData
867 )
868 {
869 ASSERT_INVALID_PCI_ADDRESS (Address);
870 return MmioOr32 (GetPciExpressBaseAddress () + Address, OrData);
871 }
872
873 /**
874 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
875 value.
876
877 Reads the 32-bit PCI configuration register specified by Address, performs a
878 bitwise AND between the read result and the value specified by AndData, and
879 writes the result to the 32-bit PCI configuration register specified by
880 Address. The value written to the PCI configuration register is returned.
881 This function must guarantee that all PCI read and write operations are
882 serialized.
883
884 If Address > 0x0FFFFFFF, then ASSERT().
885 If Address is not aligned on a 32-bit boundary, then ASSERT().
886
887 @param Address Address that encodes the PCI Bus, Device, Function and
888 Register.
889 @param AndData The value to AND with the PCI configuration register.
890
891 @return The value written back to the PCI configuration register.
892
893 **/
894 UINT32
895 EFIAPI
896 PciExpressAnd32 (
897 IN UINTN Address,
898 IN UINT32 AndData
899 )
900 {
901 ASSERT_INVALID_PCI_ADDRESS (Address);
902 return MmioAnd32 (GetPciExpressBaseAddress () + Address, AndData);
903 }
904
905 /**
906 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
907 value, followed a bitwise inclusive OR with another 32-bit value.
908
909 Reads the 32-bit PCI configuration register specified by Address, performs a
910 bitwise AND between the read result and the value specified by AndData,
911 performs a bitwise inclusive OR between the result of the AND operation and
912 the value specified by OrData, and writes the result to the 32-bit PCI
913 configuration register specified by Address. The value written to the PCI
914 configuration register is returned. This function must guarantee that all PCI
915 read and write operations are serialized.
916
917 If Address > 0x0FFFFFFF, then ASSERT().
918 If Address is not aligned on a 32-bit boundary, then ASSERT().
919
920 @param Address Address that encodes the PCI Bus, Device, Function and
921 Register.
922 @param AndData The value to AND with the PCI configuration register.
923 @param OrData The value to OR with the result of the AND operation.
924
925 @return The value written back to the PCI configuration register.
926
927 **/
928 UINT32
929 EFIAPI
930 PciExpressAndThenOr32 (
931 IN UINTN Address,
932 IN UINT32 AndData,
933 IN UINT32 OrData
934 )
935 {
936 ASSERT_INVALID_PCI_ADDRESS (Address);
937 return MmioAndThenOr32 (
938 GetPciExpressBaseAddress () + Address,
939 AndData,
940 OrData
941 );
942 }
943
944 /**
945 Reads a bit field of a PCI configuration register.
946
947 Reads the bit field in a 32-bit PCI configuration register. The bit field is
948 specified by the StartBit and the EndBit. The value of the bit field is
949 returned.
950
951 If Address > 0x0FFFFFFF, then ASSERT().
952 If Address is not aligned on a 32-bit boundary, then ASSERT().
953 If StartBit is greater than 31, then ASSERT().
954 If EndBit is greater than 31, then ASSERT().
955 If EndBit is less than or equal to StartBit, then ASSERT().
956
957 @param Address PCI configuration register to read.
958 @param StartBit The ordinal of the least significant bit in the bit field.
959 Range 0..31.
960 @param EndBit The ordinal of the most significant bit in the bit field.
961 Range 0..31.
962
963 @return The value of the bit field read from the PCI configuration register.
964
965 **/
966 UINT32
967 EFIAPI
968 PciExpressBitFieldRead32 (
969 IN UINTN Address,
970 IN UINTN StartBit,
971 IN UINTN EndBit
972 )
973 {
974 ASSERT_INVALID_PCI_ADDRESS (Address);
975 return MmioBitFieldRead32 (
976 GetPciExpressBaseAddress () + Address,
977 StartBit,
978 EndBit
979 );
980 }
981
982 /**
983 Writes a bit field to a PCI configuration register.
984
985 Writes Value to the bit field of the PCI configuration register. The bit
986 field is specified by the StartBit and the EndBit. All other bits in the
987 destination PCI configuration register are preserved. The new value of the
988 32-bit register is returned.
989
990 If Address > 0x0FFFFFFF, then ASSERT().
991 If Address is not aligned on a 32-bit boundary, then ASSERT().
992 If StartBit is greater than 31, then ASSERT().
993 If EndBit is greater than 31, then ASSERT().
994 If EndBit is less than or equal to StartBit, then ASSERT().
995
996 @param Address PCI configuration register to write.
997 @param StartBit The ordinal of the least significant bit in the bit field.
998 Range 0..31.
999 @param EndBit The ordinal of the most significant bit in the bit field.
1000 Range 0..31.
1001 @param Value New value of the bit field.
1002
1003 @return The value written back to the PCI configuration register.
1004
1005 **/
1006 UINT32
1007 EFIAPI
1008 PciExpressBitFieldWrite32 (
1009 IN UINTN Address,
1010 IN UINTN StartBit,
1011 IN UINTN EndBit,
1012 IN UINT32 Value
1013 )
1014 {
1015 ASSERT_INVALID_PCI_ADDRESS (Address);
1016 return MmioBitFieldWrite32 (
1017 GetPciExpressBaseAddress () + Address,
1018 StartBit,
1019 EndBit,
1020 Value
1021 );
1022 }
1023
1024 /**
1025 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1026 writes the result back to the bit field in the 32-bit port.
1027
1028 Reads the 32-bit PCI configuration register specified by Address, performs a
1029 bitwise inclusive OR between the read result and the value specified by
1030 OrData, and writes the result to the 32-bit PCI configuration register
1031 specified by Address. The value written to the PCI configuration register is
1032 returned. This function must guarantee that all PCI read and write operations
1033 are serialized. Extra left bits in OrData are stripped.
1034
1035 If Address > 0x0FFFFFFF, then ASSERT().
1036 If Address is not aligned on a 32-bit boundary, then ASSERT().
1037 If StartBit is greater than 31, then ASSERT().
1038 If EndBit is greater than 31, then ASSERT().
1039 If EndBit is less than or equal to StartBit, then ASSERT().
1040
1041 @param Address PCI configuration register to write.
1042 @param StartBit The ordinal of the least significant bit in the bit field.
1043 Range 0..31.
1044 @param EndBit The ordinal of the most significant bit in the bit field.
1045 Range 0..31.
1046 @param OrData The value to OR with the PCI configuration register.
1047
1048 @return The value written back to the PCI configuration register.
1049
1050 **/
1051 UINT32
1052 EFIAPI
1053 PciExpressBitFieldOr32 (
1054 IN UINTN Address,
1055 IN UINTN StartBit,
1056 IN UINTN EndBit,
1057 IN UINT32 OrData
1058 )
1059 {
1060 ASSERT_INVALID_PCI_ADDRESS (Address);
1061 return MmioBitFieldOr32 (
1062 GetPciExpressBaseAddress () + Address,
1063 StartBit,
1064 EndBit,
1065 OrData
1066 );
1067 }
1068
1069 /**
1070 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1071 AND, and writes the result back to the bit field in the 32-bit register.
1072
1073 Reads the 32-bit PCI configuration register specified by Address, performs a
1074 bitwise AND between the read result and the value specified by AndData, and
1075 writes the result to the 32-bit PCI configuration register specified by
1076 Address. The value written to the PCI configuration register is returned.
1077 This function must guarantee that all PCI read and write operations are
1078 serialized. Extra left bits in AndData are stripped.
1079
1080 If Address > 0x0FFFFFFF, then ASSERT().
1081 If Address is not aligned on a 32-bit boundary, then ASSERT().
1082 If StartBit is greater than 31, then ASSERT().
1083 If EndBit is greater than 31, then ASSERT().
1084 If EndBit is less than or equal to StartBit, then ASSERT().
1085
1086 @param Address PCI configuration register to write.
1087 @param StartBit The ordinal of the least significant bit in the bit field.
1088 Range 0..31.
1089 @param EndBit The ordinal of the most significant bit in the bit field.
1090 Range 0..31.
1091 @param AndData The value to AND with the PCI configuration register.
1092
1093 @return The value written back to the PCI configuration register.
1094
1095 **/
1096 UINT32
1097 EFIAPI
1098 PciExpressBitFieldAnd32 (
1099 IN UINTN Address,
1100 IN UINTN StartBit,
1101 IN UINTN EndBit,
1102 IN UINT32 AndData
1103 )
1104 {
1105 ASSERT_INVALID_PCI_ADDRESS (Address);
1106 return MmioBitFieldAnd32 (
1107 GetPciExpressBaseAddress () + Address,
1108 StartBit,
1109 EndBit,
1110 AndData
1111 );
1112 }
1113
1114 /**
1115 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1116 bitwise inclusive OR, and writes the result back to the bit field in the
1117 32-bit port.
1118
1119 Reads the 32-bit PCI configuration register specified by Address, performs a
1120 bitwise AND followed by a bitwise inclusive OR between the read result and
1121 the value specified by AndData, and writes the result to the 32-bit PCI
1122 configuration register specified by Address. The value written to the PCI
1123 configuration register is returned. This function must guarantee that all PCI
1124 read and write operations are serialized. Extra left bits in both AndData and
1125 OrData are stripped.
1126
1127 If Address > 0x0FFFFFFF, then ASSERT().
1128 If Address is not aligned on a 32-bit boundary, then ASSERT().
1129 If StartBit is greater than 31, then ASSERT().
1130 If EndBit is greater than 31, then ASSERT().
1131 If EndBit is less than or equal to StartBit, then ASSERT().
1132
1133 @param Address PCI configuration register to write.
1134 @param StartBit The ordinal of the least significant bit in the bit field.
1135 Range 0..31.
1136 @param EndBit The ordinal of the most significant bit in the bit field.
1137 Range 0..31.
1138 @param AndData The value to AND with the PCI configuration register.
1139 @param OrData The value to OR with the result of the AND operation.
1140
1141 @return The value written back to the PCI configuration register.
1142
1143 **/
1144 UINT32
1145 EFIAPI
1146 PciExpressBitFieldAndThenOr32 (
1147 IN UINTN Address,
1148 IN UINTN StartBit,
1149 IN UINTN EndBit,
1150 IN UINT32 AndData,
1151 IN UINT32 OrData
1152 )
1153 {
1154 ASSERT_INVALID_PCI_ADDRESS (Address);
1155 return MmioBitFieldAndThenOr32 (
1156 GetPciExpressBaseAddress () + Address,
1157 StartBit,
1158 EndBit,
1159 AndData,
1160 OrData
1161 );
1162 }
1163
1164 /**
1165 Reads a range of PCI configuration registers into a caller supplied buffer.
1166
1167 Reads the range of PCI configuration registers specified by StartAddress and
1168 Size into the buffer specified by Buffer. This function only allows the PCI
1169 configuration registers from a single PCI function to be read. Size is
1170 returned. When possible 32-bit PCI configuration read cycles are used to read
1171 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1172 and 16-bit PCI configuration read cycles may be used at the beginning and the
1173 end of the range.
1174
1175 If StartAddress > 0x0FFFFFFF, then ASSERT().
1176 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1177 If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().
1178 If Buffer is NULL, then ASSERT().
1179
1180 @param StartAddress Starting address that encodes the PCI Bus, Device,
1181 Function and Register.
1182 @param Size Size in bytes of the transfer.
1183 @param Buffer Pointer to a buffer receiving the data read.
1184
1185 @return Size
1186
1187 **/
1188 UINTN
1189 EFIAPI
1190 PciExpressReadBuffer (
1191 IN UINTN StartAddress,
1192 IN UINTN Size,
1193 OUT VOID *Buffer
1194 )
1195 {
1196 UINTN EndAddress;
1197
1198 EndAddress = StartAddress + Size;
1199
1200 if (StartAddress < EndAddress && (StartAddress & 1)) {
1201 //
1202 // Read a byte if StartAddress is byte aligned
1203 //
1204 *(UINT8*)Buffer = PciExpressRead8 (StartAddress);
1205 StartAddress += sizeof (UINT8);
1206 Buffer = (UINT8*)Buffer + 1;
1207 }
1208
1209 if (StartAddress < EndAddress && (StartAddress & 2)) {
1210 //
1211 // Read a word if StartAddress is word aligned
1212 //
1213 *(UINT16*)Buffer = PciExpressRead16 (StartAddress);
1214 StartAddress += sizeof (UINT16);
1215 Buffer = (UINT16*)Buffer + 1;
1216 }
1217
1218 while (EndAddress - StartAddress >= 4) {
1219 //
1220 // Read as many double words as possible
1221 //
1222 *(UINT32*)Buffer = PciExpressRead32 (StartAddress);
1223 StartAddress += sizeof (UINT32);
1224 Buffer = (UINT32*)Buffer + 1;
1225 }
1226
1227 if ((EndAddress & 2) != 0) {
1228 //
1229 // Read the last remaining word if exist
1230 //
1231 *(UINT16*)Buffer = PciExpressRead16 (StartAddress);
1232 StartAddress += sizeof (UINT16);
1233 Buffer = (UINT16*)Buffer + 1;
1234 }
1235
1236 if (EndAddress & 1) {
1237 //
1238 // Read the last remaining byte if exist
1239 //
1240 *(UINT8*)Buffer = PciExpressRead8 (StartAddress);
1241 }
1242
1243 return Size;
1244 }
1245
1246 /**
1247 Copies the data in a caller supplied buffer to a specified range of PCI
1248 configuration space.
1249
1250 Writes the range of PCI configuration registers specified by StartAddress and
1251 Size from the buffer specified by Buffer. This function only allows the PCI
1252 configuration registers from a single PCI function to be written. Size is
1253 returned. When possible 32-bit PCI configuration write cycles are used to
1254 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1255 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1256 and the end of the range.
1257
1258 If StartAddress > 0x0FFFFFFF, then ASSERT().
1259 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1260 If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().
1261 If Buffer is NULL, then ASSERT().
1262
1263 @param StartAddress Starting address that encodes the PCI Bus, Device,
1264 Function and Register.
1265 @param Size Size in bytes of the transfer.
1266 @param Buffer Pointer to a buffer containing the data to write.
1267
1268 @return Size
1269
1270 **/
1271 UINTN
1272 EFIAPI
1273 PciExpressWriteBuffer (
1274 IN UINTN StartAddress,
1275 IN UINTN Size,
1276 IN VOID *Buffer
1277 )
1278 {
1279 UINTN EndAddress;
1280
1281 EndAddress = StartAddress + Size;
1282
1283 if ((StartAddress < EndAddress) && ((StartAddress & 1)!= 0)) {
1284 //
1285 // Write a byte if StartAddress is byte aligned
1286 //
1287 PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
1288 StartAddress += sizeof (UINT8);
1289 Buffer = (UINT8*)Buffer + 1;
1290 }
1291
1292 if (StartAddress < EndAddress && (StartAddress & 2)) {
1293 //
1294 // Write a word if StartAddress is word aligned
1295 //
1296 PciExpressWrite16 (StartAddress, *(UINT16*)Buffer);
1297 StartAddress += sizeof (UINT16);
1298 Buffer = (UINT16*)Buffer + 1;
1299 }
1300
1301 while (EndAddress - StartAddress >= 4) {
1302 //
1303 // Write as many double words as possible
1304 //
1305 PciExpressWrite32 (StartAddress, *(UINT32*)Buffer);
1306 StartAddress += sizeof (UINT32);
1307 Buffer = (UINT32*)Buffer + 1;
1308 }
1309
1310 if (EndAddress & 2) {
1311 //
1312 // Write the last remaining word if exist
1313 //
1314 PciExpressWrite16 (StartAddress, *(UINT16*)Buffer);
1315 StartAddress += sizeof (UINT16);
1316 Buffer = (UINT16*)Buffer + 1;
1317 }
1318
1319 if (EndAddress & 1) {
1320 //
1321 // Write the last remaining byte if exist
1322 //
1323 PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
1324 }
1325
1326 return Size;
1327 }