MdePkg/Library/BasePciLibPciExpress/PciLib.c

   1 /** @file
   2   PCI Library functions that use the 256 MB PCI Express MMIO window to perform PCI
   3   Configuration cycles. Layers on PCI Express Library.
   4
   5   Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #include <Base.h>
  11
  12 #include <Library/PciLib.h>
  13 #include <Library/PciExpressLib.h>
  14
  15 /**
  16   Registers a PCI device so PCI configuration registers may be accessed after
  17   SetVirtualAddressMap().
  18
  19   Registers the PCI device specified by Address so all the PCI configuration registers
  20   associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
  21
  22   If Address > 0x0FFFFFFF, then ASSERT().
  23
  24   @param  Address The address that encodes the PCI Bus, Device, Function and
  25                   Register.
  26
  27   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
  28   @retval RETURN_UNSUPPORTED       An attempt was made to call this function
  29                                    after ExitBootServices().
  30   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
  31                                    at runtime could not be mapped.
  32   @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to
  33                                    complete the registration.
  34
  35 **/
  36 RETURN_STATUS
  37 EFIAPI
  38 PciRegisterForRuntimeAccess (
  39   IN UINTN  Address
  40   )
  41 {
  42   return PciExpressRegisterForRuntimeAccess (Address);
  43 }
  44
  45 /**
  46   Reads an 8-bit PCI configuration register.
  47
  48   Reads and returns the 8-bit PCI configuration register specified by Address.
  49   This function must guarantee that all PCI read and write operations are
  50   serialized.
  51
  52   If Address > 0x0FFFFFFF, then ASSERT().
  53
  54   @param  Address The address that encodes the PCI Bus, Device, Function and
  55                   Register.
  56
  57   @return The read value from the PCI configuration register.
  58
  59 **/
  60 UINT8
  61 EFIAPI
  62 PciRead8 (
  63   IN      UINTN  Address
  64   )
  65 {
  66   return PciExpressRead8 (Address);
  67 }
  68
  69 /**
  70   Writes an 8-bit PCI configuration register.
  71
  72   Writes the 8-bit PCI configuration register specified by Address with the
  73   value specified by Value. Value is returned. This function must guarantee
  74   that all PCI read and write operations are serialized.
  75
  76   If Address > 0x0FFFFFFF, then ASSERT().
  77
  78   @param  Address The address that encodes the PCI Bus, Device, Function and
  79                   Register.
  80   @param  Value   The value to write.
  81
  82   @return The value written to the PCI configuration register.
  83
  84 **/
  85 UINT8
  86 EFIAPI
  87 PciWrite8 (
  88   IN      UINTN  Address,
  89   IN      UINT8  Value
  90   )
  91 {
  92   return PciExpressWrite8 (Address, Value);
  93 }
  94
  95 /**
  96   Performs a bitwise OR of an 8-bit PCI configuration register with
  97   an 8-bit value.
  98
  99   Reads the 8-bit PCI configuration register specified by Address, performs a
 100   bitwise OR between the read result and the value specified by
 101   OrData, and writes the result to the 8-bit PCI configuration register
 102   specified by Address. The value written to the PCI configuration register is
 103   returned. This function must guarantee that all PCI read and write operations
 104   are serialized.
 105
 106   If Address > 0x0FFFFFFF, then ASSERT().
 107
 108   @param  Address The address that encodes the PCI Bus, Device, Function and
 109                   Register.
 110   @param  OrData  The value to OR with the PCI configuration register.
 111
 112   @return The value written back to the PCI configuration register.
 113
 114 **/
 115 UINT8
 116 EFIAPI
 117 PciOr8 (
 118   IN      UINTN  Address,
 119   IN      UINT8  OrData
 120   )
 121 {
 122   return PciExpressOr8 (Address, OrData);
 123 }
 124
 125 /**
 126   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 127   value.
 128
 129   Reads the 8-bit PCI configuration register specified by Address, performs a
 130   bitwise AND between the read result and the value specified by AndData, and
 131   writes the result to the 8-bit PCI configuration register specified by
 132   Address. The value written to the PCI configuration register is returned.
 133   This function must guarantee that all PCI read and write operations are
 134   serialized.
 135
 136   If Address > 0x0FFFFFFF, then ASSERT().
 137
 138   @param  Address The address that encodes the PCI Bus, Device, Function and
 139                   Register.
 140   @param  AndData The value to AND with the PCI configuration register.
 141
 142   @return The value written back to the PCI configuration register.
 143
 144 **/
 145 UINT8
 146 EFIAPI
 147 PciAnd8 (
 148   IN      UINTN  Address,
 149   IN      UINT8  AndData
 150   )
 151 {
 152   return PciExpressAnd8 (Address, AndData);
 153 }
 154
 155 /**
 156   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 157   value, followed a  bitwise OR with another 8-bit value.
 158
 159   Reads the 8-bit PCI configuration register specified by Address, performs a
 160   bitwise AND between the read result and the value specified by AndData,
 161   performs a bitwise OR between the result of the AND operation and
 162   the value specified by OrData, and writes the result to the 8-bit PCI
 163   configuration register specified by Address. The value written to the PCI
 164   configuration register is returned. This function must guarantee that all PCI
 165   read and write operations are serialized.
 166
 167   If Address > 0x0FFFFFFF, then ASSERT().
 168
 169   @param  Address The address that encodes the PCI Bus, Device, Function and
 170                   Register.
 171   @param  AndData The value to AND with the PCI configuration register.
 172   @param  OrData  The value to OR with the result of the AND operation.
 173
 174   @return The value written back to the PCI configuration register.
 175
 176 **/
 177 UINT8
 178 EFIAPI
 179 PciAndThenOr8 (
 180   IN      UINTN  Address,
 181   IN      UINT8  AndData,
 182   IN      UINT8  OrData
 183   )
 184 {
 185   return PciExpressAndThenOr8 (Address, AndData, OrData);
 186 }
 187
 188 /**
 189   Reads a bit field of a PCI configuration register.
 190
 191   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 192   specified by the StartBit and the EndBit. The value of the bit field is
 193   returned.
 194
 195   If Address > 0x0FFFFFFF, then ASSERT().
 196   If StartBit is greater than 7, then ASSERT().
 197   If EndBit is greater than 7, then ASSERT().
 198   If EndBit is less than StartBit, then ASSERT().
 199
 200   @param  Address   The PCI configuration register to read.
 201   @param  StartBit  The ordinal of the least significant bit in the bit field.
 202                     Range 0..7.
 203   @param  EndBit    The ordinal of the most significant bit in the bit field.
 204                     Range 0..7.
 205
 206   @return The value of the bit field read from the PCI configuration register.
 207
 208 **/
 209 UINT8
 210 EFIAPI
 211 PciBitFieldRead8 (
 212   IN      UINTN  Address,
 213   IN      UINTN  StartBit,
 214   IN      UINTN  EndBit
 215   )
 216 {
 217   return PciExpressBitFieldRead8 (Address, StartBit, EndBit);
 218 }
 219
 220 /**
 221   Writes a bit field to a PCI configuration register.
 222
 223   Writes Value to the bit field of the PCI configuration register. The bit
 224   field is specified by the StartBit and the EndBit. All other bits in the
 225   destination PCI configuration register are preserved. The new value of the
 226   8-bit register is returned.
 227
 228   If Address > 0x0FFFFFFF, then ASSERT().
 229   If StartBit is greater than 7, then ASSERT().
 230   If EndBit is greater than 7, then ASSERT().
 231   If EndBit is less than StartBit, then ASSERT().
 232   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 233
 234   @param  Address   The PCI configuration register to write.
 235   @param  StartBit  The ordinal of the least significant bit in the bit field.
 236                     Range 0..7.
 237   @param  EndBit    The ordinal of the most significant bit in the bit field.
 238                     Range 0..7.
 239   @param  Value     The new value of the bit field.
 240
 241   @return The value written back to the PCI configuration register.
 242
 243 **/
 244 UINT8
 245 EFIAPI
 246 PciBitFieldWrite8 (
 247   IN      UINTN  Address,
 248   IN      UINTN  StartBit,
 249   IN      UINTN  EndBit,
 250   IN      UINT8  Value
 251   )
 252 {
 253   return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);
 254 }
 255
 256 /**
 257   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 258   writes the result back to the bit field in the 8-bit port.
 259
 260   Reads the 8-bit PCI configuration register specified by Address, performs a
 261   bitwise OR between the read result and the value specified by
 262   OrData, and writes the result to the 8-bit PCI configuration register
 263   specified by Address. The value written to the PCI configuration register is
 264   returned. This function must guarantee that all PCI read and write operations
 265   are serialized. Extra left bits in OrData are stripped.
 266
 267   If Address > 0x0FFFFFFF, then ASSERT().
 268   If StartBit is greater than 7, then ASSERT().
 269   If EndBit is greater than 7, then ASSERT().
 270   If EndBit is less than StartBit, then ASSERT().
 271   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 272
 273   @param  Address   The PCI configuration register to write.
 274   @param  StartBit  The ordinal of the least significant bit in the bit field.
 275                     Range 0..7.
 276   @param  EndBit    The ordinal of the most significant bit in the bit field.
 277                     Range 0..7.
 278   @param  OrData    The value to OR with the PCI configuration register.
 279
 280   @return The value written back to the PCI configuration register.
 281
 282 **/
 283 UINT8
 284 EFIAPI
 285 PciBitFieldOr8 (
 286   IN      UINTN  Address,
 287   IN      UINTN  StartBit,
 288   IN      UINTN  EndBit,
 289   IN      UINT8  OrData
 290   )
 291 {
 292   return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);
 293 }
 294
 295 /**
 296   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 297   AND, and writes the result back to the bit field in the 8-bit register.
 298
 299   Reads the 8-bit PCI configuration register specified by Address, performs a
 300   bitwise AND between the read result and the value specified by AndData, and
 301   writes the result to the 8-bit PCI configuration register specified by
 302   Address. The value written to the PCI configuration register is returned.
 303   This function must guarantee that all PCI read and write operations are
 304   serialized. Extra left bits in AndData are stripped.
 305
 306   If Address > 0x0FFFFFFF, then ASSERT().
 307   If StartBit is greater than 7, then ASSERT().
 308   If EndBit is greater than 7, then ASSERT().
 309   If EndBit is less than StartBit, then ASSERT().
 310   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 311
 312   @param  Address   The PCI configuration register to write.
 313   @param  StartBit  The ordinal of the least significant bit in the bit field.
 314                     Range 0..7.
 315   @param  EndBit    The ordinal of the most significant bit in the bit field.
 316                     Range 0..7.
 317   @param  AndData   The value to AND with the PCI configuration register.
 318
 319   @return The value written back to the PCI configuration register.
 320
 321 **/
 322 UINT8
 323 EFIAPI
 324 PciBitFieldAnd8 (
 325   IN      UINTN  Address,
 326   IN      UINTN  StartBit,
 327   IN      UINTN  EndBit,
 328   IN      UINT8  AndData
 329   )
 330 {
 331   return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);
 332 }
 333
 334 /**
 335   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 336   bitwise OR, and writes the result back to the bit field in the
 337   8-bit port.
 338
 339   Reads the 8-bit PCI configuration register specified by Address, performs a
 340   bitwise AND followed by a bitwise OR between the read result and
 341   the value specified by AndData, and writes the result to the 8-bit PCI
 342   configuration register specified by Address. The value written to the PCI
 343   configuration register is returned. This function must guarantee that all PCI
 344   read and write operations are serialized. Extra left bits in both AndData and
 345   OrData are stripped.
 346
 347   If Address > 0x0FFFFFFF, then ASSERT().
 348   If StartBit is greater than 7, then ASSERT().
 349   If EndBit is greater than 7, then ASSERT().
 350   If EndBit is less than StartBit, then ASSERT().
 351   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 352   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 353
 354   @param  Address   The PCI configuration register to write.
 355   @param  StartBit  The ordinal of the least significant bit in the bit field.
 356                     Range 0..7.
 357   @param  EndBit    The ordinal of the most significant bit in the bit field.
 358                     Range 0..7.
 359   @param  AndData   The value to AND with the PCI configuration register.
 360   @param  OrData    The value to OR with the result of the AND operation.
 361
 362   @return The value written back to the PCI configuration register.
 363
 364 **/
 365 UINT8
 366 EFIAPI
 367 PciBitFieldAndThenOr8 (
 368   IN      UINTN  Address,
 369   IN      UINTN  StartBit,
 370   IN      UINTN  EndBit,
 371   IN      UINT8  AndData,
 372   IN      UINT8  OrData
 373   )
 374 {
 375   return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);
 376 }
 377
 378 /**
 379   Reads a 16-bit PCI configuration register.
 380
 381   Reads and returns the 16-bit PCI configuration register specified by Address.
 382   This function must guarantee that all PCI read and write operations are
 383   serialized.
 384
 385   If Address > 0x0FFFFFFF, then ASSERT().
 386   If Address is not aligned on a 16-bit boundary, then ASSERT().
 387
 388   @param  Address The address that encodes the PCI Bus, Device, Function and
 389                   Register.
 390
 391   @return The read value from the PCI configuration register.
 392
 393 **/
 394 UINT16
 395 EFIAPI
 396 PciRead16 (
 397   IN      UINTN  Address
 398   )
 399 {
 400   return PciExpressRead16 (Address);
 401 }
 402
 403 /**
 404   Writes a 16-bit PCI configuration register.
 405
 406   Writes the 16-bit PCI configuration register specified by Address with the
 407   value specified by Value. Value is returned. This function must guarantee
 408   that all PCI read and write operations are serialized.
 409
 410   If Address > 0x0FFFFFFF, then ASSERT().
 411   If Address is not aligned on a 16-bit boundary, then ASSERT().
 412
 413   @param  Address The address that encodes the PCI Bus, Device, Function and
 414                   Register.
 415   @param  Value   The value to write.
 416
 417   @return The value written to the PCI configuration register.
 418
 419 **/
 420 UINT16
 421 EFIAPI
 422 PciWrite16 (
 423   IN      UINTN   Address,
 424   IN      UINT16  Value
 425   )
 426 {
 427   return PciExpressWrite16 (Address, Value);
 428 }
 429
 430 /**
 431   Performs a bitwise OR of a 16-bit PCI configuration register with
 432   a 16-bit value.
 433
 434   Reads the 16-bit PCI configuration register specified by Address, performs a
 435   bitwise OR between the read result and the value specified by
 436   OrData, and writes the result to the 16-bit PCI configuration register
 437   specified by Address. The value written to the PCI configuration register is
 438   returned. This function must guarantee that all PCI read and write operations
 439   are serialized.
 440
 441   If Address > 0x0FFFFFFF, then ASSERT().
 442   If Address is not aligned on a 16-bit boundary, then ASSERT().
 443
 444   @param  Address The address that encodes the PCI Bus, Device, Function and
 445                   Register.
 446   @param  OrData  The value to OR with the PCI configuration register.
 447
 448   @return The value written back to the PCI configuration register.
 449
 450 **/
 451 UINT16
 452 EFIAPI
 453 PciOr16 (
 454   IN      UINTN   Address,
 455   IN      UINT16  OrData
 456   )
 457 {
 458   return PciExpressOr16 (Address, OrData);
 459 }
 460
 461 /**
 462   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 463   value.
 464
 465   Reads the 16-bit PCI configuration register specified by Address, performs a
 466   bitwise AND between the read result and the value specified by AndData, and
 467   writes the result to the 16-bit PCI configuration register specified by
 468   Address. The value written to the PCI configuration register is returned.
 469   This function must guarantee that all PCI read and write operations are
 470   serialized.
 471
 472   If Address > 0x0FFFFFFF, then ASSERT().
 473   If Address is not aligned on a 16-bit boundary, then ASSERT().
 474
 475   @param  Address The address that encodes the PCI Bus, Device, Function and
 476                   Register.
 477   @param  AndData The value to AND with the PCI configuration register.
 478
 479   @return The value written back to the PCI configuration register.
 480
 481 **/
 482 UINT16
 483 EFIAPI
 484 PciAnd16 (
 485   IN      UINTN   Address,
 486   IN      UINT16  AndData
 487   )
 488 {
 489   return PciExpressAnd16 (Address, AndData);
 490 }
 491
 492 /**
 493   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 494   value, followed a  bitwise OR with another 16-bit value.
 495
 496   Reads the 16-bit PCI configuration register specified by Address, performs a
 497   bitwise AND between the read result and the value specified by AndData,
 498   performs a bitwise OR between the result of the AND operation and
 499   the value specified by OrData, and writes the result to the 16-bit PCI
 500   configuration register specified by Address. The value written to the PCI
 501   configuration register is returned. This function must guarantee that all PCI
 502   read and write operations are serialized.
 503
 504   If Address > 0x0FFFFFFF, then ASSERT().
 505   If Address is not aligned on a 16-bit boundary, then ASSERT().
 506
 507   @param  Address The address that encodes the PCI Bus, Device, Function and
 508                   Register.
 509   @param  AndData The value to AND with the PCI configuration register.
 510   @param  OrData  The value to OR with the result of the AND operation.
 511
 512   @return The value written back to the PCI configuration register.
 513
 514 **/
 515 UINT16
 516 EFIAPI
 517 PciAndThenOr16 (
 518   IN      UINTN   Address,
 519   IN      UINT16  AndData,
 520   IN      UINT16  OrData
 521   )
 522 {
 523   return PciExpressAndThenOr16 (Address, AndData, OrData);
 524 }
 525
 526 /**
 527   Reads a bit field of a PCI configuration register.
 528
 529   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 530   specified by the StartBit and the EndBit. The value of the bit field is
 531   returned.
 532
 533   If Address > 0x0FFFFFFF, then ASSERT().
 534   If Address is not aligned on a 16-bit boundary, then ASSERT().
 535   If StartBit is greater than 15, then ASSERT().
 536   If EndBit is greater than 15, then ASSERT().
 537   If EndBit is less than StartBit, then ASSERT().
 538
 539   @param  Address   The PCI configuration register to read.
 540   @param  StartBit  The ordinal of the least significant bit in the bit field.
 541                     Range 0..15.
 542   @param  EndBit    The ordinal of the most significant bit in the bit field.
 543                     Range 0..15.
 544
 545   @return The value of the bit field read from the PCI configuration register.
 546
 547 **/
 548 UINT16
 549 EFIAPI
 550 PciBitFieldRead16 (
 551   IN      UINTN  Address,
 552   IN      UINTN  StartBit,
 553   IN      UINTN  EndBit
 554   )
 555 {
 556   return PciExpressBitFieldRead16 (Address, StartBit, EndBit);
 557 }
 558
 559 /**
 560   Writes a bit field to a PCI configuration register.
 561
 562   Writes Value to the bit field of the PCI configuration register. The bit
 563   field is specified by the StartBit and the EndBit. All other bits in the
 564   destination PCI configuration register are preserved. The new value of the
 565   16-bit register is returned.
 566
 567   If Address > 0x0FFFFFFF, then ASSERT().
 568   If Address is not aligned on a 16-bit boundary, then ASSERT().
 569   If StartBit is greater than 15, then ASSERT().
 570   If EndBit is greater than 15, then ASSERT().
 571   If EndBit is less than StartBit, then ASSERT().
 572   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 573
 574   @param  Address   The PCI configuration register to write.
 575   @param  StartBit  The ordinal of the least significant bit in the bit field.
 576                     Range 0..15.
 577   @param  EndBit    The ordinal of the most significant bit in the bit field.
 578                     Range 0..15.
 579   @param  Value     The new value of the bit field.
 580
 581   @return The value written back to the PCI configuration register.
 582
 583 **/
 584 UINT16
 585 EFIAPI
 586 PciBitFieldWrite16 (
 587   IN      UINTN   Address,
 588   IN      UINTN   StartBit,
 589   IN      UINTN   EndBit,
 590   IN      UINT16  Value
 591   )
 592 {
 593   return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);
 594 }
 595
 596 /**
 597   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 598   writes the result back to the bit field in the 16-bit port.
 599
 600   Reads the 16-bit PCI configuration register specified by Address, performs a
 601   bitwise OR between the read result and the value specified by
 602   OrData, and writes the result to the 16-bit PCI configuration register
 603   specified by Address. The value written to the PCI configuration register is
 604   returned. This function must guarantee that all PCI read and write operations
 605   are serialized. Extra left bits in OrData are stripped.
 606
 607   If Address > 0x0FFFFFFF, then ASSERT().
 608   If Address is not aligned on a 16-bit boundary, then ASSERT().
 609   If StartBit is greater than 15, then ASSERT().
 610   If EndBit is greater than 15, then ASSERT().
 611   If EndBit is less than StartBit, then ASSERT().
 612   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 613
 614   @param  Address   The PCI configuration register to write.
 615   @param  StartBit  The ordinal of the least significant bit in the bit field.
 616                     Range 0..15.
 617   @param  EndBit    The ordinal of the most significant bit in the bit field.
 618                     Range 0..15.
 619   @param  OrData    The value to OR with the PCI configuration register.
 620
 621   @return The value written back to the PCI configuration register.
 622
 623 **/
 624 UINT16
 625 EFIAPI
 626 PciBitFieldOr16 (
 627   IN      UINTN   Address,
 628   IN      UINTN   StartBit,
 629   IN      UINTN   EndBit,
 630   IN      UINT16  OrData
 631   )
 632 {
 633   return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);
 634 }
 635
 636 /**
 637   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 638   AND, and writes the result back to the bit field in the 16-bit register.
 639
 640   Reads the 16-bit PCI configuration register specified by Address, performs a
 641   bitwise AND between the read result and the value specified by AndData, and
 642   writes the result to the 16-bit PCI configuration register specified by
 643   Address. The value written to the PCI configuration register is returned.
 644   This function must guarantee that all PCI read and write operations are
 645   serialized. Extra left bits in AndData are stripped.
 646
 647   If Address > 0x0FFFFFFF, then ASSERT().
 648   If Address is not aligned on a 16-bit boundary, then ASSERT().
 649   If StartBit is greater than 15, then ASSERT().
 650   If EndBit is greater than 15, then ASSERT().
 651   If EndBit is less than StartBit, then ASSERT().
 652   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 653
 654   @param  Address   The PCI configuration register to write.
 655   @param  StartBit  The ordinal of the least significant bit in the bit field.
 656                     Range 0..15.
 657   @param  EndBit    The ordinal of the most significant bit in the bit field.
 658                     Range 0..15.
 659   @param  AndData   The value to AND with the PCI configuration register.
 660
 661   @return The value written back to the PCI configuration register.
 662
 663 **/
 664 UINT16
 665 EFIAPI
 666 PciBitFieldAnd16 (
 667   IN      UINTN   Address,
 668   IN      UINTN   StartBit,
 669   IN      UINTN   EndBit,
 670   IN      UINT16  AndData
 671   )
 672 {
 673   return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);
 674 }
 675
 676 /**
 677   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 678   bitwise OR, and writes the result back to the bit field in the
 679   16-bit port.
 680
 681   Reads the 16-bit PCI configuration register specified by Address, performs a
 682   bitwise AND followed by a bitwise OR between the read result and
 683   the value specified by AndData, and writes the result to the 16-bit PCI
 684   configuration register specified by Address. The value written to the PCI
 685   configuration register is returned. This function must guarantee that all PCI
 686   read and write operations are serialized. Extra left bits in both AndData and
 687   OrData are stripped.
 688
 689   If Address > 0x0FFFFFFF, then ASSERT().
 690   If Address is not aligned on a 16-bit boundary, then ASSERT().
 691   If StartBit is greater than 15, then ASSERT().
 692   If EndBit is greater than 15, then ASSERT().
 693   If EndBit is less than StartBit, then ASSERT().
 694   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 695   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 696
 697   @param  Address   The PCI configuration register to write.
 698   @param  StartBit  The ordinal of the least significant bit in the bit field.
 699                     Range 0..15.
 700   @param  EndBit    The ordinal of the most significant bit in the bit field.
 701                     Range 0..15.
 702   @param  AndData   The value to AND with the PCI configuration register.
 703   @param  OrData    The value to OR with the result of the AND operation.
 704
 705   @return The value written back to the PCI configuration register.
 706
 707 **/
 708 UINT16
 709 EFIAPI
 710 PciBitFieldAndThenOr16 (
 711   IN      UINTN   Address,
 712   IN      UINTN   StartBit,
 713   IN      UINTN   EndBit,
 714   IN      UINT16  AndData,
 715   IN      UINT16  OrData
 716   )
 717 {
 718   return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);
 719 }
 720
 721 /**
 722   Reads a 32-bit PCI configuration register.
 723
 724   Reads and returns the 32-bit PCI configuration register specified by Address.
 725   This function must guarantee that all PCI read and write operations are
 726   serialized.
 727
 728   If Address > 0x0FFFFFFF, then ASSERT().
 729   If Address is not aligned on a 32-bit boundary, then ASSERT().
 730
 731   @param  Address The address that encodes the PCI Bus, Device, Function and
 732                   Register.
 733
 734   @return The read value from the PCI configuration register.
 735
 736 **/
 737 UINT32
 738 EFIAPI
 739 PciRead32 (
 740   IN      UINTN  Address
 741   )
 742 {
 743   return PciExpressRead32 (Address);
 744 }
 745
 746 /**
 747   Writes a 32-bit PCI configuration register.
 748
 749   Writes the 32-bit PCI configuration register specified by Address with the
 750   value specified by Value. Value is returned. This function must guarantee
 751   that all PCI read and write operations are serialized.
 752
 753   If Address > 0x0FFFFFFF, then ASSERT().
 754   If Address is not aligned on a 32-bit boundary, then ASSERT().
 755
 756   @param  Address The address that encodes the PCI Bus, Device, Function and
 757                   Register.
 758   @param  Value   The value to write.
 759
 760   @return The value written to the PCI configuration register.
 761
 762 **/
 763 UINT32
 764 EFIAPI
 765 PciWrite32 (
 766   IN      UINTN   Address,
 767   IN      UINT32  Value
 768   )
 769 {
 770   return PciExpressWrite32 (Address, Value);
 771 }
 772
 773 /**
 774   Performs a bitwise OR of a 32-bit PCI configuration register with
 775   a 32-bit value.
 776
 777   Reads the 32-bit PCI configuration register specified by Address, performs a
 778   bitwise OR between the read result and the value specified by
 779   OrData, and writes the result to the 32-bit PCI configuration register
 780   specified by Address. The value written to the PCI configuration register is
 781   returned. This function must guarantee that all PCI read and write operations
 782   are serialized.
 783
 784   If Address > 0x0FFFFFFF, then ASSERT().
 785   If Address is not aligned on a 32-bit boundary, then ASSERT().
 786
 787   @param  Address The address that encodes the PCI Bus, Device, Function and
 788                   Register.
 789   @param  OrData  The value to OR with the PCI configuration register.
 790
 791   @return The value written back to the PCI configuration register.
 792
 793 **/
 794 UINT32
 795 EFIAPI
 796 PciOr32 (
 797   IN      UINTN   Address,
 798   IN      UINT32  OrData
 799   )
 800 {
 801   return PciExpressOr32 (Address, OrData);
 802 }
 803
 804 /**
 805   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 806   value.
 807
 808   Reads the 32-bit PCI configuration register specified by Address, performs a
 809   bitwise AND between the read result and the value specified by AndData, and
 810   writes the result to the 32-bit PCI configuration register specified by
 811   Address. The value written to the PCI configuration register is returned.
 812   This function must guarantee that all PCI read and write operations are
 813   serialized.
 814
 815   If Address > 0x0FFFFFFF, then ASSERT().
 816   If Address is not aligned on a 32-bit boundary, then ASSERT().
 817
 818   @param  Address The address that encodes the PCI Bus, Device, Function and
 819                   Register.
 820   @param  AndData The value to AND with the PCI configuration register.
 821
 822   @return The value written back to the PCI configuration register.
 823
 824 **/
 825 UINT32
 826 EFIAPI
 827 PciAnd32 (
 828   IN      UINTN   Address,
 829   IN      UINT32  AndData
 830   )
 831 {
 832   return PciExpressAnd32 (Address, AndData);
 833 }
 834
 835 /**
 836   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 837   value, followed a  bitwise OR with another 32-bit value.
 838
 839   Reads the 32-bit PCI configuration register specified by Address, performs a
 840   bitwise AND between the read result and the value specified by AndData,
 841   performs a bitwise OR between the result of the AND operation and
 842   the value specified by OrData, and writes the result to the 32-bit PCI
 843   configuration register specified by Address. The value written to the PCI
 844   configuration register is returned. This function must guarantee that all PCI
 845   read and write operations are serialized.
 846
 847   If Address > 0x0FFFFFFF, then ASSERT().
 848   If Address is not aligned on a 32-bit boundary, then ASSERT().
 849
 850   @param  Address The address that encodes the PCI Bus, Device, Function and
 851                   Register.
 852   @param  AndData The value to AND with the PCI configuration register.
 853   @param  OrData  The value to OR with the result of the AND operation.
 854
 855   @return The value written back to the PCI configuration register.
 856
 857 **/
 858 UINT32
 859 EFIAPI
 860 PciAndThenOr32 (
 861   IN      UINTN   Address,
 862   IN      UINT32  AndData,
 863   IN      UINT32  OrData
 864   )
 865 {
 866   return PciExpressAndThenOr32 (Address, AndData, OrData);
 867 }
 868
 869 /**
 870   Reads a bit field of a PCI configuration register.
 871
 872   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 873   specified by the StartBit and the EndBit. The value of the bit field is
 874   returned.
 875
 876   If Address > 0x0FFFFFFF, then ASSERT().
 877   If Address is not aligned on a 32-bit boundary, then ASSERT().
 878   If StartBit is greater than 31, then ASSERT().
 879   If EndBit is greater than 31, then ASSERT().
 880   If EndBit is less than StartBit, then ASSERT().
 881
 882   @param  Address   The PCI configuration register to read.
 883   @param  StartBit  The ordinal of the least significant bit in the bit field.
 884                     Range 0..31.
 885   @param  EndBit    The ordinal of the most significant bit in the bit field.
 886                     Range 0..31.
 887
 888   @return The value of the bit field read from the PCI configuration register.
 889
 890 **/
 891 UINT32
 892 EFIAPI
 893 PciBitFieldRead32 (
 894   IN      UINTN  Address,
 895   IN      UINTN  StartBit,
 896   IN      UINTN  EndBit
 897   )
 898 {
 899   return PciExpressBitFieldRead32 (Address, StartBit, EndBit);
 900 }
 901
 902 /**
 903   Writes a bit field to a PCI configuration register.
 904
 905   Writes Value to the bit field of the PCI configuration register. The bit
 906   field is specified by the StartBit and the EndBit. All other bits in the
 907   destination PCI configuration register are preserved. The new value of the
 908   32-bit register is returned.
 909
 910   If Address > 0x0FFFFFFF, then ASSERT().
 911   If Address is not aligned on a 32-bit boundary, then ASSERT().
 912   If StartBit is greater than 31, then ASSERT().
 913   If EndBit is greater than 31, then ASSERT().
 914   If EndBit is less than StartBit, then ASSERT().
 915   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 916
 917   @param  Address   The PCI configuration register to write.
 918   @param  StartBit  The ordinal of the least significant bit in the bit field.
 919                     Range 0..31.
 920   @param  EndBit    The ordinal of the most significant bit in the bit field.
 921                     Range 0..31.
 922   @param  Value     The new value of the bit field.
 923
 924   @return The value written back to the PCI configuration register.
 925
 926 **/
 927 UINT32
 928 EFIAPI
 929 PciBitFieldWrite32 (
 930   IN      UINTN   Address,
 931   IN      UINTN   StartBit,
 932   IN      UINTN   EndBit,
 933   IN      UINT32  Value
 934   )
 935 {
 936   return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);
 937 }
 938
 939 /**
 940   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 941   writes the result back to the bit field in the 32-bit port.
 942
 943   Reads the 32-bit PCI configuration register specified by Address, performs a
 944   bitwise OR between the read result and the value specified by
 945   OrData, and writes the result to the 32-bit PCI configuration register
 946   specified by Address. The value written to the PCI configuration register is
 947   returned. This function must guarantee that all PCI read and write operations
 948   are serialized. Extra left bits in OrData are stripped.
 949
 950   If Address > 0x0FFFFFFF, then ASSERT().
 951   If Address is not aligned on a 32-bit boundary, then ASSERT().
 952   If StartBit is greater than 31, then ASSERT().
 953   If EndBit is greater than 31, then ASSERT().
 954   If EndBit is less than StartBit, then ASSERT().
 955   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 956
 957   @param  Address   The PCI configuration register to write.
 958   @param  StartBit  The ordinal of the least significant bit in the bit field.
 959                     Range 0..31.
 960   @param  EndBit    The ordinal of the most significant bit in the bit field.
 961                     Range 0..31.
 962   @param  OrData    The value to OR with the PCI configuration register.
 963
 964   @return The value written back to the PCI configuration register.
 965
 966 **/
 967 UINT32
 968 EFIAPI
 969 PciBitFieldOr32 (
 970   IN      UINTN   Address,
 971   IN      UINTN   StartBit,
 972   IN      UINTN   EndBit,
 973   IN      UINT32  OrData
 974   )
 975 {
 976   return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);
 977 }
 978
 979 /**
 980   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 981   AND, and writes the result back to the bit field in the 32-bit register.
 982
 983   Reads the 32-bit PCI configuration register specified by Address, performs a
 984   bitwise AND between the read result and the value specified by AndData, and
 985   writes the result to the 32-bit PCI configuration register specified by
 986   Address. The value written to the PCI configuration register is returned.
 987   This function must guarantee that all PCI read and write operations are
 988   serialized. Extra left bits in AndData are stripped.
 989
 990   If Address > 0x0FFFFFFF, then ASSERT().
 991   If Address is not aligned on a 32-bit boundary, then ASSERT().
 992   If StartBit is greater than 31, then ASSERT().
 993   If EndBit is greater than 31, then ASSERT().
 994   If EndBit is less than StartBit, then ASSERT().
 995   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 996
 997   @param  Address   The PCI configuration register to write.
 998   @param  StartBit  The ordinal of the least significant bit in the bit field.
 999                     Range 0..31.
1000   @param  EndBit    The ordinal of the most significant bit in the bit field.
1001                     Range 0..31.
1002   @param  AndData   The value to AND with the PCI configuration register.
1003
1004   @return The value written back to the PCI configuration register.
1005
1006 **/
1007 UINT32
1008 EFIAPI
1009 PciBitFieldAnd32 (
1010   IN      UINTN   Address,
1011   IN      UINTN   StartBit,
1012   IN      UINTN   EndBit,
1013   IN      UINT32  AndData
1014   )
1015 {
1016   return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);
1017 }
1018
1019 /**
1020   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1021   bitwise OR, and writes the result back to the bit field in the
1022   32-bit port.
1023
1024   Reads the 32-bit PCI configuration register specified by Address, performs a
1025   bitwise AND followed by a bitwise OR between the read result and
1026   the value specified by AndData, and writes the result to the 32-bit PCI
1027   configuration register specified by Address. The value written to the PCI
1028   configuration register is returned. This function must guarantee that all PCI
1029   read and write operations are serialized. Extra left bits in both AndData and
1030   OrData are stripped.
1031
1032   If Address > 0x0FFFFFFF, then ASSERT().
1033   If Address is not aligned on a 32-bit boundary, then ASSERT().
1034   If StartBit is greater than 31, then ASSERT().
1035   If EndBit is greater than 31, then ASSERT().
1036   If EndBit is less than StartBit, then ASSERT().
1037   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1038   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1039
1040   @param  Address   The PCI configuration register to write.
1041   @param  StartBit  The ordinal of the least significant bit in the bit field.
1042                     Range 0..31.
1043   @param  EndBit    The ordinal of the most significant bit in the bit field.
1044                     Range 0..31.
1045   @param  AndData   The value to AND with the PCI configuration register.
1046   @param  OrData    The value to OR with the result of the AND operation.
1047
1048   @return The value written back to the PCI configuration register.
1049
1050 **/
1051 UINT32
1052 EFIAPI
1053 PciBitFieldAndThenOr32 (
1054   IN      UINTN   Address,
1055   IN      UINTN   StartBit,
1056   IN      UINTN   EndBit,
1057   IN      UINT32  AndData,
1058   IN      UINT32  OrData
1059   )
1060 {
1061   return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);
1062 }
1063
1064 /**
1065   Reads a range of PCI configuration registers into a caller supplied buffer.
1066
1067   Reads the range of PCI configuration registers specified by StartAddress and
1068   Size into the buffer specified by Buffer. This function only allows the PCI
1069   configuration registers from a single PCI function to be read. Size is
1070   returned. When possible 32-bit PCI configuration read cycles are used to read
1071   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1072   and 16-bit PCI configuration read cycles may be used at the beginning and the
1073   end of the range.
1074
1075   If StartAddress > 0x0FFFFFFF, then ASSERT().
1076   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1077   If Size > 0 and Buffer is NULL, then ASSERT().
1078
1079   @param  StartAddress  The starting address that encodes the PCI Bus, Device,
1080                         Function and Register.
1081   @param  Size          The size in bytes of the transfer.
1082   @param  Buffer        The pointer to a buffer receiving the data read.
1083
1084   @return Size
1085
1086 **/
1087 UINTN
1088 EFIAPI
1089 PciReadBuffer (
1090   IN      UINTN  StartAddress,
1091   IN      UINTN  Size,
1092   OUT     VOID   *Buffer
1093   )
1094 {
1095   return PciExpressReadBuffer (StartAddress, Size, Buffer);
1096 }
1097
1098 /**
1099   Copies the data in a caller supplied buffer to a specified range of PCI
1100   configuration space.
1101
1102   Writes the range of PCI configuration registers specified by StartAddress and
1103   Size from the buffer specified by Buffer. This function only allows the PCI
1104   configuration registers from a single PCI function to be written. Size is
1105   returned. When possible 32-bit PCI configuration write cycles are used to
1106   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1107   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1108   and the end of the range.
1109
1110   If StartAddress > 0x0FFFFFFF, then ASSERT().
1111   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1112   If Size > 0 and Buffer is NULL, then ASSERT().
1113
1114   @param  StartAddress  The starting address that encodes the PCI Bus, Device,
1115                         Function and Register.
1116   @param  Size          The size in bytes of the transfer.
1117   @param  Buffer        The pointer to a buffer containing the data to write.
1118
1119   @return Size written to StartAddress.
1120
1121 **/
1122 UINTN
1123 EFIAPI
1124 PciWriteBuffer (
1125   IN      UINTN  StartAddress,
1126   IN      UINTN  Size,
1127   IN      VOID   *Buffer
1128   )
1129 {
1130   return PciExpressWriteBuffer (StartAddress, Size, Buffer);
1131 }