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1 /** @file
2 Fixes Intel Itanium(TM) specific relocation types.
3
4 Copyright (c) 2006, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 Module Name: PeCoffLoaderEx.c
14
15 **/
16
17
18
19
20
21 #define EXT_IMM64(Value, Address, Size, InstPos, ValPos) \
22 Value |= (((UINT64)((*(Address) >> InstPos) & (((UINT64)1 << Size) - 1))) << ValPos)
23
24 #define INS_IMM64(Value, Address, Size, InstPos, ValPos) \
25 *(UINT32*)Address = (*(UINT32*)Address & ~(((1 << Size) - 1) << InstPos)) | \
26 ((UINT32)((((UINT64)Value >> ValPos) & (((UINT64)1 << Size) - 1))) << InstPos)
27
28 #define IMM64_IMM7B_INST_WORD_X 3
29 #define IMM64_IMM7B_SIZE_X 7
30 #define IMM64_IMM7B_INST_WORD_POS_X 4
31 #define IMM64_IMM7B_VAL_POS_X 0
32
33 #define IMM64_IMM9D_INST_WORD_X 3
34 #define IMM64_IMM9D_SIZE_X 9
35 #define IMM64_IMM9D_INST_WORD_POS_X 18
36 #define IMM64_IMM9D_VAL_POS_X 7
37
38 #define IMM64_IMM5C_INST_WORD_X 3
39 #define IMM64_IMM5C_SIZE_X 5
40 #define IMM64_IMM5C_INST_WORD_POS_X 13
41 #define IMM64_IMM5C_VAL_POS_X 16
42
43 #define IMM64_IC_INST_WORD_X 3
44 #define IMM64_IC_SIZE_X 1
45 #define IMM64_IC_INST_WORD_POS_X 12
46 #define IMM64_IC_VAL_POS_X 21
47
48 #define IMM64_IMM41a_INST_WORD_X 1
49 #define IMM64_IMM41a_SIZE_X 10
50 #define IMM64_IMM41a_INST_WORD_POS_X 14
51 #define IMM64_IMM41a_VAL_POS_X 22
52
53 #define IMM64_IMM41b_INST_WORD_X 1
54 #define IMM64_IMM41b_SIZE_X 8
55 #define IMM64_IMM41b_INST_WORD_POS_X 24
56 #define IMM64_IMM41b_VAL_POS_X 32
57
58 #define IMM64_IMM41c_INST_WORD_X 2
59 #define IMM64_IMM41c_SIZE_X 23
60 #define IMM64_IMM41c_INST_WORD_POS_X 0
61 #define IMM64_IMM41c_VAL_POS_X 40
62
63 #define IMM64_SIGN_INST_WORD_X 3
64 #define IMM64_SIGN_SIZE_X 1
65 #define IMM64_SIGN_INST_WORD_POS_X 27
66 #define IMM64_SIGN_VAL_POS_X 63
67
68 /**
69 Performs an Itanium-based specific relocation fixup.
70
71 @param Reloc Pointer to the relocation record.
72
73 @param Fixup Pointer to the address to fix up.
74
75 @param FixupData Pointer to a buffer to log the fixups.
76
77 @param Adjust The offset to adjust the fixup.
78
79 @return Status code.
80
81 **/
82 RETURN_STATUS
83 PeCoffLoaderRelocateImageEx (
84 IN UINT16 *Reloc,
85 IN OUT CHAR8 *Fixup,
86 IN OUT CHAR8 **FixupData,
87 IN UINT64 Adjust
88 )
89 {
90 UINT64 *F64;
91 UINT64 FixupVal;
92
93 switch ((*Reloc) >> 12) {
94
95 case EFI_IMAGE_REL_BASED_DIR64:
96 F64 = (UINT64 *) Fixup;
97 *F64 = *F64 + (UINT64) Adjust;
98 if (*FixupData != NULL) {
99 *FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));
100 *(UINT64 *)(*FixupData) = *F64;
101 *FixupData = *FixupData + sizeof(UINT64);
102 }
103 break;
104
105 case EFI_IMAGE_REL_BASED_IA64_IMM64:
106
107 //
108 // Align it to bundle address before fixing up the
109 // 64-bit immediate value of the movl instruction.
110 //
111
112 Fixup = (CHAR8 *)((UINTN) Fixup & (UINTN) ~(15));
113 FixupVal = (UINT64)0;
114
115 //
116 // Extract the lower 32 bits of IMM64 from bundle
117 //
118 EXT_IMM64(FixupVal,
119 (UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X,
120 IMM64_IMM7B_SIZE_X,
121 IMM64_IMM7B_INST_WORD_POS_X,
122 IMM64_IMM7B_VAL_POS_X
123 );
124
125 EXT_IMM64(FixupVal,
126 (UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X,
127 IMM64_IMM9D_SIZE_X,
128 IMM64_IMM9D_INST_WORD_POS_X,
129 IMM64_IMM9D_VAL_POS_X
130 );
131
132 EXT_IMM64(FixupVal,
133 (UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X,
134 IMM64_IMM5C_SIZE_X,
135 IMM64_IMM5C_INST_WORD_POS_X,
136 IMM64_IMM5C_VAL_POS_X
137 );
138
139 EXT_IMM64(FixupVal,
140 (UINT32 *)Fixup + IMM64_IC_INST_WORD_X,
141 IMM64_IC_SIZE_X,
142 IMM64_IC_INST_WORD_POS_X,
143 IMM64_IC_VAL_POS_X
144 );
145
146 EXT_IMM64(FixupVal,
147 (UINT32 *)Fixup + IMM64_IMM41a_INST_WORD_X,
148 IMM64_IMM41a_SIZE_X,
149 IMM64_IMM41a_INST_WORD_POS_X,
150 IMM64_IMM41a_VAL_POS_X
151 );
152
153 //
154 // Update 64-bit address
155 //
156 FixupVal += Adjust;
157
158 //
159 // Insert IMM64 into bundle
160 //
161 INS_IMM64(FixupVal,
162 ((UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X),
163 IMM64_IMM7B_SIZE_X,
164 IMM64_IMM7B_INST_WORD_POS_X,
165 IMM64_IMM7B_VAL_POS_X
166 );
167
168 INS_IMM64(FixupVal,
169 ((UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X),
170 IMM64_IMM9D_SIZE_X,
171 IMM64_IMM9D_INST_WORD_POS_X,
172 IMM64_IMM9D_VAL_POS_X
173 );
174
175 INS_IMM64(FixupVal,
176 ((UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X),
177 IMM64_IMM5C_SIZE_X,
178 IMM64_IMM5C_INST_WORD_POS_X,
179 IMM64_IMM5C_VAL_POS_X
180 );
181
182 INS_IMM64(FixupVal,
183 ((UINT32 *)Fixup + IMM64_IC_INST_WORD_X),
184 IMM64_IC_SIZE_X,
185 IMM64_IC_INST_WORD_POS_X,
186 IMM64_IC_VAL_POS_X
187 );
188
189 INS_IMM64(FixupVal,
190 ((UINT32 *)Fixup + IMM64_IMM41a_INST_WORD_X),
191 IMM64_IMM41a_SIZE_X,
192 IMM64_IMM41a_INST_WORD_POS_X,
193 IMM64_IMM41a_VAL_POS_X
194 );
195
196 INS_IMM64(FixupVal,
197 ((UINT32 *)Fixup + IMM64_IMM41b_INST_WORD_X),
198 IMM64_IMM41b_SIZE_X,
199 IMM64_IMM41b_INST_WORD_POS_X,
200 IMM64_IMM41b_VAL_POS_X
201 );
202
203 INS_IMM64(FixupVal,
204 ((UINT32 *)Fixup + IMM64_IMM41c_INST_WORD_X),
205 IMM64_IMM41c_SIZE_X,
206 IMM64_IMM41c_INST_WORD_POS_X,
207 IMM64_IMM41c_VAL_POS_X
208 );
209
210 INS_IMM64(FixupVal,
211 ((UINT32 *)Fixup + IMM64_SIGN_INST_WORD_X),
212 IMM64_SIGN_SIZE_X,
213 IMM64_SIGN_INST_WORD_POS_X,
214 IMM64_SIGN_VAL_POS_X
215 );
216
217 F64 = (UINT64 *) Fixup;
218 if (*FixupData != NULL) {
219 *FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));
220 *(UINT64 *)(*FixupData) = *F64;
221 *FixupData = *FixupData + sizeof(UINT64);
222 }
223 break;
224
225 default:
226 return RETURN_UNSUPPORTED;
227 }
228
229 return RETURN_SUCCESS;
230 }