MdePkg/Library/BaseS3PciSegmentLib/S3PciSegmentLib.c

   1 /** @file
   2   The multiple segments PCI configuration Library Services that carry out
   3   PCI configuration and enable the PCI operations to be replayed during an
   4   S3 resume. This library class maps directly on top of the PciSegmentLib class.
   5
   6   Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 #include <Base.h>
  12
  13 #include <Library/DebugLib.h>
  14 #include <Library/S3BootScriptLib.h>
  15 #include <Library/PciSegmentLib.h>
  16
  17 /**
  18   Macro that converts address in PciSegmentLib format to the new address that can be pass
  19   to the S3 Boot Script Library functions. The Segment is dropped.
  20
  21   @param Address  Address in PciSegmentLib format.
  22
  23   @retval New address that can be pass to the S3 Boot Script Library functions.
  24 **/
  25 #define PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS(Address) \
  26           ((((UINT32)(Address) >> 20) & 0xff) << 24) | \
  27           ((((UINT32)(Address) >> 15) & 0x1f) << 16) | \
  28           ((((UINT32)(Address) >> 12) & 0x07) <<  8) | \
  29           LShiftU64 ((Address) & 0xfff, 32)    // Always put Register in high four bytes.
  30
  31 /**
  32   Saves a PCI configuration value to the boot script.
  33
  34   This internal worker function saves a PCI configuration value in
  35   the S3 script to be replayed on S3 resume.
  36
  37   If the saving process fails, then ASSERT().
  38
  39   @param  Width   The width of PCI configuration.
  40   @param  Address Address that encodes the PCI Bus, Device, Function and
  41                   Register.
  42   @param  Buffer  The buffer containing value.
  43
  44 **/
  45 VOID
  46 InternalSavePciSegmentWriteValueToBootScript (
  47   IN S3_BOOT_SCRIPT_LIB_WIDTH  Width,
  48   IN UINT64                    Address,
  49   IN VOID                      *Buffer
  50   )
  51 {
  52   RETURN_STATUS  Status;
  53
  54   Status = S3BootScriptSavePciCfg2Write (
  55              Width,
  56              RShiftU64 ((Address), 32) & 0xffff,
  57              PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS (Address),
  58              1,
  59              Buffer
  60              );
  61   ASSERT_RETURN_ERROR (Status);
  62 }
  63
  64 /**
  65   Saves an 8-bit PCI configuration value to the boot script.
  66
  67   This internal worker function saves an 8-bit PCI configuration value in
  68   the S3 script to be replayed on S3 resume.
  69
  70   If the saving process fails, then ASSERT().
  71
  72   @param  Address Address that encodes the PCI Bus, Device, Function and
  73                   Register.
  74   @param  Value   The value saved to boot script.
  75
  76   @return Value.
  77
  78 **/
  79 UINT8
  80 InternalSavePciSegmentWrite8ValueToBootScript (
  81   IN UINT64  Address,
  82   IN UINT8   Value
  83   )
  84 {
  85   InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint8, Address, &Value);
  86
  87   return Value;
  88 }
  89
  90 /**
  91   Reads an 8-bit PCI configuration register, and saves the value in the S3 script to
  92   be replayed on S3 resume.
  93
  94   Reads and returns the 8-bit PCI configuration register specified by Address.
  95   This function must guarantee that all PCI read and write operations are serialized.
  96
  97   If any reserved bits in Address are set, then ASSERT().
  98
  99   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 100
 101   @return The 8-bit PCI configuration register specified by Address.
 102
 103 **/
 104 UINT8
 105 EFIAPI
 106 S3PciSegmentRead8 (
 107   IN UINT64  Address
 108   )
 109 {
 110   return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentRead8 (Address));
 111 }
 112
 113 /**
 114   Writes an 8-bit PCI configuration register, and saves the value in the S3 script to
 115   be replayed on S3 resume.
 116
 117   Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
 118   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 119
 120   If any reserved bits in Address are set, then ASSERT().
 121
 122   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 123   @param  Value       The value to write.
 124
 125   @return The value written to the PCI configuration register.
 126
 127 **/
 128 UINT8
 129 EFIAPI
 130 S3PciSegmentWrite8 (
 131   IN UINT64  Address,
 132   IN UINT8   Value
 133   )
 134 {
 135   return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentWrite8 (Address, Value));
 136 }
 137
 138 /**
 139   Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value, and saves
 140   the value in the S3 script to be replayed on S3 resume.
 141
 142   Reads the 8-bit PCI configuration register specified by Address,
 143   performs a bitwise OR between the read result and the value specified by OrData,
 144   and writes the result to the 8-bit PCI configuration register specified by Address.
 145   The value written to the PCI configuration register is returned.
 146   This function must guarantee that all PCI read and write operations are serialized.
 147
 148   If any reserved bits in Address are set, then ASSERT().
 149
 150   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 151   @param  OrData    The value to OR with the PCI configuration register.
 152
 153   @return The value written to the PCI configuration register.
 154
 155 **/
 156 UINT8
 157 EFIAPI
 158 S3PciSegmentOr8 (
 159   IN UINT64  Address,
 160   IN UINT8   OrData
 161   )
 162 {
 163   return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentOr8 (Address, OrData));
 164 }
 165
 166 /**
 167   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, and
 168   saves the value in the S3 script to be replayed on S3 resume.
 169
 170   Reads the 8-bit PCI configuration register specified by Address,
 171   performs a bitwise AND between the read result and the value specified by AndData,
 172   and writes the result to the 8-bit PCI configuration register specified by Address.
 173   The value written to the PCI configuration register is returned.
 174   This function must guarantee that all PCI read and write operations are serialized.
 175   If any reserved bits in Address are set, then ASSERT().
 176
 177   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 178   @param  AndData   The value to AND with the PCI configuration register.
 179
 180   @return The value written to the PCI configuration register.
 181
 182 **/
 183 UINT8
 184 EFIAPI
 185 S3PciSegmentAnd8 (
 186   IN UINT64  Address,
 187   IN UINT8   AndData
 188   )
 189 {
 190   return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentAnd8 (Address, AndData));
 191 }
 192
 193 /**
 194   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
 195   followed a bitwise OR with another 8-bit value, and saves the value in the S3 script to
 196   be replayed on S3 resume.
 197
 198   Reads the 8-bit PCI configuration register specified by Address,
 199   performs a bitwise AND between the read result and the value specified by AndData,
 200   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
 201   and writes the result to the 8-bit PCI configuration register specified by Address.
 202   The value written to the PCI configuration register is returned.
 203   This function must guarantee that all PCI read and write operations are serialized.
 204
 205   If any reserved bits in Address are set, then ASSERT().
 206
 207   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 208   @param  AndData    The value to AND with the PCI configuration register.
 209   @param  OrData    The value to OR with the PCI configuration register.
 210
 211   @return The value written to the PCI configuration register.
 212
 213 **/
 214 UINT8
 215 EFIAPI
 216 S3PciSegmentAndThenOr8 (
 217   IN UINT64  Address,
 218   IN UINT8   AndData,
 219   IN UINT8   OrData
 220   )
 221 {
 222   return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentAndThenOr8 (Address, AndData, OrData));
 223 }
 224
 225 /**
 226   Reads a bit field of a PCI configuration register, and saves the value in the
 227   S3 script to be replayed on S3 resume.
 228
 229   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 230   specified by the StartBit and the EndBit. The value of the bit field is
 231   returned.
 232
 233   If any reserved bits in Address are set, then ASSERT().
 234   If StartBit is greater than 7, then ASSERT().
 235   If EndBit is greater than 7, then ASSERT().
 236   If EndBit is less than StartBit, then ASSERT().
 237
 238   @param  Address   PCI configuration register to read.
 239   @param  StartBit  The ordinal of the least significant bit in the bit field.
 240                     Range 0..7.
 241   @param  EndBit    The ordinal of the most significant bit in the bit field.
 242                     Range 0..7.
 243
 244   @return The value of the bit field read from the PCI configuration register.
 245
 246 **/
 247 UINT8
 248 EFIAPI
 249 S3PciSegmentBitFieldRead8 (
 250   IN UINT64  Address,
 251   IN UINTN   StartBit,
 252   IN UINTN   EndBit
 253   )
 254 {
 255   return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldRead8 (Address, StartBit, EndBit));
 256 }
 257
 258 /**
 259   Writes a bit field to a PCI configuration register, and saves the value in
 260   the S3 script to be replayed on S3 resume.
 261
 262   Writes Value to the bit field of the PCI configuration register. The bit
 263   field is specified by the StartBit and the EndBit. All other bits in the
 264   destination PCI configuration register are preserved. The new value of the
 265   8-bit register is returned.
 266
 267   If any reserved bits in Address are set, then ASSERT().
 268   If StartBit is greater than 7, then ASSERT().
 269   If EndBit is greater than 7, then ASSERT().
 270   If EndBit is less than StartBit, then ASSERT().
 271   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 272
 273   @param  Address   PCI configuration register to write.
 274   @param  StartBit  The ordinal of the least significant bit in the bit field.
 275                     Range 0..7.
 276   @param  EndBit    The ordinal of the most significant bit in the bit field.
 277                     Range 0..7.
 278   @param  Value     New value of the bit field.
 279
 280   @return The value written back to the PCI configuration register.
 281
 282 **/
 283 UINT8
 284 EFIAPI
 285 S3PciSegmentBitFieldWrite8 (
 286   IN UINT64  Address,
 287   IN UINTN   StartBit,
 288   IN UINTN   EndBit,
 289   IN UINT8   Value
 290   )
 291 {
 292   return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldWrite8 (Address, StartBit, EndBit, Value));
 293 }
 294
 295 /**
 296   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, writes
 297   the result back to the bit field in the 8-bit port, and saves the value in the
 298   S3 script to be replayed on S3 resume.
 299
 300   Reads the 8-bit PCI configuration register specified by Address, performs a
 301   bitwise OR between the read result and the value specified by
 302   OrData, and writes the result to the 8-bit PCI configuration register
 303   specified by Address. The value written to the PCI configuration register is
 304   returned. This function must guarantee that all PCI read and write operations
 305   are serialized. Extra left bits in OrData are stripped.
 306
 307   If any reserved bits in Address are set, then ASSERT().
 308   If StartBit is greater than 7, then ASSERT().
 309   If EndBit is greater than 7, then ASSERT().
 310   If EndBit is less than StartBit, then ASSERT().
 311   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 312
 313   @param  Address   PCI configuration register to write.
 314   @param  StartBit  The ordinal of the least significant bit in the bit field.
 315                     Range 0..7.
 316   @param  EndBit    The ordinal of the most significant bit in the bit field.
 317                     Range 0..7.
 318   @param  OrData    The value to OR with the PCI configuration register.
 319
 320   @return The value written back to the PCI configuration register.
 321
 322 **/
 323 UINT8
 324 EFIAPI
 325 S3PciSegmentBitFieldOr8 (
 326   IN UINT64  Address,
 327   IN UINTN   StartBit,
 328   IN UINTN   EndBit,
 329   IN UINT8   OrData
 330   )
 331 {
 332   return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldOr8 (Address, StartBit, EndBit, OrData));
 333 }
 334
 335 /**
 336   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 337   AND, writes the result back to the bit field in the 8-bit register, and
 338   saves the value in the S3 script to be replayed on S3 resume.
 339
 340   Reads the 8-bit PCI configuration register specified by Address, performs a
 341   bitwise AND between the read result and the value specified by AndData, and
 342   writes the result to the 8-bit PCI configuration register specified by
 343   Address. The value written to the PCI configuration register is returned.
 344   This function must guarantee that all PCI read and write operations are
 345   serialized. Extra left bits in AndData are stripped.
 346
 347   If any reserved bits in Address are set, then ASSERT().
 348   If StartBit is greater than 7, then ASSERT().
 349   If EndBit is greater than 7, then ASSERT().
 350   If EndBit is less than StartBit, then ASSERT().
 351   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 352
 353   @param  Address   PCI configuration register to write.
 354   @param  StartBit  The ordinal of the least significant bit in the bit field.
 355                     Range 0..7.
 356   @param  EndBit    The ordinal of the most significant bit in the bit field.
 357                     Range 0..7.
 358   @param  AndData   The value to AND with the PCI configuration register.
 359
 360   @return The value written back to the PCI configuration register.
 361
 362 **/
 363 UINT8
 364 EFIAPI
 365 S3PciSegmentBitFieldAnd8 (
 366   IN UINT64  Address,
 367   IN UINTN   StartBit,
 368   IN UINTN   EndBit,
 369   IN UINT8   AndData
 370   )
 371 {
 372   return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldAnd8 (Address, StartBit, EndBit, AndData));
 373 }
 374
 375 /**
 376   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 377   bitwise OR, writes the result back to the bit field in the 8-bit port,
 378   and saves the value in the S3 script to be replayed on S3 resume.
 379
 380   Reads the 8-bit PCI configuration register specified by Address, performs a
 381   bitwise AND followed by a bitwise OR between the read result and
 382   the value specified by AndData, and writes the result to the 8-bit PCI
 383   configuration register specified by Address. The value written to the PCI
 384   configuration register is returned. This function must guarantee that all PCI
 385   read and write operations are serialized. Extra left bits in both AndData and
 386   OrData are stripped.
 387
 388   If any reserved bits in Address are set, then ASSERT().
 389   If StartBit is greater than 7, then ASSERT().
 390   If EndBit is greater than 7, then ASSERT().
 391   If EndBit is less than StartBit, then ASSERT().
 392   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 393   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 394
 395   @param  Address   PCI configuration register to write.
 396   @param  StartBit  The ordinal of the least significant bit in the bit field.
 397                     Range 0..7.
 398   @param  EndBit    The ordinal of the most significant bit in the bit field.
 399                     Range 0..7.
 400   @param  AndData   The value to AND with the PCI configuration register.
 401   @param  OrData    The value to OR with the result of the AND operation.
 402
 403   @return The value written back to the PCI configuration register.
 404
 405 **/
 406 UINT8
 407 EFIAPI
 408 S3PciSegmentBitFieldAndThenOr8 (
 409   IN UINT64  Address,
 410   IN UINTN   StartBit,
 411   IN UINTN   EndBit,
 412   IN UINT8   AndData,
 413   IN UINT8   OrData
 414   )
 415 {
 416   return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData));
 417 }
 418
 419 /**
 420   Saves a 16-bit PCI configuration value to the boot script.
 421
 422   This internal worker function saves a 16-bit PCI configuration value in
 423   the S3 script to be replayed on S3 resume.
 424
 425   If the saving process fails, then ASSERT().
 426
 427   @param  Address Address that encodes the PCI Bus, Device, Function and
 428                   Register.
 429   @param  Value   The value saved to boot script.
 430
 431   @return Value.
 432
 433 **/
 434 UINT16
 435 InternalSavePciSegmentWrite16ValueToBootScript (
 436   IN UINT64  Address,
 437   IN UINT16  Value
 438   )
 439 {
 440   InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint16, Address, &Value);
 441
 442   return Value;
 443 }
 444
 445 /**
 446   Reads a 16-bit PCI configuration register, and saves the value in the S3 script
 447   to be replayed on S3 resume.
 448
 449   Reads and returns the 16-bit PCI configuration register specified by Address.
 450   This function must guarantee that all PCI read and write operations are serialized.
 451
 452   If any reserved bits in Address are set, then ASSERT().
 453   If Address is not aligned on a 16-bit boundary, then ASSERT().
 454
 455   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 456
 457   @return The 16-bit PCI configuration register specified by Address.
 458
 459 **/
 460 UINT16
 461 EFIAPI
 462 S3PciSegmentRead16 (
 463   IN UINT64  Address
 464   )
 465 {
 466   return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentRead16 (Address));
 467 }
 468
 469 /**
 470   Writes a 16-bit PCI configuration register, and saves the value in the S3 script to
 471   be replayed on S3 resume.
 472
 473   Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
 474   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 475
 476   If any reserved bits in Address are set, then ASSERT().
 477   If Address is not aligned on a 16-bit boundary, then ASSERT().
 478
 479   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 480   @param  Value       The value to write.
 481
 482   @return The parameter of Value.
 483
 484 **/
 485 UINT16
 486 EFIAPI
 487 S3PciSegmentWrite16 (
 488   IN UINT64  Address,
 489   IN UINT16  Value
 490   )
 491 {
 492   return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentWrite16 (Address, Value));
 493 }
 494
 495 /**
 496   Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit
 497   value, and saves the value in the S3 script to be replayed on S3 resume.
 498
 499   Reads the 16-bit PCI configuration register specified by Address, performs a
 500   bitwise OR between the read result and the value specified by OrData, and
 501   writes the result to the 16-bit PCI configuration register specified by Address.
 502   The value written to the PCI configuration register is returned. This function
 503   must guarantee that all PCI read and write operations are serialized.
 504
 505   If any reserved bits in Address are set, then ASSERT().
 506   If Address is not aligned on a 16-bit boundary, then ASSERT().
 507
 508   @param  Address Address that encodes the PCI Segment, Bus, Device, Function and
 509                   Register.
 510   @param  OrData  The value to OR with the PCI configuration register.
 511
 512   @return The value written back to the PCI configuration register.
 513
 514 **/
 515 UINT16
 516 EFIAPI
 517 S3PciSegmentOr16 (
 518   IN UINT64  Address,
 519   IN UINT16  OrData
 520   )
 521 {
 522   return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentOr16 (Address, OrData));
 523 }
 524
 525 /**
 526   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, and
 527   saves the value in the S3 script to be replayed on S3 resume.
 528
 529   Reads the 16-bit PCI configuration register specified by Address,
 530   performs a bitwise AND between the read result and the value specified by AndData,
 531   and writes the result to the 16-bit PCI configuration register specified by Address.
 532   The value written to the PCI configuration register is returned.
 533   This function must guarantee that all PCI read and write operations are serialized.
 534
 535   If any reserved bits in Address are set, then ASSERT().
 536   If Address is not aligned on a 16-bit boundary, then ASSERT().
 537
 538   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 539   @param  AndData   The value to AND with the PCI configuration register.
 540
 541   @return The value written to the PCI configuration register.
 542
 543 **/
 544 UINT16
 545 EFIAPI
 546 S3PciSegmentAnd16 (
 547   IN UINT64  Address,
 548   IN UINT16  AndData
 549   )
 550 {
 551   return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentAnd16 (Address, AndData));
 552 }
 553
 554 /**
 555   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
 556   followed a bitwise OR with another 16-bit value, and saves the value in the S3 script to
 557   be replayed on S3 resume.
 558
 559   Reads the 16-bit PCI configuration register specified by Address,
 560   performs a bitwise AND between the read result and the value specified by AndData,
 561   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
 562   and writes the result to the 16-bit PCI configuration register specified by Address.
 563   The value written to the PCI configuration register is returned.
 564   This function must guarantee that all PCI read and write operations are serialized.
 565
 566   If any reserved bits in Address are set, then ASSERT().
 567   If Address is not aligned on a 16-bit boundary, then ASSERT().
 568
 569   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 570   @param  AndData   The value to AND with the PCI configuration register.
 571   @param  OrData    The value to OR with the PCI configuration register.
 572
 573   @return The value written to the PCI configuration register.
 574
 575 **/
 576 UINT16
 577 EFIAPI
 578 S3PciSegmentAndThenOr16 (
 579   IN UINT64  Address,
 580   IN UINT16  AndData,
 581   IN UINT16  OrData
 582   )
 583 {
 584   return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentAndThenOr16 (Address, AndData, OrData));
 585 }
 586
 587 /**
 588   Reads a bit field of a PCI configuration register, and saves the value in the
 589   S3 script to be replayed on S3 resume.
 590
 591   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 592   specified by the StartBit and the EndBit. The value of the bit field is
 593   returned.
 594
 595   If any reserved bits in Address are set, then ASSERT().
 596   If Address is not aligned on a 16-bit boundary, then ASSERT().
 597   If StartBit is greater than 15, then ASSERT().
 598   If EndBit is greater than 15, then ASSERT().
 599   If EndBit is less than StartBit, then ASSERT().
 600
 601   @param  Address   PCI configuration register to read.
 602   @param  StartBit  The ordinal of the least significant bit in the bit field.
 603                     Range 0..15.
 604   @param  EndBit    The ordinal of the most significant bit in the bit field.
 605                     Range 0..15.
 606
 607   @return The value of the bit field read from the PCI configuration register.
 608
 609 **/
 610 UINT16
 611 EFIAPI
 612 S3PciSegmentBitFieldRead16 (
 613   IN UINT64  Address,
 614   IN UINTN   StartBit,
 615   IN UINTN   EndBit
 616   )
 617 {
 618   return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldRead16 (Address, StartBit, EndBit));
 619 }
 620
 621 /**
 622   Writes a bit field to a PCI configuration register, and saves the value in
 623   the S3 script to be replayed on S3 resume.
 624
 625   Writes Value to the bit field of the PCI configuration register. The bit
 626   field is specified by the StartBit and the EndBit. All other bits in the
 627   destination PCI configuration register are preserved. The new value of the
 628   16-bit register is returned.
 629
 630   If any reserved bits in Address are set, then ASSERT().
 631   If Address is not aligned on a 16-bit boundary, then ASSERT().
 632   If StartBit is greater than 15, then ASSERT().
 633   If EndBit is greater than 15, then ASSERT().
 634   If EndBit is less than StartBit, then ASSERT().
 635   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 636
 637   @param  Address   PCI configuration register to write.
 638   @param  StartBit  The ordinal of the least significant bit in the bit field.
 639                     Range 0..15.
 640   @param  EndBit    The ordinal of the most significant bit in the bit field.
 641                     Range 0..15.
 642   @param  Value     New value of the bit field.
 643
 644   @return The value written back to the PCI configuration register.
 645
 646 **/
 647 UINT16
 648 EFIAPI
 649 S3PciSegmentBitFieldWrite16 (
 650   IN UINT64  Address,
 651   IN UINTN   StartBit,
 652   IN UINTN   EndBit,
 653   IN UINT16  Value
 654   )
 655 {
 656   return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldWrite16 (Address, StartBit, EndBit, Value));
 657 }
 658
 659 /**
 660   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
 661   the result back to the bit field in the 16-bit port, and saves the value in the
 662   S3 script to be replayed on S3 resume.
 663
 664   Reads the 16-bit PCI configuration register specified by Address, performs a
 665   bitwise OR between the read result and the value specified by
 666   OrData, and writes the result to the 16-bit PCI configuration register
 667   specified by Address. The value written to the PCI configuration register is
 668   returned. This function must guarantee that all PCI read and write operations
 669   are serialized. Extra left bits in OrData are stripped.
 670
 671   If any reserved bits in Address are set, then ASSERT().
 672   If Address is not aligned on a 16-bit boundary, then ASSERT().
 673   If StartBit is greater than 15, then ASSERT().
 674   If EndBit is greater than 15, then ASSERT().
 675   If EndBit is less than StartBit, then ASSERT().
 676   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 677
 678   @param  Address   PCI configuration register to write.
 679   @param  StartBit  The ordinal of the least significant bit in the bit field.
 680                     Range 0..15.
 681   @param  EndBit    The ordinal of the most significant bit in the bit field.
 682                     Range 0..15.
 683   @param  OrData    The value to OR with the PCI configuration register.
 684
 685   @return The value written back to the PCI configuration register.
 686
 687 **/
 688 UINT16
 689 EFIAPI
 690 S3PciSegmentBitFieldOr16 (
 691   IN UINT64  Address,
 692   IN UINTN   StartBit,
 693   IN UINTN   EndBit,
 694   IN UINT16  OrData
 695   )
 696 {
 697   return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldOr16 (Address, StartBit, EndBit, OrData));
 698 }
 699
 700 /**
 701   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 702   AND, writes the result back to the bit field in the 16-bit register, and
 703   saves the value in the S3 script to be replayed on S3 resume.
 704
 705   Reads the 16-bit PCI configuration register specified by Address, performs a
 706   bitwise AND between the read result and the value specified by AndData, and
 707   writes the result to the 16-bit PCI configuration register specified by
 708   Address. The value written to the PCI configuration register is returned.
 709   This function must guarantee that all PCI read and write operations are
 710   serialized. Extra left bits in AndData are stripped.
 711
 712   If any reserved bits in Address are set, then ASSERT().
 713   If Address is not aligned on a 16-bit boundary, then ASSERT().
 714   If StartBit is greater than 15, then ASSERT().
 715   If EndBit is greater than 15, then ASSERT().
 716   If EndBit is less than StartBit, then ASSERT().
 717   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 718
 719   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 720   @param  StartBit  The ordinal of the least significant bit in the bit field.
 721                     Range 0..15.
 722   @param  EndBit    The ordinal of the most significant bit in the bit field.
 723                     Range 0..15.
 724   @param  AndData   The value to AND with the PCI configuration register.
 725
 726   @return The value written back to the PCI configuration register.
 727
 728 **/
 729 UINT16
 730 EFIAPI
 731 S3PciSegmentBitFieldAnd16 (
 732   IN UINT64  Address,
 733   IN UINTN   StartBit,
 734   IN UINTN   EndBit,
 735   IN UINT16  AndData
 736   )
 737 {
 738   return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldAnd16 (Address, StartBit, EndBit, AndData));
 739 }
 740
 741 /**
 742   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 743   bitwise OR, writes the result back to the bit field in the 16-bit port,
 744   and saves the value in the S3 script to be replayed on S3 resume.
 745
 746   Reads the 16-bit PCI configuration register specified by Address, performs a
 747   bitwise AND followed by a bitwise OR between the read result and
 748   the value specified by AndData, and writes the result to the 16-bit PCI
 749   configuration register specified by Address. The value written to the PCI
 750   configuration register is returned. This function must guarantee that all PCI
 751   read and write operations are serialized. Extra left bits in both AndData and
 752   OrData are stripped.
 753
 754   If any reserved bits in Address are set, then ASSERT().
 755   If StartBit is greater than 15, then ASSERT().
 756   If EndBit is greater than 15, then ASSERT().
 757   If EndBit is less than StartBit, then ASSERT().
 758   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 759   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 760
 761   @param  Address   PCI configuration register to write.
 762   @param  StartBit  The ordinal of the least significant bit in the bit field.
 763                     Range 0..15.
 764   @param  EndBit    The ordinal of the most significant bit in the bit field.
 765                     Range 0..15.
 766   @param  AndData   The value to AND with the PCI configuration register.
 767   @param  OrData    The value to OR with the result of the AND operation.
 768
 769   @return The value written back to the PCI configuration register.
 770
 771 **/
 772 UINT16
 773 EFIAPI
 774 S3PciSegmentBitFieldAndThenOr16 (
 775   IN UINT64  Address,
 776   IN UINTN   StartBit,
 777   IN UINTN   EndBit,
 778   IN UINT16  AndData,
 779   IN UINT16  OrData
 780   )
 781 {
 782   return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData));
 783 }
 784
 785 /**
 786   Saves a 32-bit PCI configuration value to the boot script.
 787
 788   This internal worker function saves a 32-bit PCI configuration value in the S3 script
 789   to be replayed on S3 resume.
 790
 791   If the saving process fails, then ASSERT().
 792
 793   @param  Address Address that encodes the PCI Bus, Device, Function and
 794                   Register.
 795   @param  Value   The value saved to boot script.
 796
 797   @return Value.
 798
 799 **/
 800 UINT32
 801 InternalSavePciSegmentWrite32ValueToBootScript (
 802   IN UINT64  Address,
 803   IN UINT32  Value
 804   )
 805 {
 806   InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint32, Address, &Value);
 807
 808   return Value;
 809 }
 810
 811 /**
 812   Reads a 32-bit PCI configuration register, and saves the value in the S3 script
 813   to be replayed on S3 resume.
 814
 815   Reads and returns the 32-bit PCI configuration register specified by Address.
 816   This function must guarantee that all PCI read and write operations are serialized.
 817
 818   If any reserved bits in Address are set, then ASSERT().
 819   If Address is not aligned on a 32-bit boundary, then ASSERT().
 820
 821   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 822
 823   @return The 32-bit PCI configuration register specified by Address.
 824
 825 **/
 826 UINT32
 827 EFIAPI
 828 S3PciSegmentRead32 (
 829   IN UINT64  Address
 830   )
 831 {
 832   return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentRead32 (Address));
 833 }
 834
 835 /**
 836   Writes a 32-bit PCI configuration register, and saves the value in the S3 script to
 837   be replayed on S3 resume.
 838
 839   Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
 840   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 841
 842   If any reserved bits in Address are set, then ASSERT().
 843   If Address is not aligned on a 32-bit boundary, then ASSERT().
 844
 845   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 846   @param  Value       The value to write.
 847
 848   @return The parameter of Value.
 849
 850 **/
 851 UINT32
 852 EFIAPI
 853 S3PciSegmentWrite32 (
 854   IN UINT64  Address,
 855   IN UINT32  Value
 856   )
 857 {
 858   return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentWrite32 (Address, Value));
 859 }
 860
 861 /**
 862   Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit
 863   value, and saves the value in the S3 script to be replayed on S3 resume.
 864
 865   Reads the 32-bit PCI configuration register specified by Address, performs a
 866   bitwise OR between the read result and the value specified by OrData, and
 867   writes the result to the 32-bit PCI configuration register specified by Address.
 868   The value written to the PCI configuration register is returned. This function
 869   must guarantee that all PCI read and write operations are serialized.
 870
 871   If any reserved bits in Address are set, then ASSERT().
 872   If Address is not aligned on a 32-bit boundary, then ASSERT().
 873
 874   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and
 875                     Register.
 876   @param  OrData    The value to OR with the PCI configuration register.
 877
 878   @return The value written back to the PCI configuration register.
 879
 880 **/
 881 UINT32
 882 EFIAPI
 883 S3PciSegmentOr32 (
 884   IN UINT64  Address,
 885   IN UINT32  OrData
 886   )
 887 {
 888   return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentOr32 (Address, OrData));
 889 }
 890
 891 /**
 892   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, and
 893   saves the value in the S3 script to be replayed on S3 resume.
 894
 895   Reads the 32-bit PCI configuration register specified by Address,
 896   performs a bitwise AND between the read result and the value specified by AndData,
 897   and writes the result to the 32-bit PCI configuration register specified by Address.
 898   The value written to the PCI configuration register is returned.
 899   This function must guarantee that all PCI read and write operations are serialized.
 900
 901   If any reserved bits in Address are set, then ASSERT().
 902   If Address is not aligned on a 32-bit boundary, then ASSERT().
 903
 904   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 905   @param  AndData   The value to AND with the PCI configuration register.
 906
 907   @return The value written to the PCI configuration register.
 908
 909 **/
 910 UINT32
 911 EFIAPI
 912 S3PciSegmentAnd32 (
 913   IN UINT64  Address,
 914   IN UINT32  AndData
 915   )
 916 {
 917   return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentAnd32 (Address, AndData));
 918 }
 919
 920 /**
 921   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
 922   followed a bitwise OR with another 32-bit value, and saves the value in the S3 script to
 923   be replayed on S3 resume.
 924
 925   Reads the 32-bit PCI configuration register specified by Address,
 926   performs a bitwise AND between the read result and the value specified by AndData,
 927   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
 928   and writes the result to the 32-bit PCI configuration register specified by Address.
 929   The value written to the PCI configuration register is returned.
 930   This function must guarantee that all PCI read and write operations are serialized.
 931
 932   If any reserved bits in Address are set, then ASSERT().
 933   If Address is not aligned on a 32-bit boundary, then ASSERT().
 934
 935   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 936   @param  AndData   The value to AND with the PCI configuration register.
 937   @param  OrData    The value to OR with the PCI configuration register.
 938
 939   @return The value written to the PCI configuration register.
 940
 941 **/
 942 UINT32
 943 EFIAPI
 944 S3PciSegmentAndThenOr32 (
 945   IN UINT64  Address,
 946   IN UINT32  AndData,
 947   IN UINT32  OrData
 948   )
 949 {
 950   return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentAndThenOr32 (Address, AndData, OrData));
 951 }
 952
 953 /**
 954   Reads a bit field of a PCI configuration register, and saves the value in the
 955   S3 script to be replayed on S3 resume.
 956
 957   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 958   specified by the StartBit and the EndBit. The value of the bit field is
 959   returned.
 960
 961   If any reserved bits in Address are set, then ASSERT().
 962   If Address is not aligned on a 32-bit boundary, then ASSERT().
 963   If StartBit is greater than 31, then ASSERT().
 964   If EndBit is greater than 31, then ASSERT().
 965   If EndBit is less than StartBit, then ASSERT().
 966
 967   @param  Address   PCI configuration register to read.
 968   @param  StartBit  The ordinal of the least significant bit in the bit field.
 969                     Range 0..31.
 970   @param  EndBit    The ordinal of the most significant bit in the bit field.
 971                     Range 0..31.
 972
 973   @return The value of the bit field read from the PCI configuration register.
 974
 975 **/
 976 UINT32
 977 EFIAPI
 978 S3PciSegmentBitFieldRead32 (
 979   IN UINT64  Address,
 980   IN UINTN   StartBit,
 981   IN UINTN   EndBit
 982   )
 983 {
 984   return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldRead32 (Address, StartBit, EndBit));
 985 }
 986
 987 /**
 988   Writes a bit field to a PCI configuration register, and saves the value in
 989   the S3 script to be replayed on S3 resume.
 990
 991   Writes Value to the bit field of the PCI configuration register. The bit
 992   field is specified by the StartBit and the EndBit. All other bits in the
 993   destination PCI configuration register are preserved. The new value of the
 994   32-bit register is returned.
 995
 996   If any reserved bits in Address are set, then ASSERT().
 997   If Address is not aligned on a 32-bit boundary, then ASSERT().
 998   If StartBit is greater than 31, then ASSERT().
 999   If EndBit is greater than 31, then ASSERT().
1000   If EndBit is less than StartBit, then ASSERT().
1001   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1002
1003   @param  Address   PCI configuration register to write.
1004   @param  StartBit  The ordinal of the least significant bit in the bit field.
1005                     Range 0..31.
1006   @param  EndBit    The ordinal of the most significant bit in the bit field.
1007                     Range 0..31.
1008   @param  Value     New value of the bit field.
1009
1010   @return The value written back to the PCI configuration register.
1011
1012 **/
1013 UINT32
1014 EFIAPI
1015 S3PciSegmentBitFieldWrite32 (
1016   IN UINT64  Address,
1017   IN UINTN   StartBit,
1018   IN UINTN   EndBit,
1019   IN UINT32  Value
1020   )
1021 {
1022   return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldWrite32 (Address, StartBit, EndBit, Value));
1023 }
1024
1025 /**
1026   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, writes
1027   the result back to the bit field in the 32-bit port, and saves the value in the
1028   S3 script to be replayed on S3 resume.
1029
1030   Reads the 32-bit PCI configuration register specified by Address, performs a
1031   bitwise OR between the read result and the value specified by
1032   OrData, and writes the result to the 32-bit PCI configuration register
1033   specified by Address. The value written to the PCI configuration register is
1034   returned. This function must guarantee that all PCI read and write operations
1035   are serialized. Extra left bits in OrData are stripped.
1036
1037   If any reserved bits in Address are set, then ASSERT().
1038   If Address is not aligned on a 32-bit boundary, then ASSERT().
1039   If StartBit is greater than 31, then ASSERT().
1040   If EndBit is greater than 31, then ASSERT().
1041   If EndBit is less than StartBit, then ASSERT().
1042   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1043
1044   @param  Address   PCI configuration register to write.
1045   @param  StartBit  The ordinal of the least significant bit in the bit field.
1046                     Range 0..31.
1047   @param  EndBit    The ordinal of the most significant bit in the bit field.
1048                     Range 0..31.
1049   @param  OrData    The value to OR with the PCI configuration register.
1050
1051   @return The value written back to the PCI configuration register.
1052
1053 **/
1054 UINT32
1055 EFIAPI
1056 S3PciSegmentBitFieldOr32 (
1057   IN UINT64  Address,
1058   IN UINTN   StartBit,
1059   IN UINTN   EndBit,
1060   IN UINT32  OrData
1061   )
1062 {
1063   return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldOr32 (Address, StartBit, EndBit, OrData));
1064 }
1065
1066 /**
1067   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1068   AND, and writes the result back to the bit field in the 32-bit register, and
1069   saves the value in the S3 script to be replayed on S3 resume.
1070
1071   Reads the 32-bit PCI configuration register specified by Address, performs a
1072   bitwise AND between the read result and the value specified by AndData, and
1073   writes the result to the 32-bit PCI configuration register specified by
1074   Address. The value written to the PCI configuration register is returned.
1075   This function must guarantee that all PCI read and write operations are
1076   serialized. Extra left bits in AndData are stripped.
1077
1078   If any reserved bits in Address are set, then ASSERT().
1079   If Address is not aligned on a 32-bit boundary, then ASSERT().
1080   If StartBit is greater than 31, then ASSERT().
1081   If EndBit is greater than 31, then ASSERT().
1082   If EndBit is less than StartBit, then ASSERT().
1083   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1084
1085   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
1086   @param  StartBit  The ordinal of the least significant bit in the bit field.
1087                     Range 0..31.
1088   @param  EndBit    The ordinal of the most significant bit in the bit field.
1089                     Range 0..31.
1090   @param  AndData   The value to AND with the PCI configuration register.
1091
1092   @return The value written back to the PCI configuration register.
1093
1094 **/
1095 UINT32
1096 EFIAPI
1097 S3PciSegmentBitFieldAnd32 (
1098   IN UINT64  Address,
1099   IN UINTN   StartBit,
1100   IN UINTN   EndBit,
1101   IN UINT32  AndData
1102   )
1103 {
1104   return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldAnd32 (Address, StartBit, EndBit, AndData));
1105 }
1106
1107 /**
1108   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1109   bitwise OR, writes the result back to the bit field in the 32-bit port,
1110   and saves the value in the S3 script to be replayed on S3 resume.
1111
1112   Reads the 32-bit PCI configuration register specified by Address, performs a
1113   bitwise AND followed by a bitwise OR between the read result and
1114   the value specified by AndData, and writes the result to the 32-bit PCI
1115   configuration register specified by Address. The value written to the PCI
1116   configuration register is returned. This function must guarantee that all PCI
1117   read and write operations are serialized. Extra left bits in both AndData and
1118   OrData are stripped.
1119
1120   If any reserved bits in Address are set, then ASSERT().
1121   If StartBit is greater than 31, then ASSERT().
1122   If EndBit is greater than 31, then ASSERT().
1123   If EndBit is less than StartBit, then ASSERT().
1124   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1125   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1126
1127   @param  Address   PCI configuration register to write.
1128   @param  StartBit  The ordinal of the least significant bit in the bit field.
1129                     Range 0..31.
1130   @param  EndBit    The ordinal of the most significant bit in the bit field.
1131                     Range 0..31.
1132   @param  AndData   The value to AND with the PCI configuration register.
1133   @param  OrData    The value to OR with the result of the AND operation.
1134
1135   @return The value written back to the PCI configuration register.
1136
1137 **/
1138 UINT32
1139 EFIAPI
1140 S3PciSegmentBitFieldAndThenOr32 (
1141   IN UINT64  Address,
1142   IN UINTN   StartBit,
1143   IN UINTN   EndBit,
1144   IN UINT32  AndData,
1145   IN UINT32  OrData
1146   )
1147 {
1148   return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData));
1149 }
1150
1151 /**
1152   Reads a range of PCI configuration registers into a caller supplied buffer,
1153   and saves the value in the S3 script to be replayed on S3 resume.
1154
1155   Reads the range of PCI configuration registers specified by StartAddress and
1156   Size into the buffer specified by Buffer. This function only allows the PCI
1157   configuration registers from a single PCI function to be read. Size is
1158   returned. When possible 32-bit PCI configuration read cycles are used to read
1159   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1160   and 16-bit PCI configuration read cycles may be used at the beginning and the
1161   end of the range.
1162
1163   If any reserved bits in StartAddress are set, then ASSERT().
1164   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1165   If Size > 0 and Buffer is NULL, then ASSERT().
1166
1167   @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,
1168                         Function and Register.
1169   @param  Size          Size in bytes of the transfer.
1170   @param  Buffer        Pointer to a buffer receiving the data read.
1171
1172   @return Size
1173
1174 **/
1175 UINTN
1176 EFIAPI
1177 S3PciSegmentReadBuffer (
1178   IN  UINT64  StartAddress,
1179   IN  UINTN   Size,
1180   OUT VOID    *Buffer
1181   )
1182 {
1183   RETURN_STATUS  Status;
1184
1185   Status = S3BootScriptSavePciCfg2Write (
1186              S3BootScriptWidthUint8,
1187              RShiftU64 (StartAddress, 32) & 0xffff,
1188              PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS (StartAddress),
1189              PciSegmentReadBuffer (StartAddress, Size, Buffer),
1190              Buffer
1191              );
1192   ASSERT_RETURN_ERROR (Status);
1193   return Size;
1194 }
1195
1196 /**
1197   Copies the data in a caller supplied buffer to a specified range of PCI
1198   configuration space, and saves the value in the S3 script to be replayed on S3
1199   resume.
1200
1201   Writes the range of PCI configuration registers specified by StartAddress and
1202   Size from the buffer specified by Buffer. This function only allows the PCI
1203   configuration registers from a single PCI function to be written. Size is
1204   returned. When possible 32-bit PCI configuration write cycles are used to
1205   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1206   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1207   and the end of the range.
1208
1209   If any reserved bits in StartAddress are set, then ASSERT().
1210   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1211   If Size > 0 and Buffer is NULL, then ASSERT().
1212
1213   @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,
1214                         Function and Register.
1215   @param  Size          Size in bytes of the transfer.
1216   @param  Buffer        Pointer to a buffer containing the data to write.
1217
1218   @return The parameter of Size.
1219
1220 **/
1221 UINTN
1222 EFIAPI
1223 S3PciSegmentWriteBuffer (
1224   IN UINT64  StartAddress,
1225   IN UINTN   Size,
1226   IN VOID    *Buffer
1227   )
1228 {
1229   RETURN_STATUS  Status;
1230
1231   Status = S3BootScriptSavePciCfg2Write (
1232              S3BootScriptWidthUint8,
1233              RShiftU64 (StartAddress, 32) & 0xffff,
1234              PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS (StartAddress),
1235              PciSegmentWriteBuffer (StartAddress, Size, Buffer),
1236              Buffer
1237              );
1238   ASSERT_RETURN_ERROR (Status);
1239   return Size;
1240 }