2 Functions in this library instance make use of MMIO functions in IoLib to
3 access memory mapped PCI configuration space.
5 All assertions for I/O operations are handled in MMIO functions in the IoLib
8 Copyright (c) 2006 - 2008, Intel Corporation<BR>
9 All rights reserved. This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 #include <Library/BaseLib.h>
23 #include <Library/PciExpressLib.h>
24 #include <Library/IoLib.h>
25 #include <Library/DebugLib.h>
26 #include <Library/PcdLib.h>
27 #include <Library/MemoryAllocationLib.h>
28 #include <Library/UefiBootServicesTableLib.h>
29 #include <Library/DxeServicesTableLib.h>
30 #include <Library/UefiRuntimeLib.h>
33 /// Define table for mapping PCI Express MMIO physical addresses to virtual addresses at OS runtime
36 UINTN PhysicalAddress
;
38 } PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE
;
41 /// Set Virtual Address Map Event
43 EFI_EVENT mDxeRuntimePciExpressLibVirtualNotifyEvent
= NULL
;
46 /// Module global that contains the base physical address of the PCI Express MMIO range
48 UINTN mDxeRuntimePciExpressLibPciExpressBaseAddress
= 0;
51 /// The number of PCI devices that have been registered for runtime access
53 UINTN mDxeRuntimePciExpressLibNumberOfRuntimeRanges
= 0;
56 /// The table of PCI devices that have been registered for runtime access
58 PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE
*mDxeRuntimePciExpressLibRegistrationTable
= NULL
;
61 /// The table index of the most recent virtual address lookup
63 UINTN mDxeRuntimePciExpressLibLastRuntimeRange
= 0;
67 Convert the physical PCI Express MMIO addresses for all registered PCI devices
70 @param[in] Event The Event that is being processed
71 @param[in] Context Event Context
75 DxeRuntimePciExpressLibVirtualNotify (
83 // If there have been no runtime registrations, then just return
85 if (mDxeRuntimePciExpressLibRegistrationTable
== NULL
) {
90 // Convert physical addresses associated with the set of registered PCI devices to
93 for (Index
= 0; Index
< mDxeRuntimePciExpressLibNumberOfRuntimeRanges
; Index
++) {
94 EfiConvertPointer (0, (VOID
**) &(mDxeRuntimePciExpressLibRegistrationTable
[Index
].VirtualAddress
));
98 // Convert table pointer that is allocated from EfiRuntimeServicesData to a virtual address.
100 EfiConvertPointer (0, (VOID
**) &mDxeRuntimePciExpressLibRegistrationTable
);
104 The constructor function caches the PCI Express Base Address and creates a
105 Set Virtual Address Map event to convert physical address to virtual addresses.
107 @param ImageHandle The firmware allocated handle for the EFI image.
108 @param SystemTable A pointer to the EFI System Table.
110 @retval EFI_SUCCESS The constructor completed successfully.
111 @retval Other value The constructor did not complete successfully.
116 DxeRuntimePciExpressLibConstructor (
117 IN EFI_HANDLE ImageHandle
,
118 IN EFI_SYSTEM_TABLE
*SystemTable
124 // Cache the physical address of the PCI Express MMIO range into a module global variable
126 mDxeRuntimePciExpressLibPciExpressBaseAddress
= (UINTN
) PcdGet64 (PcdPciExpressBaseAddress
);
129 // Register SetVirtualAddressMap () notify function
131 Status
= gBS
->CreateEvent (
132 EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE
,
134 DxeRuntimePciExpressLibVirtualNotify
,
136 &mDxeRuntimePciExpressLibVirtualNotifyEvent
138 ASSERT_EFI_ERROR (Status
);
144 The destructor function frees any allocated buffers and closes the Set Virtual
147 @param ImageHandle The firmware allocated handle for the EFI image.
148 @param SystemTable A pointer to the EFI System Table.
150 @retval EFI_SUCCESS The destructor completed successfully.
151 @retval Other value The destructor did not complete successfully.
156 DxeRuntimePciExpressLibDestructor (
157 IN EFI_HANDLE ImageHandle
,
158 IN EFI_SYSTEM_TABLE
*SystemTable
164 // If one or more PCI devices have been registered for runtime access, then
165 // free the registration table.
167 if (mDxeRuntimePciExpressLibRegistrationTable
!= NULL
) {
168 FreePool (mDxeRuntimePciExpressLibRegistrationTable
);
172 // Close the Set Virtual Address Map event
174 Status
= gBS
->CloseEvent (mDxeRuntimePciExpressLibVirtualNotifyEvent
);
175 ASSERT_EFI_ERROR (Status
);
181 Gets the base address of PCI Express.
183 This internal functions retrieves PCI Express Base Address via a PCD entry
184 PcdPciExpressBaseAddress.
186 @return The base address of PCI Express.
190 GetPciExpressAddress (
197 // Make sure Address is valid
199 ASSERT (((Address
) & ~0xfffffff) == 0);
202 // Convert Address to a physical address in the MMIO PCI Express range
204 Address
+= mDxeRuntimePciExpressLibPciExpressBaseAddress
;
207 // If SetVirtualAddressMap() has not been called, then just return the physical address
209 if (!EfiGoneVirtual ()) {
214 // See if there is a physical address match at the exact same index as the last address match
216 if (mDxeRuntimePciExpressLibRegistrationTable
[mDxeRuntimePciExpressLibLastRuntimeRange
].PhysicalAddress
== (Address
& 0x0ffff000)) {
218 // Convert the physical address to a virtual address and return the virtual address
220 return (Address
& 0x00000fff) + mDxeRuntimePciExpressLibRegistrationTable
[mDxeRuntimePciExpressLibLastRuntimeRange
].VirtualAddress
;
224 // Search the entire table for a phyical address match
226 for (Index
= 0; Index
< mDxeRuntimePciExpressLibNumberOfRuntimeRanges
; Index
++) {
227 if (mDxeRuntimePciExpressLibRegistrationTable
[Index
].PhysicalAddress
== (Address
& 0x0ffff000)) {
229 // Cache the matching index value
231 mDxeRuntimePciExpressLibLastRuntimeRange
= Index
;
233 // Convert the physical address to a virtual address and return the virtual address
235 return (Address
& 0x00000fff) + mDxeRuntimePciExpressLibRegistrationTable
[Index
].VirtualAddress
;
240 // No match was found. This is a critical error at OS runtime, so ASSERT() and force a breakpoint.
246 // Return the physical address
252 Register a PCI device so PCI configuration registers may be accessed after
253 SetVirtualAddressMap().
255 If Address > 0x0FFFFFFF, then ASSERT().
257 @param Address Address that encodes the PCI Bus, Device, Function and
260 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
261 @retval RETURN_UNSUPPORTED An attempt was made to call this function
262 after ExitBootServices().
263 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
264 at runtime could not be mapped.
265 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
266 complete the registration.
271 PciExpressRegisterForRuntimeAccess (
276 EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor
;
281 // Return an error if this function is called after ExitBootServices().
283 if (EfiAtRuntime ()) {
284 return RETURN_UNSUPPORTED
;
288 // Make sure Address is valid
290 ASSERT (((Address
) & ~0xfffffff) == 0);
293 // Convert Address to a physical address in the MMIO PCI Express range
294 // at the beginning of the PCI Configuration header for the specified
297 Address
= GetPciExpressAddress (Address
& 0x0ffff000);
300 // See if Address has already been registerd for runtime access
302 for (Index
= 0; Index
< mDxeRuntimePciExpressLibNumberOfRuntimeRanges
; Index
++) {
303 if (mDxeRuntimePciExpressLibRegistrationTable
[Index
].PhysicalAddress
== Address
) {
304 return RETURN_SUCCESS
;
309 // Get the GCD Memory Descriptor for the PCI Express Bus/Dev/Func specified by Address
311 Status
= gDS
->GetMemorySpaceDescriptor (Address
, &Descriptor
);
312 if (EFI_ERROR (Status
)) {
313 return RETURN_UNSUPPORTED
;
317 // Mark the 4KB region for the PCI Express Bus/Dev/Func as EFI_RUNTIME_MEMORY so the OS
318 // will allocate a virtual address range for the 4KB PCI Configuration Header.
320 Status
= gDS
->SetMemorySpaceAttributes (Address
, 0x1000, Descriptor
.Attributes
| EFI_MEMORY_RUNTIME
);
321 if (EFI_ERROR (Status
)) {
322 return RETURN_UNSUPPORTED
;
326 // Grow the size of the registration table
328 NewTable
= ReallocateRuntimePool (
329 (mDxeRuntimePciExpressLibNumberOfRuntimeRanges
+ 0) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE
),
330 (mDxeRuntimePciExpressLibNumberOfRuntimeRanges
+ 1) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE
),
331 mDxeRuntimePciExpressLibRegistrationTable
333 if (NewTable
== NULL
) {
334 return RETURN_OUT_OF_RESOURCES
;
336 mDxeRuntimePciExpressLibRegistrationTable
= NewTable
;
337 mDxeRuntimePciExpressLibRegistrationTable
[mDxeRuntimePciExpressLibNumberOfRuntimeRanges
].PhysicalAddress
= Address
;
338 mDxeRuntimePciExpressLibRegistrationTable
[mDxeRuntimePciExpressLibNumberOfRuntimeRanges
].VirtualAddress
= Address
;
339 mDxeRuntimePciExpressLibNumberOfRuntimeRanges
++;
341 return RETURN_SUCCESS
;
346 Reads an 8-bit PCI configuration register.
348 Reads and returns the 8-bit PCI configuration register specified by Address.
349 This function must guarantee that all PCI read and write operations are
352 If Address > 0x0FFFFFFF, then ASSERT().
354 @param Address Address that encodes the PCI Bus, Device, Function and
357 @return The read value from the PCI configuration register.
366 return MmioRead8 (GetPciExpressAddress (Address
));
370 Writes an 8-bit PCI configuration register.
372 Writes the 8-bit PCI configuration register specified by Address with the
373 value specified by Value. Value is returned. This function must guarantee
374 that all PCI read and write operations are serialized.
376 If Address > 0x0FFFFFFF, then ASSERT().
378 @param Address Address that encodes the PCI Bus, Device, Function and
380 @param Value The value to write.
382 @return The value written to the PCI configuration register.
392 return MmioWrite8 (GetPciExpressAddress (Address
), Value
);
396 Performs a bitwise OR of an 8-bit PCI configuration register with
399 Reads the 8-bit PCI configuration register specified by Address, performs a
400 bitwise OR between the read result and the value specified by
401 OrData, and writes the result to the 8-bit PCI configuration register
402 specified by Address. The value written to the PCI configuration register is
403 returned. This function must guarantee that all PCI read and write operations
406 If Address > 0x0FFFFFFF, then ASSERT().
408 @param Address Address that encodes the PCI Bus, Device, Function and
410 @param OrData The value to OR with the PCI configuration register.
412 @return The value written back to the PCI configuration register.
422 return MmioOr8 (GetPciExpressAddress (Address
), OrData
);
426 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
429 Reads the 8-bit PCI configuration register specified by Address, performs a
430 bitwise AND between the read result and the value specified by AndData, and
431 writes the result to the 8-bit PCI configuration register specified by
432 Address. The value written to the PCI configuration register is returned.
433 This function must guarantee that all PCI read and write operations are
436 If Address > 0x0FFFFFFF, then ASSERT().
438 @param Address Address that encodes the PCI Bus, Device, Function and
440 @param AndData The value to AND with the PCI configuration register.
442 @return The value written back to the PCI configuration register.
452 return MmioAnd8 (GetPciExpressAddress (Address
), AndData
);
456 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
457 value, followed a bitwise OR with another 8-bit value.
459 Reads the 8-bit PCI configuration register specified by Address, performs a
460 bitwise AND between the read result and the value specified by AndData,
461 performs a bitwise OR between the result of the AND operation and
462 the value specified by OrData, and writes the result to the 8-bit PCI
463 configuration register specified by Address. The value written to the PCI
464 configuration register is returned. This function must guarantee that all PCI
465 read and write operations are serialized.
467 If Address > 0x0FFFFFFF, then ASSERT().
469 @param Address Address that encodes the PCI Bus, Device, Function and
471 @param AndData The value to AND with the PCI configuration register.
472 @param OrData The value to OR with the result of the AND operation.
474 @return The value written back to the PCI configuration register.
479 PciExpressAndThenOr8 (
485 return MmioAndThenOr8 (
486 GetPciExpressAddress (Address
),
493 Reads a bit field of a PCI configuration register.
495 Reads the bit field in an 8-bit PCI configuration register. The bit field is
496 specified by the StartBit and the EndBit. The value of the bit field is
499 If Address > 0x0FFFFFFF, then ASSERT().
500 If StartBit is greater than 7, then ASSERT().
501 If EndBit is greater than 7, then ASSERT().
502 If EndBit is less than StartBit, then ASSERT().
504 @param Address PCI configuration register to read.
505 @param StartBit The ordinal of the least significant bit in the bit field.
507 @param EndBit The ordinal of the most significant bit in the bit field.
510 @return The value of the bit field read from the PCI configuration register.
515 PciExpressBitFieldRead8 (
521 return MmioBitFieldRead8 (
522 GetPciExpressAddress (Address
),
529 Writes a bit field to a PCI configuration register.
531 Writes Value to the bit field of the PCI configuration register. The bit
532 field is specified by the StartBit and the EndBit. All other bits in the
533 destination PCI configuration register are preserved. The new value of the
534 8-bit register is returned.
536 If Address > 0x0FFFFFFF, then ASSERT().
537 If StartBit is greater than 7, then ASSERT().
538 If EndBit is greater than 7, then ASSERT().
539 If EndBit is less than StartBit, then ASSERT().
541 @param Address PCI configuration register to write.
542 @param StartBit The ordinal of the least significant bit in the bit field.
544 @param EndBit The ordinal of the most significant bit in the bit field.
546 @param Value New value of the bit field.
548 @return The value written back to the PCI configuration register.
553 PciExpressBitFieldWrite8 (
560 return MmioBitFieldWrite8 (
561 GetPciExpressAddress (Address
),
569 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
570 writes the result back to the bit field in the 8-bit port.
572 Reads the 8-bit PCI configuration register specified by Address, performs a
573 bitwise OR between the read result and the value specified by
574 OrData, and writes the result to the 8-bit PCI configuration register
575 specified by Address. The value written to the PCI configuration register is
576 returned. This function must guarantee that all PCI read and write operations
577 are serialized. Extra left bits in OrData are stripped.
579 If Address > 0x0FFFFFFF, then ASSERT().
580 If StartBit is greater than 7, then ASSERT().
581 If EndBit is greater than 7, then ASSERT().
582 If EndBit is less than StartBit, then ASSERT().
584 @param Address PCI configuration register to write.
585 @param StartBit The ordinal of the least significant bit in the bit field.
587 @param EndBit The ordinal of the most significant bit in the bit field.
589 @param OrData The value to OR with the PCI configuration register.
591 @return The value written back to the PCI configuration register.
596 PciExpressBitFieldOr8 (
603 return MmioBitFieldOr8 (
604 GetPciExpressAddress (Address
),
612 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
613 AND, and writes the result back to the bit field in the 8-bit register.
615 Reads the 8-bit PCI configuration register specified by Address, performs a
616 bitwise AND between the read result and the value specified by AndData, and
617 writes the result to the 8-bit PCI configuration register specified by
618 Address. The value written to the PCI configuration register is returned.
619 This function must guarantee that all PCI read and write operations are
620 serialized. Extra left bits in AndData are stripped.
622 If Address > 0x0FFFFFFF, then ASSERT().
623 If StartBit is greater than 7, then ASSERT().
624 If EndBit is greater than 7, then ASSERT().
625 If EndBit is less than StartBit, then ASSERT().
627 @param Address PCI configuration register to write.
628 @param StartBit The ordinal of the least significant bit in the bit field.
630 @param EndBit The ordinal of the most significant bit in the bit field.
632 @param AndData The value to AND with the PCI configuration register.
634 @return The value written back to the PCI configuration register.
639 PciExpressBitFieldAnd8 (
646 return MmioBitFieldAnd8 (
647 GetPciExpressAddress (Address
),
655 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
656 bitwise OR, and writes the result back to the bit field in the
659 Reads the 8-bit PCI configuration register specified by Address, performs a
660 bitwise AND followed by a bitwise OR between the read result and
661 the value specified by AndData, and writes the result to the 8-bit PCI
662 configuration register specified by Address. The value written to the PCI
663 configuration register is returned. This function must guarantee that all PCI
664 read and write operations are serialized. Extra left bits in both AndData and
667 If Address > 0x0FFFFFFF, then ASSERT().
668 If StartBit is greater than 7, then ASSERT().
669 If EndBit is greater than 7, then ASSERT().
670 If EndBit is less than StartBit, then ASSERT().
672 @param Address PCI configuration register to write.
673 @param StartBit The ordinal of the least significant bit in the bit field.
675 @param EndBit The ordinal of the most significant bit in the bit field.
677 @param AndData The value to AND with the PCI configuration register.
678 @param OrData The value to OR with the result of the AND operation.
680 @return The value written back to the PCI configuration register.
685 PciExpressBitFieldAndThenOr8 (
693 return MmioBitFieldAndThenOr8 (
694 GetPciExpressAddress (Address
),
703 Reads a 16-bit PCI configuration register.
705 Reads and returns the 16-bit PCI configuration register specified by Address.
706 This function must guarantee that all PCI read and write operations are
709 If Address > 0x0FFFFFFF, then ASSERT().
710 If Address is not aligned on a 16-bit boundary, then ASSERT().
712 @param Address Address that encodes the PCI Bus, Device, Function and
715 @return The read value from the PCI configuration register.
724 return MmioRead16 (GetPciExpressAddress (Address
));
728 Writes a 16-bit PCI configuration register.
730 Writes the 16-bit PCI configuration register specified by Address with the
731 value specified by Value. Value is returned. This function must guarantee
732 that all PCI read and write operations are serialized.
734 If Address > 0x0FFFFFFF, then ASSERT().
735 If Address is not aligned on a 16-bit boundary, then ASSERT().
737 @param Address Address that encodes the PCI Bus, Device, Function and
739 @param Value The value to write.
741 @return The value written to the PCI configuration register.
751 return MmioWrite16 (GetPciExpressAddress (Address
), Value
);
755 Performs a bitwise OR of a 16-bit PCI configuration register with
758 Reads the 16-bit PCI configuration register specified by Address, performs a
759 bitwise OR between the read result and the value specified by
760 OrData, and writes the result to the 16-bit PCI configuration register
761 specified by Address. The value written to the PCI configuration register is
762 returned. This function must guarantee that all PCI read and write operations
765 If Address > 0x0FFFFFFF, then ASSERT().
766 If Address is not aligned on a 16-bit boundary, then ASSERT().
768 @param Address Address that encodes the PCI Bus, Device, Function and
770 @param OrData The value to OR with the PCI configuration register.
772 @return The value written back to the PCI configuration register.
782 return MmioOr16 (GetPciExpressAddress (Address
), OrData
);
786 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
789 Reads the 16-bit PCI configuration register specified by Address, performs a
790 bitwise AND between the read result and the value specified by AndData, and
791 writes the result to the 16-bit PCI configuration register specified by
792 Address. The value written to the PCI configuration register is returned.
793 This function must guarantee that all PCI read and write operations are
796 If Address > 0x0FFFFFFF, then ASSERT().
797 If Address is not aligned on a 16-bit boundary, then ASSERT().
799 @param Address Address that encodes the PCI Bus, Device, Function and
801 @param AndData The value to AND with the PCI configuration register.
803 @return The value written back to the PCI configuration register.
813 return MmioAnd16 (GetPciExpressAddress (Address
), AndData
);
817 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
818 value, followed a bitwise OR with another 16-bit value.
820 Reads the 16-bit PCI configuration register specified by Address, performs a
821 bitwise AND between the read result and the value specified by AndData,
822 performs a bitwise OR between the result of the AND operation and
823 the value specified by OrData, and writes the result to the 16-bit PCI
824 configuration register specified by Address. The value written to the PCI
825 configuration register is returned. This function must guarantee that all PCI
826 read and write operations are serialized.
828 If Address > 0x0FFFFFFF, then ASSERT().
829 If Address is not aligned on a 16-bit boundary, then ASSERT().
831 @param Address Address that encodes the PCI Bus, Device, Function and
833 @param AndData The value to AND with the PCI configuration register.
834 @param OrData The value to OR with the result of the AND operation.
836 @return The value written back to the PCI configuration register.
841 PciExpressAndThenOr16 (
847 return MmioAndThenOr16 (
848 GetPciExpressAddress (Address
),
855 Reads a bit field of a PCI configuration register.
857 Reads the bit field in a 16-bit PCI configuration register. The bit field is
858 specified by the StartBit and the EndBit. The value of the bit field is
861 If Address > 0x0FFFFFFF, then ASSERT().
862 If Address is not aligned on a 16-bit boundary, then ASSERT().
863 If StartBit is greater than 15, then ASSERT().
864 If EndBit is greater than 15, then ASSERT().
865 If EndBit is less than StartBit, then ASSERT().
867 @param Address PCI configuration register to read.
868 @param StartBit The ordinal of the least significant bit in the bit field.
870 @param EndBit The ordinal of the most significant bit in the bit field.
873 @return The value of the bit field read from the PCI configuration register.
878 PciExpressBitFieldRead16 (
884 return MmioBitFieldRead16 (
885 GetPciExpressAddress (Address
),
892 Writes a bit field to a PCI configuration register.
894 Writes Value to the bit field of the PCI configuration register. The bit
895 field is specified by the StartBit and the EndBit. All other bits in the
896 destination PCI configuration register are preserved. The new value of the
897 16-bit register is returned.
899 If Address > 0x0FFFFFFF, then ASSERT().
900 If Address is not aligned on a 16-bit boundary, then ASSERT().
901 If StartBit is greater than 15, then ASSERT().
902 If EndBit is greater than 15, then ASSERT().
903 If EndBit is less than StartBit, then ASSERT().
905 @param Address PCI configuration register to write.
906 @param StartBit The ordinal of the least significant bit in the bit field.
908 @param EndBit The ordinal of the most significant bit in the bit field.
910 @param Value New value of the bit field.
912 @return The value written back to the PCI configuration register.
917 PciExpressBitFieldWrite16 (
924 return MmioBitFieldWrite16 (
925 GetPciExpressAddress (Address
),
933 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
934 writes the result back to the bit field in the 16-bit port.
936 Reads the 16-bit PCI configuration register specified by Address, performs a
937 bitwise OR between the read result and the value specified by
938 OrData, and writes the result to the 16-bit PCI configuration register
939 specified by Address. The value written to the PCI configuration register is
940 returned. This function must guarantee that all PCI read and write operations
941 are serialized. Extra left bits in OrData are stripped.
943 If Address > 0x0FFFFFFF, then ASSERT().
944 If Address is not aligned on a 16-bit boundary, then ASSERT().
945 If StartBit is greater than 15, then ASSERT().
946 If EndBit is greater than 15, then ASSERT().
947 If EndBit is less than StartBit, then ASSERT().
949 @param Address PCI configuration register to write.
950 @param StartBit The ordinal of the least significant bit in the bit field.
952 @param EndBit The ordinal of the most significant bit in the bit field.
954 @param OrData The value to OR with the PCI configuration register.
956 @return The value written back to the PCI configuration register.
961 PciExpressBitFieldOr16 (
968 return MmioBitFieldOr16 (
969 GetPciExpressAddress (Address
),
977 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
978 AND, and writes the result back to the bit field in the 16-bit register.
980 Reads the 16-bit PCI configuration register specified by Address, performs a
981 bitwise AND between the read result and the value specified by AndData, and
982 writes the result to the 16-bit PCI configuration register specified by
983 Address. The value written to the PCI configuration register is returned.
984 This function must guarantee that all PCI read and write operations are
985 serialized. Extra left bits in AndData are stripped.
987 If Address > 0x0FFFFFFF, then ASSERT().
988 If Address is not aligned on a 16-bit boundary, then ASSERT().
989 If StartBit is greater than 15, then ASSERT().
990 If EndBit is greater than 15, then ASSERT().
991 If EndBit is less than StartBit, then ASSERT().
993 @param Address PCI configuration register to write.
994 @param StartBit The ordinal of the least significant bit in the bit field.
996 @param EndBit The ordinal of the most significant bit in the bit field.
998 @param AndData The value to AND with the PCI configuration register.
1000 @return The value written back to the PCI configuration register.
1005 PciExpressBitFieldAnd16 (
1012 return MmioBitFieldAnd16 (
1013 GetPciExpressAddress (Address
),
1021 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
1022 bitwise OR, and writes the result back to the bit field in the
1025 Reads the 16-bit PCI configuration register specified by Address, performs a
1026 bitwise AND followed by a bitwise OR between the read result and
1027 the value specified by AndData, and writes the result to the 16-bit PCI
1028 configuration register specified by Address. The value written to the PCI
1029 configuration register is returned. This function must guarantee that all PCI
1030 read and write operations are serialized. Extra left bits in both AndData and
1031 OrData are stripped.
1033 If Address > 0x0FFFFFFF, then ASSERT().
1034 If Address is not aligned on a 16-bit boundary, then ASSERT().
1035 If StartBit is greater than 15, then ASSERT().
1036 If EndBit is greater than 15, then ASSERT().
1037 If EndBit is less than StartBit, then ASSERT().
1039 @param Address PCI configuration register to write.
1040 @param StartBit The ordinal of the least significant bit in the bit field.
1042 @param EndBit The ordinal of the most significant bit in the bit field.
1044 @param AndData The value to AND with the PCI configuration register.
1045 @param OrData The value to OR with the result of the AND operation.
1047 @return The value written back to the PCI configuration register.
1052 PciExpressBitFieldAndThenOr16 (
1060 return MmioBitFieldAndThenOr16 (
1061 GetPciExpressAddress (Address
),
1070 Reads a 32-bit PCI configuration register.
1072 Reads and returns the 32-bit PCI configuration register specified by Address.
1073 This function must guarantee that all PCI read and write operations are
1076 If Address > 0x0FFFFFFF, then ASSERT().
1077 If Address is not aligned on a 32-bit boundary, then ASSERT().
1079 @param Address Address that encodes the PCI Bus, Device, Function and
1082 @return The read value from the PCI configuration register.
1091 return MmioRead32 (GetPciExpressAddress (Address
));
1095 Writes a 32-bit PCI configuration register.
1097 Writes the 32-bit PCI configuration register specified by Address with the
1098 value specified by Value. Value is returned. This function must guarantee
1099 that all PCI read and write operations are serialized.
1101 If Address > 0x0FFFFFFF, then ASSERT().
1102 If Address is not aligned on a 32-bit boundary, then ASSERT().
1104 @param Address Address that encodes the PCI Bus, Device, Function and
1106 @param Value The value to write.
1108 @return The value written to the PCI configuration register.
1118 return MmioWrite32 (GetPciExpressAddress (Address
), Value
);
1122 Performs a bitwise OR of a 32-bit PCI configuration register with
1125 Reads the 32-bit PCI configuration register specified by Address, performs a
1126 bitwise OR between the read result and the value specified by
1127 OrData, and writes the result to the 32-bit PCI configuration register
1128 specified by Address. The value written to the PCI configuration register is
1129 returned. This function must guarantee that all PCI read and write operations
1132 If Address > 0x0FFFFFFF, then ASSERT().
1133 If Address is not aligned on a 32-bit boundary, then ASSERT().
1135 @param Address Address that encodes the PCI Bus, Device, Function and
1137 @param OrData The value to OR with the PCI configuration register.
1139 @return The value written back to the PCI configuration register.
1149 return MmioOr32 (GetPciExpressAddress (Address
), OrData
);
1153 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
1156 Reads the 32-bit PCI configuration register specified by Address, performs a
1157 bitwise AND between the read result and the value specified by AndData, and
1158 writes the result to the 32-bit PCI configuration register specified by
1159 Address. The value written to the PCI configuration register is returned.
1160 This function must guarantee that all PCI read and write operations are
1163 If Address > 0x0FFFFFFF, then ASSERT().
1164 If Address is not aligned on a 32-bit boundary, then ASSERT().
1166 @param Address Address that encodes the PCI Bus, Device, Function and
1168 @param AndData The value to AND with the PCI configuration register.
1170 @return The value written back to the PCI configuration register.
1180 return MmioAnd32 (GetPciExpressAddress (Address
), AndData
);
1184 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
1185 value, followed a bitwise OR with another 32-bit value.
1187 Reads the 32-bit PCI configuration register specified by Address, performs a
1188 bitwise AND between the read result and the value specified by AndData,
1189 performs a bitwise OR between the result of the AND operation and
1190 the value specified by OrData, and writes the result to the 32-bit PCI
1191 configuration register specified by Address. The value written to the PCI
1192 configuration register is returned. This function must guarantee that all PCI
1193 read and write operations are serialized.
1195 If Address > 0x0FFFFFFF, then ASSERT().
1196 If Address is not aligned on a 32-bit boundary, then ASSERT().
1198 @param Address Address that encodes the PCI Bus, Device, Function and
1200 @param AndData The value to AND with the PCI configuration register.
1201 @param OrData The value to OR with the result of the AND operation.
1203 @return The value written back to the PCI configuration register.
1208 PciExpressAndThenOr32 (
1214 return MmioAndThenOr32 (
1215 GetPciExpressAddress (Address
),
1222 Reads a bit field of a PCI configuration register.
1224 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1225 specified by the StartBit and the EndBit. The value of the bit field is
1228 If Address > 0x0FFFFFFF, then ASSERT().
1229 If Address is not aligned on a 32-bit boundary, then ASSERT().
1230 If StartBit is greater than 31, then ASSERT().
1231 If EndBit is greater than 31, then ASSERT().
1232 If EndBit is less than StartBit, then ASSERT().
1234 @param Address PCI configuration register to read.
1235 @param StartBit The ordinal of the least significant bit in the bit field.
1237 @param EndBit The ordinal of the most significant bit in the bit field.
1240 @return The value of the bit field read from the PCI configuration register.
1245 PciExpressBitFieldRead32 (
1251 return MmioBitFieldRead32 (
1252 GetPciExpressAddress (Address
),
1259 Writes a bit field to a PCI configuration register.
1261 Writes Value to the bit field of the PCI configuration register. The bit
1262 field is specified by the StartBit and the EndBit. All other bits in the
1263 destination PCI configuration register are preserved. The new value of the
1264 32-bit register is returned.
1266 If Address > 0x0FFFFFFF, then ASSERT().
1267 If Address is not aligned on a 32-bit boundary, then ASSERT().
1268 If StartBit is greater than 31, then ASSERT().
1269 If EndBit is greater than 31, then ASSERT().
1270 If EndBit is less than StartBit, then ASSERT().
1272 @param Address PCI configuration register to write.
1273 @param StartBit The ordinal of the least significant bit in the bit field.
1275 @param EndBit The ordinal of the most significant bit in the bit field.
1277 @param Value New value of the bit field.
1279 @return The value written back to the PCI configuration register.
1284 PciExpressBitFieldWrite32 (
1291 return MmioBitFieldWrite32 (
1292 GetPciExpressAddress (Address
),
1300 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1301 writes the result back to the bit field in the 32-bit port.
1303 Reads the 32-bit PCI configuration register specified by Address, performs a
1304 bitwise OR between the read result and the value specified by
1305 OrData, and writes the result to the 32-bit PCI configuration register
1306 specified by Address. The value written to the PCI configuration register is
1307 returned. This function must guarantee that all PCI read and write operations
1308 are serialized. Extra left bits in OrData are stripped.
1310 If Address > 0x0FFFFFFF, then ASSERT().
1311 If Address is not aligned on a 32-bit boundary, then ASSERT().
1312 If StartBit is greater than 31, then ASSERT().
1313 If EndBit is greater than 31, then ASSERT().
1314 If EndBit is less than StartBit, then ASSERT().
1316 @param Address PCI configuration register to write.
1317 @param StartBit The ordinal of the least significant bit in the bit field.
1319 @param EndBit The ordinal of the most significant bit in the bit field.
1321 @param OrData The value to OR with the PCI configuration register.
1323 @return The value written back to the PCI configuration register.
1328 PciExpressBitFieldOr32 (
1335 return MmioBitFieldOr32 (
1336 GetPciExpressAddress (Address
),
1344 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1345 AND, and writes the result back to the bit field in the 32-bit register.
1347 Reads the 32-bit PCI configuration register specified by Address, performs a
1348 bitwise AND between the read result and the value specified by AndData, and
1349 writes the result to the 32-bit PCI configuration register specified by
1350 Address. The value written to the PCI configuration register is returned.
1351 This function must guarantee that all PCI read and write operations are
1352 serialized. Extra left bits in AndData are stripped.
1354 If Address > 0x0FFFFFFF, then ASSERT().
1355 If Address is not aligned on a 32-bit boundary, then ASSERT().
1356 If StartBit is greater than 31, then ASSERT().
1357 If EndBit is greater than 31, then ASSERT().
1358 If EndBit is less than StartBit, then ASSERT().
1360 @param Address PCI configuration register to write.
1361 @param StartBit The ordinal of the least significant bit in the bit field.
1363 @param EndBit The ordinal of the most significant bit in the bit field.
1365 @param AndData The value to AND with the PCI configuration register.
1367 @return The value written back to the PCI configuration register.
1372 PciExpressBitFieldAnd32 (
1379 return MmioBitFieldAnd32 (
1380 GetPciExpressAddress (Address
),
1388 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1389 bitwise OR, and writes the result back to the bit field in the
1392 Reads the 32-bit PCI configuration register specified by Address, performs a
1393 bitwise AND followed by a bitwise OR between the read result and
1394 the value specified by AndData, and writes the result to the 32-bit PCI
1395 configuration register specified by Address. The value written to the PCI
1396 configuration register is returned. This function must guarantee that all PCI
1397 read and write operations are serialized. Extra left bits in both AndData and
1398 OrData are stripped.
1400 If Address > 0x0FFFFFFF, then ASSERT().
1401 If Address is not aligned on a 32-bit boundary, then ASSERT().
1402 If StartBit is greater than 31, then ASSERT().
1403 If EndBit is greater than 31, then ASSERT().
1404 If EndBit is less than StartBit, then ASSERT().
1406 @param Address PCI configuration register to write.
1407 @param StartBit The ordinal of the least significant bit in the bit field.
1409 @param EndBit The ordinal of the most significant bit in the bit field.
1411 @param AndData The value to AND with the PCI configuration register.
1412 @param OrData The value to OR with the result of the AND operation.
1414 @return The value written back to the PCI configuration register.
1419 PciExpressBitFieldAndThenOr32 (
1427 return MmioBitFieldAndThenOr32 (
1428 GetPciExpressAddress (Address
),
1437 Reads a range of PCI configuration registers into a caller supplied buffer.
1439 Reads the range of PCI configuration registers specified by StartAddress and
1440 Size into the buffer specified by Buffer. This function only allows the PCI
1441 configuration registers from a single PCI function to be read. Size is
1442 returned. When possible 32-bit PCI configuration read cycles are used to read
1443 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1444 and 16-bit PCI configuration read cycles may be used at the beginning and the
1447 If StartAddress > 0x0FFFFFFF, then ASSERT().
1448 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1449 If Size > 0 and Buffer is NULL, then ASSERT().
1451 @param StartAddress Starting address that encodes the PCI Bus, Device,
1452 Function and Register.
1453 @param Size Size in bytes of the transfer.
1454 @param Buffer Pointer to a buffer receiving the data read.
1461 PciExpressReadBuffer (
1462 IN UINTN StartAddress
,
1469 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1475 ASSERT (Buffer
!= NULL
);
1478 // Save Size for return
1482 if ((StartAddress
& 1) != 0) {
1484 // Read a byte if StartAddress is byte aligned
1486 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1487 StartAddress
+= sizeof (UINT8
);
1488 Size
-= sizeof (UINT8
);
1489 Buffer
= (UINT8
*)Buffer
+ 1;
1492 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1494 // Read a word if StartAddress is word aligned
1496 WriteUnaligned16 ((UINT16
*) Buffer
, (UINT16
) PciExpressRead16 (StartAddress
));
1498 StartAddress
+= sizeof (UINT16
);
1499 Size
-= sizeof (UINT16
);
1500 Buffer
= (UINT16
*)Buffer
+ 1;
1503 while (Size
>= sizeof (UINT32
)) {
1505 // Read as many double words as possible
1507 WriteUnaligned32 ((UINT32
*) Buffer
, (UINT32
) PciExpressRead32 (StartAddress
));
1509 StartAddress
+= sizeof (UINT32
);
1510 Size
-= sizeof (UINT32
);
1511 Buffer
= (UINT32
*)Buffer
+ 1;
1514 if (Size
>= sizeof (UINT16
)) {
1516 // Read the last remaining word if exist
1518 WriteUnaligned16 ((UINT16
*) Buffer
, (UINT16
) PciExpressRead16 (StartAddress
));
1519 StartAddress
+= sizeof (UINT16
);
1520 Size
-= sizeof (UINT16
);
1521 Buffer
= (UINT16
*)Buffer
+ 1;
1524 if (Size
>= sizeof (UINT8
)) {
1526 // Read the last remaining byte if exist
1528 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1535 Copies the data in a caller supplied buffer to a specified range of PCI
1536 configuration space.
1538 Writes the range of PCI configuration registers specified by StartAddress and
1539 Size from the buffer specified by Buffer. This function only allows the PCI
1540 configuration registers from a single PCI function to be written. Size is
1541 returned. When possible 32-bit PCI configuration write cycles are used to
1542 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1543 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1544 and the end of the range.
1546 If StartAddress > 0x0FFFFFFF, then ASSERT().
1547 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1548 If Size > 0 and Buffer is NULL, then ASSERT().
1550 @param StartAddress Starting address that encodes the PCI Bus, Device,
1551 Function and Register.
1552 @param Size Size in bytes of the transfer.
1553 @param Buffer Pointer to a buffer containing the data to write.
1560 PciExpressWriteBuffer (
1561 IN UINTN StartAddress
,
1568 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1574 ASSERT (Buffer
!= NULL
);
1577 // Save Size for return
1581 if ((StartAddress
& 1) != 0) {
1583 // Write a byte if StartAddress is byte aligned
1585 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1586 StartAddress
+= sizeof (UINT8
);
1587 Size
-= sizeof (UINT8
);
1588 Buffer
= (UINT8
*)Buffer
+ 1;
1591 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1593 // Write a word if StartAddress is word aligned
1595 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1596 StartAddress
+= sizeof (UINT16
);
1597 Size
-= sizeof (UINT16
);
1598 Buffer
= (UINT16
*)Buffer
+ 1;
1601 while (Size
>= sizeof (UINT32
)) {
1603 // Write as many double words as possible
1605 PciExpressWrite32 (StartAddress
, ReadUnaligned32 ((UINT32
*)Buffer
));
1606 StartAddress
+= sizeof (UINT32
);
1607 Size
-= sizeof (UINT32
);
1608 Buffer
= (UINT32
*)Buffer
+ 1;
1611 if (Size
>= sizeof (UINT16
)) {
1613 // Write the last remaining word if exist
1615 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1616 StartAddress
+= sizeof (UINT16
);
1617 Size
-= sizeof (UINT16
);
1618 Buffer
= (UINT16
*)Buffer
+ 1;
1621 if (Size
>= sizeof (UINT8
)) {
1623 // Write the last remaining byte if exist
1625 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);