2 PCI Library using PCI CFG2 PPI.
4 Copyright (c) 2007 - 2008, Intel Corporation All rights
5 reserved. This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Ppi/PciCfg2.h>
20 #include <Library/PciLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/PeiServicesTablePointerLib.h>
23 #include <Library/DebugLib.h>
24 #include <Library/PeiServicesLib.h>
27 Assert the validity of a PCI address. A valid PCI address should contain 1's
28 only in the low 28 bits.
30 @param A The address to validate.
31 @param M Additional bits to assert to be zero.
34 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
35 ASSERT (((A) & (~0xfffffff | (M))) == 0)
38 Translate PCI Lib address into format of PCI CFG2 PPI.
40 @param A Address that encodes the PCI Bus, Device, Function and
44 #define PCI_TO_PCICFG2_ADDRESS(A) \
45 ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
48 Internal worker function to read a PCI configuration register.
50 This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.
51 It reads and returns the PCI configuration register specified by Address,
52 the width of data is specified by Width.
54 @param Address Address that encodes the PCI Bus, Device, Function and
56 @param Width Width of data to read
58 @return The value read from the PCI configuration register.
62 PeiPciLibPciCfg2ReadWorker (
64 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
69 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
71 Status
= PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid
, 0, NULL
, (VOID
**) &PciCfg2Ppi
);
72 ASSERT_EFI_ERROR (Status
);
73 ASSERT (PciCfg2Ppi
!= NULL
);
76 GetPeiServicesTablePointer (),
79 PCI_TO_PCICFG2_ADDRESS (Address
),
87 Internal worker function to writes a PCI configuration register.
89 This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.
90 It writes the PCI configuration register specified by Address with the
91 value specified by Data. The width of data is specifed by Width.
94 @param Address Address that encodes the PCI Bus, Device, Function and
96 @param Width Width of data to write
97 @param Data The value to write.
99 @return The value written to the PCI configuration register.
103 PeiPciLibPciCfg2WriteWorker (
105 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
,
110 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
112 Status
= PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid
, 0, NULL
, (VOID
**) &PciCfg2Ppi
);
113 ASSERT_EFI_ERROR (Status
);
114 ASSERT (PciCfg2Ppi
!= NULL
);
117 GetPeiServicesTablePointer (),
120 PCI_TO_PCICFG2_ADDRESS (Address
),
128 Register a PCI device so PCI configuration registers may be accessed after
129 SetVirtualAddressMap().
131 If Address > 0x0FFFFFFF, then ASSERT().
133 @param Address Address that encodes the PCI Bus, Device, Function and
136 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
137 @retval RETURN_UNSUPPORTED An attempt was made to call this function
138 after ExitBootServices().
139 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
140 at runtime could not be mapped.
141 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
142 complete the registration.
147 PciRegisterForRuntimeAccess (
151 return RETURN_UNSUPPORTED
;
155 Reads an 8-bit PCI configuration register.
157 Reads and returns the 8-bit PCI configuration register specified by Address.
158 This function must guarantee that all PCI read and write operations are
161 If Address > 0x0FFFFFFF, then ASSERT().
163 @param Address Address that encodes the PCI Bus, Device, Function and
166 @return The value read from the PCI configuration register.
175 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
177 return (UINT8
) PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint8
);
181 Writes an 8-bit PCI configuration register.
183 Writes the 8-bit PCI configuration register specified by Address with the
184 value specified by Value. Value is returned. This function must guarantee
185 that all PCI read and write operations are serialized.
187 If Address > 0x0FFFFFFF, then ASSERT().
189 @param Address Address that encodes the PCI Bus, Device, Function and
191 @param Data The value to write.
193 @return The value written to the PCI configuration register.
203 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
205 return (UINT8
) PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint8
, Data
);
209 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
212 Reads the 8-bit PCI configuration register specified by Address, performs a
213 bitwise inclusive OR between the read result and the value specified by
214 OrData, and writes the result to the 8-bit PCI configuration register
215 specified by Address. The value written to the PCI configuration register is
216 returned. This function must guarantee that all PCI read and write operations
219 If Address > 0x0FFFFFFF, then ASSERT().
221 @param Address Address that encodes the PCI Bus, Device, Function and
223 @param OrData The value to OR with the PCI configuration register.
225 @return The value written back to the PCI configuration register.
235 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) | OrData
));
239 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
242 Reads the 8-bit PCI configuration register specified by Address, performs a
243 bitwise AND between the read result and the value specified by AndData, and
244 writes the result to the 8-bit PCI configuration register specified by
245 Address. The value written to the PCI configuration register is returned.
246 This function must guarantee that all PCI read and write operations are
249 If Address > 0x0FFFFFFF, then ASSERT().
251 @param Address Address that encodes the PCI Bus, Device, Function and
253 @param AndData The value to AND with the PCI configuration register.
255 @return The value written back to the PCI configuration register.
265 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) & AndData
));
269 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
270 value, followed a bitwise inclusive OR with another 8-bit value.
272 Reads the 8-bit PCI configuration register specified by Address, performs a
273 bitwise AND between the read result and the value specified by AndData,
274 performs a bitwise inclusive OR between the result of the AND operation and
275 the value specified by OrData, and writes the result to the 8-bit PCI
276 configuration register specified by Address. The value written to the PCI
277 configuration register is returned. This function must guarantee that all PCI
278 read and write operations are serialized.
280 If Address > 0x0FFFFFFF, then ASSERT().
282 @param Address Address that encodes the PCI Bus, Device, Function and
284 @param AndData The value to AND with the PCI configuration register.
285 @param OrData The value to OR with the result of the AND operation.
287 @return The value written back to the PCI configuration register.
298 return PciWrite8 (Address
, (UINT8
) ((PciRead8 (Address
) & AndData
) | OrData
));
302 Reads a bit field of a PCI configuration register.
304 Reads the bit field in an 8-bit PCI configuration register. The bit field is
305 specified by the StartBit and the EndBit. The value of the bit field is
308 If Address > 0x0FFFFFFF, then ASSERT().
309 If StartBit is greater than 7, then ASSERT().
310 If EndBit is greater than 7, then ASSERT().
311 If EndBit is less than StartBit, then ASSERT().
313 @param Address PCI configuration register to read.
314 @param StartBit The ordinal of the least significant bit in the bit field.
316 @param EndBit The ordinal of the most significant bit in the bit field.
319 @return The value of the bit field read from the PCI configuration register.
330 return BitFieldRead8 (PciRead8 (Address
), StartBit
, EndBit
);
334 Writes a bit field to a PCI configuration register.
336 Writes Value to the bit field of the PCI configuration register. The bit
337 field is specified by the StartBit and the EndBit. All other bits in the
338 destination PCI configuration register are preserved. The new value of the
339 8-bit register is returned.
341 If Address > 0x0FFFFFFF, then ASSERT().
342 If StartBit is greater than 7, then ASSERT().
343 If EndBit is greater than 7, then ASSERT().
344 If EndBit is less than StartBit, then ASSERT().
346 @param Address PCI configuration register to write.
347 @param StartBit The ordinal of the least significant bit in the bit field.
349 @param EndBit The ordinal of the most significant bit in the bit field.
351 @param Value New value of the bit field.
353 @return The value written back to the PCI configuration register.
367 BitFieldWrite8 (PciRead8 (Address
), StartBit
, EndBit
, Value
)
372 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
373 writes the result back to the bit field in the 8-bit port.
375 Reads the 8-bit PCI configuration register specified by Address, performs a
376 bitwise inclusive OR between the read result and the value specified by
377 OrData, and writes the result to the 8-bit PCI configuration register
378 specified by Address. The value written to the PCI configuration register is
379 returned. This function must guarantee that all PCI read and write operations
380 are serialized. Extra left bits in OrData are stripped.
382 If Address > 0x0FFFFFFF, then ASSERT().
383 If StartBit is greater than 7, then ASSERT().
384 If EndBit is greater than 7, then ASSERT().
385 If EndBit is less than StartBit, then ASSERT().
387 @param Address PCI configuration register to write.
388 @param StartBit The ordinal of the least significant bit in the bit field.
390 @param EndBit The ordinal of the most significant bit in the bit field.
392 @param OrData The value to OR with the PCI configuration register.
394 @return The value written back to the PCI configuration register.
408 BitFieldOr8 (PciRead8 (Address
), StartBit
, EndBit
, OrData
)
413 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
414 AND, and writes the result back to the bit field in the 8-bit register.
416 Reads the 8-bit PCI configuration register specified by Address, performs a
417 bitwise AND between the read result and the value specified by AndData, and
418 writes the result to the 8-bit PCI configuration register specified by
419 Address. The value written to the PCI configuration register is returned.
420 This function must guarantee that all PCI read and write operations are
421 serialized. Extra left bits in AndData are stripped.
423 If Address > 0x0FFFFFFF, then ASSERT().
424 If StartBit is greater than 7, then ASSERT().
425 If EndBit is greater than 7, then ASSERT().
426 If EndBit is less than StartBit, then ASSERT().
428 @param Address PCI configuration register to write.
429 @param StartBit The ordinal of the least significant bit in the bit field.
431 @param EndBit The ordinal of the most significant bit in the bit field.
433 @param AndData The value to AND with the PCI configuration register.
435 @return The value written back to the PCI configuration register.
449 BitFieldAnd8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
)
454 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
455 bitwise inclusive OR, and writes the result back to the bit field in the
458 Reads the 8-bit PCI configuration register specified by Address, performs a
459 bitwise AND followed by a bitwise inclusive OR between the read result and
460 the value specified by AndData, and writes the result to the 8-bit PCI
461 configuration register specified by Address. The value written to the PCI
462 configuration register is returned. This function must guarantee that all PCI
463 read and write operations are serialized. Extra left bits in both AndData and
466 If Address > 0x0FFFFFFF, then ASSERT().
467 If StartBit is greater than 7, then ASSERT().
468 If EndBit is greater than 7, then ASSERT().
469 If EndBit is less than StartBit, then ASSERT().
471 @param Address PCI configuration register to write.
472 @param StartBit The ordinal of the least significant bit in the bit field.
474 @param EndBit The ordinal of the most significant bit in the bit field.
476 @param AndData The value to AND with the PCI configuration register.
477 @param OrData The value to OR with the result of the AND operation.
479 @return The value written back to the PCI configuration register.
484 PciBitFieldAndThenOr8 (
494 BitFieldAndThenOr8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
499 Reads a 16-bit PCI configuration register.
501 Reads and returns the 16-bit PCI configuration register specified by Address.
502 This function must guarantee that all PCI read and write operations are
505 If Address > 0x0FFFFFFF, then ASSERT().
506 If Address is not aligned on a 16-bit boundary, then ASSERT().
508 @param Address Address that encodes the PCI Bus, Device, Function and
511 @return The value read from the PCI configuration register.
520 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
522 return (UINT16
) PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint16
);
526 Writes a 16-bit PCI configuration register.
528 Writes the 16-bit PCI configuration register specified by Address with the
529 value specified by Value. Value is returned. This function must guarantee
530 that all PCI read and write operations are serialized.
532 If Address > 0x0FFFFFFF, then ASSERT().
533 If Address is not aligned on a 16-bit boundary, then ASSERT().
535 @param Address Address that encodes the PCI Bus, Device, Function and
537 @param Data The value to write.
539 @return The value written to the PCI configuration register.
549 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
551 return (UINT16
) PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint16
, Data
);
555 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
558 Reads the 16-bit PCI configuration register specified by Address, performs a
559 bitwise inclusive OR between the read result and the value specified by
560 OrData, and writes the result to the 16-bit PCI configuration register
561 specified by Address. The value written to the PCI configuration register is
562 returned. This function must guarantee that all PCI read and write operations
565 If Address > 0x0FFFFFFF, then ASSERT().
566 If Address is not aligned on a 16-bit boundary, then ASSERT().
568 @param Address Address that encodes the PCI Bus, Device, Function and
570 @param OrData The value to OR with the PCI configuration register.
572 @return The value written back to the PCI configuration register.
582 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) | OrData
));
586 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
589 Reads the 16-bit PCI configuration register specified by Address, performs a
590 bitwise AND between the read result and the value specified by AndData, and
591 writes the result to the 16-bit PCI configuration register specified by
592 Address. The value written to the PCI configuration register is returned.
593 This function must guarantee that all PCI read and write operations are
596 If Address > 0x0FFFFFFF, then ASSERT().
597 If Address is not aligned on a 16-bit boundary, then ASSERT().
599 @param Address Address that encodes the PCI Bus, Device, Function and
601 @param AndData The value to AND with the PCI configuration register.
603 @return The value written back to the PCI configuration register.
613 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) & AndData
));
617 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
618 value, followed a bitwise inclusive OR with another 16-bit value.
620 Reads the 16-bit PCI configuration register specified by Address, performs a
621 bitwise AND between the read result and the value specified by AndData,
622 performs a bitwise inclusive OR between the result of the AND operation and
623 the value specified by OrData, and writes the result to the 16-bit PCI
624 configuration register specified by Address. The value written to the PCI
625 configuration register is returned. This function must guarantee that all PCI
626 read and write operations are serialized.
628 If Address > 0x0FFFFFFF, then ASSERT().
629 If Address is not aligned on a 16-bit boundary, then ASSERT().
631 @param Address Address that encodes the PCI Bus, Device, Function and
633 @param AndData The value to AND with the PCI configuration register.
634 @param OrData The value to OR with the result of the AND operation.
636 @return The value written back to the PCI configuration register.
647 return PciWrite16 (Address
, (UINT16
) ((PciRead16 (Address
) & AndData
) | OrData
));
651 Reads a bit field of a PCI configuration register.
653 Reads the bit field in a 16-bit PCI configuration register. The bit field is
654 specified by the StartBit and the EndBit. The value of the bit field is
657 If Address > 0x0FFFFFFF, then ASSERT().
658 If Address is not aligned on a 16-bit boundary, then ASSERT().
659 If StartBit is greater than 15, then ASSERT().
660 If EndBit is greater than 15, then ASSERT().
661 If EndBit is less than StartBit, then ASSERT().
663 @param Address PCI configuration register to read.
664 @param StartBit The ordinal of the least significant bit in the bit field.
666 @param EndBit The ordinal of the most significant bit in the bit field.
669 @return The value of the bit field read from the PCI configuration register.
680 return BitFieldRead16 (PciRead16 (Address
), StartBit
, EndBit
);
684 Writes a bit field to a PCI configuration register.
686 Writes Value to the bit field of the PCI configuration register. The bit
687 field is specified by the StartBit and the EndBit. All other bits in the
688 destination PCI configuration register are preserved. The new value of the
689 16-bit register is returned.
691 If Address > 0x0FFFFFFF, then ASSERT().
692 If Address is not aligned on a 16-bit boundary, then ASSERT().
693 If StartBit is greater than 15, then ASSERT().
694 If EndBit is greater than 15, then ASSERT().
695 If EndBit is less than StartBit, then ASSERT().
697 @param Address PCI configuration register to write.
698 @param StartBit The ordinal of the least significant bit in the bit field.
700 @param EndBit The ordinal of the most significant bit in the bit field.
702 @param Value New value of the bit field.
704 @return The value written back to the PCI configuration register.
718 BitFieldWrite16 (PciRead16 (Address
), StartBit
, EndBit
, Value
)
723 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
724 writes the result back to the bit field in the 16-bit port.
726 Reads the 16-bit PCI configuration register specified by Address, performs a
727 bitwise inclusive OR between the read result and the value specified by
728 OrData, and writes the result to the 16-bit PCI configuration register
729 specified by Address. The value written to the PCI configuration register is
730 returned. This function must guarantee that all PCI read and write operations
731 are serialized. Extra left bits in OrData are stripped.
733 If Address > 0x0FFFFFFF, then ASSERT().
734 If Address is not aligned on a 16-bit boundary, then ASSERT().
735 If StartBit is greater than 15, then ASSERT().
736 If EndBit is greater than 15, then ASSERT().
737 If EndBit is less than StartBit, then ASSERT().
739 @param Address PCI configuration register to write.
740 @param StartBit The ordinal of the least significant bit in the bit field.
742 @param EndBit The ordinal of the most significant bit in the bit field.
744 @param OrData The value to OR with the PCI configuration register.
746 @return The value written back to the PCI configuration register.
760 BitFieldOr16 (PciRead16 (Address
), StartBit
, EndBit
, OrData
)
765 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
766 AND, and writes the result back to the bit field in the 16-bit register.
768 Reads the 16-bit PCI configuration register specified by Address, performs a
769 bitwise AND between the read result and the value specified by AndData, and
770 writes the result to the 16-bit PCI configuration register specified by
771 Address. The value written to the PCI configuration register is returned.
772 This function must guarantee that all PCI read and write operations are
773 serialized. Extra left bits in AndData are stripped.
775 If Address > 0x0FFFFFFF, then ASSERT().
776 If Address is not aligned on a 16-bit boundary, then ASSERT().
777 If StartBit is greater than 15, then ASSERT().
778 If EndBit is greater than 15, then ASSERT().
779 If EndBit is less than StartBit, then ASSERT().
781 @param Address PCI configuration register to write.
782 @param StartBit The ordinal of the least significant bit in the bit field.
784 @param EndBit The ordinal of the most significant bit in the bit field.
786 @param AndData The value to AND with the PCI configuration register.
788 @return The value written back to the PCI configuration register.
802 BitFieldAnd16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
)
807 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
808 bitwise inclusive OR, and writes the result back to the bit field in the
811 Reads the 16-bit PCI configuration register specified by Address, performs a
812 bitwise AND followed by a bitwise inclusive OR between the read result and
813 the value specified by AndData, and writes the result to the 16-bit PCI
814 configuration register specified by Address. The value written to the PCI
815 configuration register is returned. This function must guarantee that all PCI
816 read and write operations are serialized. Extra left bits in both AndData and
819 If Address > 0x0FFFFFFF, then ASSERT().
820 If Address is not aligned on a 16-bit boundary, then ASSERT().
821 If StartBit is greater than 15, then ASSERT().
822 If EndBit is greater than 15, then ASSERT().
823 If EndBit is less than StartBit, then ASSERT().
825 @param Address PCI configuration register to write.
826 @param StartBit The ordinal of the least significant bit in the bit field.
828 @param EndBit The ordinal of the most significant bit in the bit field.
830 @param AndData The value to AND with the PCI configuration register.
831 @param OrData The value to OR with the result of the AND operation.
833 @return The value written back to the PCI configuration register.
838 PciBitFieldAndThenOr16 (
848 BitFieldAndThenOr16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
853 Reads a 32-bit PCI configuration register.
855 Reads and returns the 32-bit PCI configuration register specified by Address.
856 This function must guarantee that all PCI read and write operations are
859 If Address > 0x0FFFFFFF, then ASSERT().
860 If Address is not aligned on a 32-bit boundary, then ASSERT().
862 @param Address Address that encodes the PCI Bus, Device, Function and
865 @return The value read from the PCI configuration register.
874 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
876 return PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint32
);
880 Writes a 32-bit PCI configuration register.
882 Writes the 32-bit PCI configuration register specified by Address with the
883 value specified by Value. Value is returned. This function must guarantee
884 that all PCI read and write operations are serialized.
886 If Address > 0x0FFFFFFF, then ASSERT().
887 If Address is not aligned on a 32-bit boundary, then ASSERT().
889 @param Address Address that encodes the PCI Bus, Device, Function and
891 @param Data The value to write.
893 @return The value written to the PCI configuration register.
903 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
905 return PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint32
, Data
);
909 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
912 Reads the 32-bit PCI configuration register specified by Address, performs a
913 bitwise inclusive OR between the read result and the value specified by
914 OrData, and writes the result to the 32-bit PCI configuration register
915 specified by Address. The value written to the PCI configuration register is
916 returned. This function must guarantee that all PCI read and write operations
919 If Address > 0x0FFFFFFF, then ASSERT().
920 If Address is not aligned on a 32-bit boundary, then ASSERT().
922 @param Address Address that encodes the PCI Bus, Device, Function and
924 @param OrData The value to OR with the PCI configuration register.
926 @return The value written back to the PCI configuration register.
936 return PciWrite32 (Address
, PciRead32 (Address
) | OrData
);
940 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
943 Reads the 32-bit PCI configuration register specified by Address, performs a
944 bitwise AND between the read result and the value specified by AndData, and
945 writes the result to the 32-bit PCI configuration register specified by
946 Address. The value written to the PCI configuration register is returned.
947 This function must guarantee that all PCI read and write operations are
950 If Address > 0x0FFFFFFF, then ASSERT().
951 If Address is not aligned on a 32-bit boundary, then ASSERT().
953 @param Address Address that encodes the PCI Bus, Device, Function and
955 @param AndData The value to AND with the PCI configuration register.
957 @return The value written back to the PCI configuration register.
967 return PciWrite32 (Address
, PciRead32 (Address
) & AndData
);
971 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
972 value, followed a bitwise inclusive OR with another 32-bit value.
974 Reads the 32-bit PCI configuration register specified by Address, performs a
975 bitwise AND between the read result and the value specified by AndData,
976 performs a bitwise inclusive OR between the result of the AND operation and
977 the value specified by OrData, and writes the result to the 32-bit PCI
978 configuration register specified by Address. The value written to the PCI
979 configuration register is returned. This function must guarantee that all PCI
980 read and write operations are serialized.
982 If Address > 0x0FFFFFFF, then ASSERT().
983 If Address is not aligned on a 32-bit boundary, then ASSERT().
985 @param Address Address that encodes the PCI Bus, Device, Function and
987 @param AndData The value to AND with the PCI configuration register.
988 @param OrData The value to OR with the result of the AND operation.
990 @return The value written back to the PCI configuration register.
1001 return PciWrite32 (Address
, (PciRead32 (Address
) & AndData
) | OrData
);
1005 Reads a bit field of a PCI configuration register.
1007 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1008 specified by the StartBit and the EndBit. The value of the bit field is
1011 If Address > 0x0FFFFFFF, then ASSERT().
1012 If Address is not aligned on a 32-bit boundary, then ASSERT().
1013 If StartBit is greater than 31, then ASSERT().
1014 If EndBit is greater than 31, then ASSERT().
1015 If EndBit is less than StartBit, then ASSERT().
1017 @param Address PCI configuration register to read.
1018 @param StartBit The ordinal of the least significant bit in the bit field.
1020 @param EndBit The ordinal of the most significant bit in the bit field.
1023 @return The value of the bit field read from the PCI configuration register.
1034 return BitFieldRead32 (PciRead32 (Address
), StartBit
, EndBit
);
1038 Writes a bit field to a PCI configuration register.
1040 Writes Value to the bit field of the PCI configuration register. The bit
1041 field is specified by the StartBit and the EndBit. All other bits in the
1042 destination PCI configuration register are preserved. The new value of the
1043 32-bit register is returned.
1045 If Address > 0x0FFFFFFF, then ASSERT().
1046 If Address is not aligned on a 32-bit boundary, then ASSERT().
1047 If StartBit is greater than 31, then ASSERT().
1048 If EndBit is greater than 31, then ASSERT().
1049 If EndBit is less than StartBit, then ASSERT().
1051 @param Address PCI configuration register to write.
1052 @param StartBit The ordinal of the least significant bit in the bit field.
1054 @param EndBit The ordinal of the most significant bit in the bit field.
1056 @param Value New value of the bit field.
1058 @return The value written back to the PCI configuration register.
1063 PciBitFieldWrite32 (
1072 BitFieldWrite32 (PciRead32 (Address
), StartBit
, EndBit
, Value
)
1077 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1078 writes the result back to the bit field in the 32-bit port.
1080 Reads the 32-bit PCI configuration register specified by Address, performs a
1081 bitwise inclusive OR between the read result and the value specified by
1082 OrData, and writes the result to the 32-bit PCI configuration register
1083 specified by Address. The value written to the PCI configuration register is
1084 returned. This function must guarantee that all PCI read and write operations
1085 are serialized. Extra left bits in OrData are stripped.
1087 If Address > 0x0FFFFFFF, then ASSERT().
1088 If Address is not aligned on a 32-bit boundary, then ASSERT().
1089 If StartBit is greater than 31, then ASSERT().
1090 If EndBit is greater than 31, then ASSERT().
1091 If EndBit is less than StartBit, then ASSERT().
1093 @param Address PCI configuration register to write.
1094 @param StartBit The ordinal of the least significant bit in the bit field.
1096 @param EndBit The ordinal of the most significant bit in the bit field.
1098 @param OrData The value to OR with the PCI configuration register.
1100 @return The value written back to the PCI configuration register.
1114 BitFieldOr32 (PciRead32 (Address
), StartBit
, EndBit
, OrData
)
1119 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1120 AND, and writes the result back to the bit field in the 32-bit register.
1122 Reads the 32-bit PCI configuration register specified by Address, performs a
1123 bitwise AND between the read result and the value specified by AndData, and
1124 writes the result to the 32-bit PCI configuration register specified by
1125 Address. The value written to the PCI configuration register is returned.
1126 This function must guarantee that all PCI read and write operations are
1127 serialized. Extra left bits in AndData are stripped.
1129 If Address > 0x0FFFFFFF, then ASSERT().
1130 If Address is not aligned on a 32-bit boundary, then ASSERT().
1131 If StartBit is greater than 31, then ASSERT().
1132 If EndBit is greater than 31, then ASSERT().
1133 If EndBit is less than StartBit, then ASSERT().
1135 @param Address PCI configuration register to write.
1136 @param StartBit The ordinal of the least significant bit in the bit field.
1138 @param EndBit The ordinal of the most significant bit in the bit field.
1140 @param AndData The value to AND with the PCI configuration register.
1142 @return The value written back to the PCI configuration register.
1156 BitFieldAnd32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
)
1161 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1162 bitwise inclusive OR, and writes the result back to the bit field in the
1165 Reads the 32-bit PCI configuration register specified by Address, performs a
1166 bitwise AND followed by a bitwise inclusive OR between the read result and
1167 the value specified by AndData, and writes the result to the 32-bit PCI
1168 configuration register specified by Address. The value written to the PCI
1169 configuration register is returned. This function must guarantee that all PCI
1170 read and write operations are serialized. Extra left bits in both AndData and
1171 OrData are stripped.
1173 If Address > 0x0FFFFFFF, then ASSERT().
1174 If Address is not aligned on a 32-bit boundary, then ASSERT().
1175 If StartBit is greater than 31, then ASSERT().
1176 If EndBit is greater than 31, then ASSERT().
1177 If EndBit is less than StartBit, then ASSERT().
1179 @param Address PCI configuration register to write.
1180 @param StartBit The ordinal of the least significant bit in the bit field.
1182 @param EndBit The ordinal of the most significant bit in the bit field.
1184 @param AndData The value to AND with the PCI configuration register.
1185 @param OrData The value to OR with the result of the AND operation.
1187 @return The value written back to the PCI configuration register.
1192 PciBitFieldAndThenOr32 (
1202 BitFieldAndThenOr32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1207 Reads a range of PCI configuration registers into a caller supplied buffer.
1209 Reads the range of PCI configuration registers specified by StartAddress and
1210 Size into the buffer specified by Buffer. This function only allows the PCI
1211 configuration registers from a single PCI function to be read. Size is
1212 returned. When possible 32-bit PCI configuration read cycles are used to read
1213 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1214 and 16-bit PCI configuration read cycles may be used at the beginning and the
1217 If StartAddress > 0x0FFFFFFF, then ASSERT().
1218 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1219 If Size > 0 and Buffer is NULL, then ASSERT().
1221 @param StartAddress Starting address that encodes the PCI Bus, Device,
1222 Function and Register.
1223 @param Size Size in bytes of the transfer.
1224 @param Buffer Pointer to a buffer receiving the data read.
1232 IN UINTN StartAddress
,
1239 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1240 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1246 ASSERT (Buffer
!= NULL
);
1249 // Save Size for return
1253 if ((StartAddress
& BIT0
) != 0) {
1255 // Read a byte if StartAddress is byte aligned
1257 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1258 StartAddress
+= sizeof (UINT8
);
1259 Size
-= sizeof (UINT8
);
1260 Buffer
= (UINT8
*)Buffer
+ 1;
1263 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1265 // Read a word if StartAddress is word aligned
1267 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1268 StartAddress
+= sizeof (UINT16
);
1269 Size
-= sizeof (UINT16
);
1270 Buffer
= (UINT16
*)Buffer
+ 1;
1273 while (Size
>= sizeof (UINT32
)) {
1275 // Read as many double words as possible
1277 *(volatile UINT32
*)Buffer
= PciRead32 (StartAddress
);
1278 StartAddress
+= sizeof (UINT32
);
1279 Size
-= sizeof (UINT32
);
1280 Buffer
= (UINT32
*)Buffer
+ 1;
1283 if (Size
>= sizeof (UINT16
)) {
1285 // Read the last remaining word if exist
1287 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1288 StartAddress
+= sizeof (UINT16
);
1289 Size
-= sizeof (UINT16
);
1290 Buffer
= (UINT16
*)Buffer
+ 1;
1293 if (Size
>= sizeof (UINT8
)) {
1295 // Read the last remaining byte if exist
1297 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1304 Copies the data in a caller supplied buffer to a specified range of PCI
1305 configuration space.
1307 Writes the range of PCI configuration registers specified by StartAddress and
1308 Size from the buffer specified by Buffer. This function only allows the PCI
1309 configuration registers from a single PCI function to be written. Size is
1310 returned. When possible 32-bit PCI configuration write cycles are used to
1311 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1312 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1313 and the end of the range.
1315 If StartAddress > 0x0FFFFFFF, then ASSERT().
1316 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1317 If Size > 0 and Buffer is NULL, then ASSERT().
1319 @param StartAddress Starting address that encodes the PCI Bus, Device,
1320 Function and Register.
1321 @param Size Size in bytes of the transfer.
1322 @param Buffer Pointer to a buffer containing the data to write.
1330 IN UINTN StartAddress
,
1337 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1338 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1344 ASSERT (Buffer
!= NULL
);
1347 // Save Size for return
1351 if ((StartAddress
& BIT0
) != 0) {
1353 // Write a byte if StartAddress is byte aligned
1355 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1356 StartAddress
+= sizeof (UINT8
);
1357 Size
-= sizeof (UINT8
);
1358 Buffer
= (UINT8
*)Buffer
+ 1;
1361 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1363 // Write a word if StartAddress is word aligned
1365 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1366 StartAddress
+= sizeof (UINT16
);
1367 Size
-= sizeof (UINT16
);
1368 Buffer
= (UINT16
*)Buffer
+ 1;
1371 while (Size
>= sizeof (UINT32
)) {
1373 // Write as many double words as possible
1375 PciWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1376 StartAddress
+= sizeof (UINT32
);
1377 Size
-= sizeof (UINT32
);
1378 Buffer
= (UINT32
*)Buffer
+ 1;
1381 if (Size
>= sizeof (UINT16
)) {
1383 // Write the last remaining word if exist
1385 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1386 StartAddress
+= sizeof (UINT16
);
1387 Size
-= sizeof (UINT16
);
1388 Buffer
= (UINT16
*)Buffer
+ 1;
1391 if (Size
>= sizeof (UINT8
)) {
1393 // Write the last remaining byte if exist
1395 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);