2 PCI Library using PCI CFG2 PPI.
4 Copyright (c) 2007 - 2008, Intel Corporation All rights
5 reserved. This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Ppi/PciCfg2.h>
20 #include <Library/PciLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/PeiServicesTablePointerLib.h>
23 #include <Library/DebugLib.h>
24 #include <Library/PeiServicesLib.h>
27 Assert the validity of a PCI address. A valid PCI address should contain 1's
28 only in the low 28 bits.
30 @param A The address to validate.
31 @param M Additional bits to assert to be zero.
34 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
35 ASSERT (((A) & (~0xfffffff | (M))) == 0)
38 Translate PCI Lib address into format of PCI CFG2 PPI.
40 @param A Address that encodes the PCI Bus, Device, Function and
44 #define PCI_TO_PCICFG2_ADDRESS(A) \
45 (((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | ((UINT64)((A) & 0xFFF) << 32)
48 Internal worker function to read a PCI configuration register.
50 This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.
51 It reads and returns the PCI configuration register specified by Address,
52 the width of data is specified by Width.
54 @param Address Address that encodes the PCI Bus, Device, Function and
56 @param Width Width of data to read
58 @return The value read from the PCI configuration register.
62 PeiPciLibPciCfg2ReadWorker (
64 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
69 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
71 Status
= PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid
, 0, NULL
, (VOID
**) &PciCfg2Ppi
);
72 ASSERT_EFI_ERROR (Status
);
73 ASSERT (PciCfg2Ppi
!= NULL
);
76 GetPeiServicesTablePointer (),
79 PCI_TO_PCICFG2_ADDRESS (Address
),
87 Internal worker function to writes a PCI configuration register.
89 This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.
90 It writes the PCI configuration register specified by Address with the
91 value specified by Data. The width of data is specifed by Width.
94 @param Address Address that encodes the PCI Bus, Device, Function and
96 @param Width Width of data to write
97 @param Data The value to write.
99 @return The value written to the PCI configuration register.
103 PeiPciLibPciCfg2WriteWorker (
105 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
,
110 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
112 Status
= PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid
, 0, NULL
, (VOID
**) &PciCfg2Ppi
);
113 ASSERT_EFI_ERROR (Status
);
114 ASSERT (PciCfg2Ppi
!= NULL
);
117 GetPeiServicesTablePointer (),
120 PCI_TO_PCICFG2_ADDRESS (Address
),
128 Reads an 8-bit PCI configuration register.
130 Reads and returns the 8-bit PCI configuration register specified by Address.
131 This function must guarantee that all PCI read and write operations are
134 If Address > 0x0FFFFFFF, then ASSERT().
136 @param Address Address that encodes the PCI Bus, Device, Function and
139 @return The value read from the PCI configuration register.
148 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
150 return (UINT8
) PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint8
);
154 Writes an 8-bit PCI configuration register.
156 Writes the 8-bit PCI configuration register specified by Address with the
157 value specified by Value. Value is returned. This function must guarantee
158 that all PCI read and write operations are serialized.
160 If Address > 0x0FFFFFFF, then ASSERT().
162 @param Address Address that encodes the PCI Bus, Device, Function and
164 @param Data The value to write.
166 @return The value written to the PCI configuration register.
176 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
178 return (UINT8
) PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint8
, Data
);
182 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
185 Reads the 8-bit PCI configuration register specified by Address, performs a
186 bitwise inclusive OR between the read result and the value specified by
187 OrData, and writes the result to the 8-bit PCI configuration register
188 specified by Address. The value written to the PCI configuration register is
189 returned. This function must guarantee that all PCI read and write operations
192 If Address > 0x0FFFFFFF, then ASSERT().
194 @param Address Address that encodes the PCI Bus, Device, Function and
196 @param OrData The value to OR with the PCI configuration register.
198 @return The value written back to the PCI configuration register.
208 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) | OrData
));
212 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
215 Reads the 8-bit PCI configuration register specified by Address, performs a
216 bitwise AND between the read result and the value specified by AndData, and
217 writes the result to the 8-bit PCI configuration register specified by
218 Address. The value written to the PCI configuration register is returned.
219 This function must guarantee that all PCI read and write operations are
222 If Address > 0x0FFFFFFF, then ASSERT().
224 @param Address Address that encodes the PCI Bus, Device, Function and
226 @param AndData The value to AND with the PCI configuration register.
228 @return The value written back to the PCI configuration register.
238 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) & AndData
));
242 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
243 value, followed a bitwise inclusive OR with another 8-bit value.
245 Reads the 8-bit PCI configuration register specified by Address, performs a
246 bitwise AND between the read result and the value specified by AndData,
247 performs a bitwise inclusive OR between the result of the AND operation and
248 the value specified by OrData, and writes the result to the 8-bit PCI
249 configuration register specified by Address. The value written to the PCI
250 configuration register is returned. This function must guarantee that all PCI
251 read and write operations are serialized.
253 If Address > 0x0FFFFFFF, then ASSERT().
255 @param Address Address that encodes the PCI Bus, Device, Function and
257 @param AndData The value to AND with the PCI configuration register.
258 @param OrData The value to OR with the result of the AND operation.
260 @return The value written back to the PCI configuration register.
271 return PciWrite8 (Address
, (UINT8
) ((PciRead8 (Address
) & AndData
) | OrData
));
275 Reads a bit field of a PCI configuration register.
277 Reads the bit field in an 8-bit PCI configuration register. The bit field is
278 specified by the StartBit and the EndBit. The value of the bit field is
281 If Address > 0x0FFFFFFF, then ASSERT().
282 If StartBit is greater than 7, then ASSERT().
283 If EndBit is greater than 7, then ASSERT().
284 If EndBit is less than StartBit, then ASSERT().
286 @param Address PCI configuration register to read.
287 @param StartBit The ordinal of the least significant bit in the bit field.
289 @param EndBit The ordinal of the most significant bit in the bit field.
292 @return The value of the bit field read from the PCI configuration register.
303 return BitFieldRead8 (PciRead8 (Address
), StartBit
, EndBit
);
307 Writes a bit field to a PCI configuration register.
309 Writes Value to the bit field of the PCI configuration register. The bit
310 field is specified by the StartBit and the EndBit. All other bits in the
311 destination PCI configuration register are preserved. The new value of the
312 8-bit register is returned.
314 If Address > 0x0FFFFFFF, then ASSERT().
315 If StartBit is greater than 7, then ASSERT().
316 If EndBit is greater than 7, then ASSERT().
317 If EndBit is less than StartBit, then ASSERT().
319 @param Address PCI configuration register to write.
320 @param StartBit The ordinal of the least significant bit in the bit field.
322 @param EndBit The ordinal of the most significant bit in the bit field.
324 @param Value New value of the bit field.
326 @return The value written back to the PCI configuration register.
340 BitFieldWrite8 (PciRead8 (Address
), StartBit
, EndBit
, Value
)
345 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
346 writes the result back to the bit field in the 8-bit port.
348 Reads the 8-bit PCI configuration register specified by Address, performs a
349 bitwise inclusive OR between the read result and the value specified by
350 OrData, and writes the result to the 8-bit PCI configuration register
351 specified by Address. The value written to the PCI configuration register is
352 returned. This function must guarantee that all PCI read and write operations
353 are serialized. Extra left bits in OrData are stripped.
355 If Address > 0x0FFFFFFF, then ASSERT().
356 If StartBit is greater than 7, then ASSERT().
357 If EndBit is greater than 7, then ASSERT().
358 If EndBit is less than StartBit, then ASSERT().
360 @param Address PCI configuration register to write.
361 @param StartBit The ordinal of the least significant bit in the bit field.
363 @param EndBit The ordinal of the most significant bit in the bit field.
365 @param OrData The value to OR with the PCI configuration register.
367 @return The value written back to the PCI configuration register.
381 BitFieldOr8 (PciRead8 (Address
), StartBit
, EndBit
, OrData
)
386 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
387 AND, and writes the result back to the bit field in the 8-bit register.
389 Reads the 8-bit PCI configuration register specified by Address, performs a
390 bitwise AND between the read result and the value specified by AndData, and
391 writes the result to the 8-bit PCI configuration register specified by
392 Address. The value written to the PCI configuration register is returned.
393 This function must guarantee that all PCI read and write operations are
394 serialized. Extra left bits in AndData are stripped.
396 If Address > 0x0FFFFFFF, then ASSERT().
397 If StartBit is greater than 7, then ASSERT().
398 If EndBit is greater than 7, then ASSERT().
399 If EndBit is less than StartBit, then ASSERT().
401 @param Address PCI configuration register to write.
402 @param StartBit The ordinal of the least significant bit in the bit field.
404 @param EndBit The ordinal of the most significant bit in the bit field.
406 @param AndData The value to AND with the PCI configuration register.
408 @return The value written back to the PCI configuration register.
422 BitFieldAnd8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
)
427 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
428 bitwise inclusive OR, and writes the result back to the bit field in the
431 Reads the 8-bit PCI configuration register specified by Address, performs a
432 bitwise AND followed by a bitwise inclusive OR between the read result and
433 the value specified by AndData, and writes the result to the 8-bit PCI
434 configuration register specified by Address. The value written to the PCI
435 configuration register is returned. This function must guarantee that all PCI
436 read and write operations are serialized. Extra left bits in both AndData and
439 If Address > 0x0FFFFFFF, then ASSERT().
440 If StartBit is greater than 7, then ASSERT().
441 If EndBit is greater than 7, then ASSERT().
442 If EndBit is less than StartBit, then ASSERT().
444 @param Address PCI configuration register to write.
445 @param StartBit The ordinal of the least significant bit in the bit field.
447 @param EndBit The ordinal of the most significant bit in the bit field.
449 @param AndData The value to AND with the PCI configuration register.
450 @param OrData The value to OR with the result of the AND operation.
452 @return The value written back to the PCI configuration register.
457 PciBitFieldAndThenOr8 (
467 BitFieldAndThenOr8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
472 Reads a 16-bit PCI configuration register.
474 Reads and returns the 16-bit PCI configuration register specified by Address.
475 This function must guarantee that all PCI read and write operations are
478 If Address > 0x0FFFFFFF, then ASSERT().
479 If Address is not aligned on a 16-bit boundary, then ASSERT().
481 @param Address Address that encodes the PCI Bus, Device, Function and
484 @return The value read from the PCI configuration register.
493 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
495 return (UINT16
) PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint16
);
499 Writes a 16-bit PCI configuration register.
501 Writes the 16-bit PCI configuration register specified by Address with the
502 value specified by Value. Value is returned. This function must guarantee
503 that all PCI read and write operations are serialized.
505 If Address > 0x0FFFFFFF, then ASSERT().
506 If Address is not aligned on a 16-bit boundary, then ASSERT().
508 @param Address Address that encodes the PCI Bus, Device, Function and
510 @param Data The value to write.
512 @return The value written to the PCI configuration register.
522 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
524 return (UINT16
) PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint16
, Data
);
528 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
531 Reads the 16-bit PCI configuration register specified by Address, performs a
532 bitwise inclusive OR between the read result and the value specified by
533 OrData, and writes the result to the 16-bit PCI configuration register
534 specified by Address. The value written to the PCI configuration register is
535 returned. This function must guarantee that all PCI read and write operations
538 If Address > 0x0FFFFFFF, then ASSERT().
539 If Address is not aligned on a 16-bit boundary, then ASSERT().
541 @param Address Address that encodes the PCI Bus, Device, Function and
543 @param OrData The value to OR with the PCI configuration register.
545 @return The value written back to the PCI configuration register.
555 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) | OrData
));
559 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
562 Reads the 16-bit PCI configuration register specified by Address, performs a
563 bitwise AND between the read result and the value specified by AndData, and
564 writes the result to the 16-bit PCI configuration register specified by
565 Address. The value written to the PCI configuration register is returned.
566 This function must guarantee that all PCI read and write operations are
569 If Address > 0x0FFFFFFF, then ASSERT().
570 If Address is not aligned on a 16-bit boundary, then ASSERT().
572 @param Address Address that encodes the PCI Bus, Device, Function and
574 @param AndData The value to AND with the PCI configuration register.
576 @return The value written back to the PCI configuration register.
586 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) & AndData
));
590 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
591 value, followed a bitwise inclusive OR with another 16-bit value.
593 Reads the 16-bit PCI configuration register specified by Address, performs a
594 bitwise AND between the read result and the value specified by AndData,
595 performs a bitwise inclusive OR between the result of the AND operation and
596 the value specified by OrData, and writes the result to the 16-bit PCI
597 configuration register specified by Address. The value written to the PCI
598 configuration register is returned. This function must guarantee that all PCI
599 read and write operations are serialized.
601 If Address > 0x0FFFFFFF, then ASSERT().
602 If Address is not aligned on a 16-bit boundary, then ASSERT().
604 @param Address Address that encodes the PCI Bus, Device, Function and
606 @param AndData The value to AND with the PCI configuration register.
607 @param OrData The value to OR with the result of the AND operation.
609 @return The value written back to the PCI configuration register.
620 return PciWrite16 (Address
, (UINT16
) ((PciRead16 (Address
) & AndData
) | OrData
));
624 Reads a bit field of a PCI configuration register.
626 Reads the bit field in a 16-bit PCI configuration register. The bit field is
627 specified by the StartBit and the EndBit. The value of the bit field is
630 If Address > 0x0FFFFFFF, then ASSERT().
631 If Address is not aligned on a 16-bit boundary, then ASSERT().
632 If StartBit is greater than 15, then ASSERT().
633 If EndBit is greater than 15, then ASSERT().
634 If EndBit is less than StartBit, then ASSERT().
636 @param Address PCI configuration register to read.
637 @param StartBit The ordinal of the least significant bit in the bit field.
639 @param EndBit The ordinal of the most significant bit in the bit field.
642 @return The value of the bit field read from the PCI configuration register.
653 return BitFieldRead16 (PciRead16 (Address
), StartBit
, EndBit
);
657 Writes a bit field to a PCI configuration register.
659 Writes Value to the bit field of the PCI configuration register. The bit
660 field is specified by the StartBit and the EndBit. All other bits in the
661 destination PCI configuration register are preserved. The new value of the
662 16-bit register is returned.
664 If Address > 0x0FFFFFFF, then ASSERT().
665 If Address is not aligned on a 16-bit boundary, then ASSERT().
666 If StartBit is greater than 15, then ASSERT().
667 If EndBit is greater than 15, then ASSERT().
668 If EndBit is less than StartBit, then ASSERT().
670 @param Address PCI configuration register to write.
671 @param StartBit The ordinal of the least significant bit in the bit field.
673 @param EndBit The ordinal of the most significant bit in the bit field.
675 @param Value New value of the bit field.
677 @return The value written back to the PCI configuration register.
691 BitFieldWrite16 (PciRead16 (Address
), StartBit
, EndBit
, Value
)
696 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
697 writes the result back to the bit field in the 16-bit port.
699 Reads the 16-bit PCI configuration register specified by Address, performs a
700 bitwise inclusive OR between the read result and the value specified by
701 OrData, and writes the result to the 16-bit PCI configuration register
702 specified by Address. The value written to the PCI configuration register is
703 returned. This function must guarantee that all PCI read and write operations
704 are serialized. Extra left bits in OrData are stripped.
706 If Address > 0x0FFFFFFF, then ASSERT().
707 If Address is not aligned on a 16-bit boundary, then ASSERT().
708 If StartBit is greater than 15, then ASSERT().
709 If EndBit is greater than 15, then ASSERT().
710 If EndBit is less than StartBit, then ASSERT().
712 @param Address PCI configuration register to write.
713 @param StartBit The ordinal of the least significant bit in the bit field.
715 @param EndBit The ordinal of the most significant bit in the bit field.
717 @param OrData The value to OR with the PCI configuration register.
719 @return The value written back to the PCI configuration register.
733 BitFieldOr16 (PciRead16 (Address
), StartBit
, EndBit
, OrData
)
738 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
739 AND, and writes the result back to the bit field in the 16-bit register.
741 Reads the 16-bit PCI configuration register specified by Address, performs a
742 bitwise AND between the read result and the value specified by AndData, and
743 writes the result to the 16-bit PCI configuration register specified by
744 Address. The value written to the PCI configuration register is returned.
745 This function must guarantee that all PCI read and write operations are
746 serialized. Extra left bits in AndData are stripped.
748 If Address > 0x0FFFFFFF, then ASSERT().
749 If Address is not aligned on a 16-bit boundary, then ASSERT().
750 If StartBit is greater than 15, then ASSERT().
751 If EndBit is greater than 15, then ASSERT().
752 If EndBit is less than StartBit, then ASSERT().
754 @param Address PCI configuration register to write.
755 @param StartBit The ordinal of the least significant bit in the bit field.
757 @param EndBit The ordinal of the most significant bit in the bit field.
759 @param AndData The value to AND with the PCI configuration register.
761 @return The value written back to the PCI configuration register.
775 BitFieldAnd16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
)
780 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
781 bitwise inclusive OR, and writes the result back to the bit field in the
784 Reads the 16-bit PCI configuration register specified by Address, performs a
785 bitwise AND followed by a bitwise inclusive OR between the read result and
786 the value specified by AndData, and writes the result to the 16-bit PCI
787 configuration register specified by Address. The value written to the PCI
788 configuration register is returned. This function must guarantee that all PCI
789 read and write operations are serialized. Extra left bits in both AndData and
792 If Address > 0x0FFFFFFF, then ASSERT().
793 If Address is not aligned on a 16-bit boundary, then ASSERT().
794 If StartBit is greater than 15, then ASSERT().
795 If EndBit is greater than 15, then ASSERT().
796 If EndBit is less than StartBit, then ASSERT().
798 @param Address PCI configuration register to write.
799 @param StartBit The ordinal of the least significant bit in the bit field.
801 @param EndBit The ordinal of the most significant bit in the bit field.
803 @param AndData The value to AND with the PCI configuration register.
804 @param OrData The value to OR with the result of the AND operation.
806 @return The value written back to the PCI configuration register.
811 PciBitFieldAndThenOr16 (
821 BitFieldAndThenOr16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
826 Reads a 32-bit PCI configuration register.
828 Reads and returns the 32-bit PCI configuration register specified by Address.
829 This function must guarantee that all PCI read and write operations are
832 If Address > 0x0FFFFFFF, then ASSERT().
833 If Address is not aligned on a 32-bit boundary, then ASSERT().
835 @param Address Address that encodes the PCI Bus, Device, Function and
838 @return The value read from the PCI configuration register.
847 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
849 return PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint32
);
853 Writes a 32-bit PCI configuration register.
855 Writes the 32-bit PCI configuration register specified by Address with the
856 value specified by Value. Value is returned. This function must guarantee
857 that all PCI read and write operations are serialized.
859 If Address > 0x0FFFFFFF, then ASSERT().
860 If Address is not aligned on a 32-bit boundary, then ASSERT().
862 @param Address Address that encodes the PCI Bus, Device, Function and
864 @param Data The value to write.
866 @return The value written to the PCI configuration register.
876 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
878 return PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint32
, Data
);
882 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
885 Reads the 32-bit PCI configuration register specified by Address, performs a
886 bitwise inclusive OR between the read result and the value specified by
887 OrData, and writes the result to the 32-bit PCI configuration register
888 specified by Address. The value written to the PCI configuration register is
889 returned. This function must guarantee that all PCI read and write operations
892 If Address > 0x0FFFFFFF, then ASSERT().
893 If Address is not aligned on a 32-bit boundary, then ASSERT().
895 @param Address Address that encodes the PCI Bus, Device, Function and
897 @param OrData The value to OR with the PCI configuration register.
899 @return The value written back to the PCI configuration register.
909 return PciWrite32 (Address
, PciRead32 (Address
) | OrData
);
913 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
916 Reads the 32-bit PCI configuration register specified by Address, performs a
917 bitwise AND between the read result and the value specified by AndData, and
918 writes the result to the 32-bit PCI configuration register specified by
919 Address. The value written to the PCI configuration register is returned.
920 This function must guarantee that all PCI read and write operations are
923 If Address > 0x0FFFFFFF, then ASSERT().
924 If Address is not aligned on a 32-bit boundary, then ASSERT().
926 @param Address Address that encodes the PCI Bus, Device, Function and
928 @param AndData The value to AND with the PCI configuration register.
930 @return The value written back to the PCI configuration register.
940 return PciWrite32 (Address
, PciRead32 (Address
) & AndData
);
944 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
945 value, followed a bitwise inclusive OR with another 32-bit value.
947 Reads the 32-bit PCI configuration register specified by Address, performs a
948 bitwise AND between the read result and the value specified by AndData,
949 performs a bitwise inclusive OR between the result of the AND operation and
950 the value specified by OrData, and writes the result to the 32-bit PCI
951 configuration register specified by Address. The value written to the PCI
952 configuration register is returned. This function must guarantee that all PCI
953 read and write operations are serialized.
955 If Address > 0x0FFFFFFF, then ASSERT().
956 If Address is not aligned on a 32-bit boundary, then ASSERT().
958 @param Address Address that encodes the PCI Bus, Device, Function and
960 @param AndData The value to AND with the PCI configuration register.
961 @param OrData The value to OR with the result of the AND operation.
963 @return The value written back to the PCI configuration register.
974 return PciWrite32 (Address
, (PciRead32 (Address
) & AndData
) | OrData
);
978 Reads a bit field of a PCI configuration register.
980 Reads the bit field in a 32-bit PCI configuration register. The bit field is
981 specified by the StartBit and the EndBit. The value of the bit field is
984 If Address > 0x0FFFFFFF, then ASSERT().
985 If Address is not aligned on a 32-bit boundary, then ASSERT().
986 If StartBit is greater than 31, then ASSERT().
987 If EndBit is greater than 31, then ASSERT().
988 If EndBit is less than StartBit, then ASSERT().
990 @param Address PCI configuration register to read.
991 @param StartBit The ordinal of the least significant bit in the bit field.
993 @param EndBit The ordinal of the most significant bit in the bit field.
996 @return The value of the bit field read from the PCI configuration register.
1007 return BitFieldRead32 (PciRead32 (Address
), StartBit
, EndBit
);
1011 Writes a bit field to a PCI configuration register.
1013 Writes Value to the bit field of the PCI configuration register. The bit
1014 field is specified by the StartBit and the EndBit. All other bits in the
1015 destination PCI configuration register are preserved. The new value of the
1016 32-bit register is returned.
1018 If Address > 0x0FFFFFFF, then ASSERT().
1019 If Address is not aligned on a 32-bit boundary, then ASSERT().
1020 If StartBit is greater than 31, then ASSERT().
1021 If EndBit is greater than 31, then ASSERT().
1022 If EndBit is less than StartBit, then ASSERT().
1024 @param Address PCI configuration register to write.
1025 @param StartBit The ordinal of the least significant bit in the bit field.
1027 @param EndBit The ordinal of the most significant bit in the bit field.
1029 @param Value New value of the bit field.
1031 @return The value written back to the PCI configuration register.
1036 PciBitFieldWrite32 (
1045 BitFieldWrite32 (PciRead32 (Address
), StartBit
, EndBit
, Value
)
1050 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1051 writes the result back to the bit field in the 32-bit port.
1053 Reads the 32-bit PCI configuration register specified by Address, performs a
1054 bitwise inclusive OR between the read result and the value specified by
1055 OrData, and writes the result to the 32-bit PCI configuration register
1056 specified by Address. The value written to the PCI configuration register is
1057 returned. This function must guarantee that all PCI read and write operations
1058 are serialized. Extra left bits in OrData are stripped.
1060 If Address > 0x0FFFFFFF, then ASSERT().
1061 If Address is not aligned on a 32-bit boundary, then ASSERT().
1062 If StartBit is greater than 31, then ASSERT().
1063 If EndBit is greater than 31, then ASSERT().
1064 If EndBit is less than StartBit, then ASSERT().
1066 @param Address PCI configuration register to write.
1067 @param StartBit The ordinal of the least significant bit in the bit field.
1069 @param EndBit The ordinal of the most significant bit in the bit field.
1071 @param OrData The value to OR with the PCI configuration register.
1073 @return The value written back to the PCI configuration register.
1087 BitFieldOr32 (PciRead32 (Address
), StartBit
, EndBit
, OrData
)
1092 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1093 AND, and writes the result back to the bit field in the 32-bit register.
1095 Reads the 32-bit PCI configuration register specified by Address, performs a
1096 bitwise AND between the read result and the value specified by AndData, and
1097 writes the result to the 32-bit PCI configuration register specified by
1098 Address. The value written to the PCI configuration register is returned.
1099 This function must guarantee that all PCI read and write operations are
1100 serialized. Extra left bits in AndData are stripped.
1102 If Address > 0x0FFFFFFF, then ASSERT().
1103 If Address is not aligned on a 32-bit boundary, then ASSERT().
1104 If StartBit is greater than 31, then ASSERT().
1105 If EndBit is greater than 31, then ASSERT().
1106 If EndBit is less than StartBit, then ASSERT().
1108 @param Address PCI configuration register to write.
1109 @param StartBit The ordinal of the least significant bit in the bit field.
1111 @param EndBit The ordinal of the most significant bit in the bit field.
1113 @param AndData The value to AND with the PCI configuration register.
1115 @return The value written back to the PCI configuration register.
1129 BitFieldAnd32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
)
1134 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1135 bitwise inclusive OR, and writes the result back to the bit field in the
1138 Reads the 32-bit PCI configuration register specified by Address, performs a
1139 bitwise AND followed by a bitwise inclusive OR between the read result and
1140 the value specified by AndData, and writes the result to the 32-bit PCI
1141 configuration register specified by Address. The value written to the PCI
1142 configuration register is returned. This function must guarantee that all PCI
1143 read and write operations are serialized. Extra left bits in both AndData and
1144 OrData are stripped.
1146 If Address > 0x0FFFFFFF, then ASSERT().
1147 If Address is not aligned on a 32-bit boundary, then ASSERT().
1148 If StartBit is greater than 31, then ASSERT().
1149 If EndBit is greater than 31, then ASSERT().
1150 If EndBit is less than StartBit, then ASSERT().
1152 @param Address PCI configuration register to write.
1153 @param StartBit The ordinal of the least significant bit in the bit field.
1155 @param EndBit The ordinal of the most significant bit in the bit field.
1157 @param AndData The value to AND with the PCI configuration register.
1158 @param OrData The value to OR with the result of the AND operation.
1160 @return The value written back to the PCI configuration register.
1165 PciBitFieldAndThenOr32 (
1175 BitFieldAndThenOr32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1180 Reads a range of PCI configuration registers into a caller supplied buffer.
1182 Reads the range of PCI configuration registers specified by StartAddress and
1183 Size into the buffer specified by Buffer. This function only allows the PCI
1184 configuration registers from a single PCI function to be read. Size is
1185 returned. When possible 32-bit PCI configuration read cycles are used to read
1186 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1187 and 16-bit PCI configuration read cycles may be used at the beginning and the
1190 If StartAddress > 0x0FFFFFFF, then ASSERT().
1191 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1192 If Size > 0 and Buffer is NULL, then ASSERT().
1194 @param StartAddress Starting address that encodes the PCI Bus, Device,
1195 Function and Register.
1196 @param Size Size in bytes of the transfer.
1197 @param Buffer Pointer to a buffer receiving the data read.
1205 IN UINTN StartAddress
,
1212 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1213 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x100);
1219 ASSERT (Buffer
!= NULL
);
1222 // Save Size for return
1226 if ((StartAddress
& 1) != 0) {
1228 // Read a byte if StartAddress is byte aligned
1230 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1231 StartAddress
+= sizeof (UINT8
);
1232 Size
-= sizeof (UINT8
);
1233 Buffer
= (UINT8
*)Buffer
+ 1;
1236 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1238 // Read a word if StartAddress is word aligned
1240 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1241 StartAddress
+= sizeof (UINT16
);
1242 Size
-= sizeof (UINT16
);
1243 Buffer
= (UINT16
*)Buffer
+ 1;
1246 while (Size
>= sizeof (UINT32
)) {
1248 // Read as many double words as possible
1250 *(volatile UINT32
*)Buffer
= PciRead32 (StartAddress
);
1251 StartAddress
+= sizeof (UINT32
);
1252 Size
-= sizeof (UINT32
);
1253 Buffer
= (UINT32
*)Buffer
+ 1;
1256 if (Size
>= sizeof (UINT16
)) {
1258 // Read the last remaining word if exist
1260 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1261 StartAddress
+= sizeof (UINT16
);
1262 Size
-= sizeof (UINT16
);
1263 Buffer
= (UINT16
*)Buffer
+ 1;
1266 if (Size
>= sizeof (UINT8
)) {
1268 // Read the last remaining byte if exist
1270 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1277 Copies the data in a caller supplied buffer to a specified range of PCI
1278 configuration space.
1280 Writes the range of PCI configuration registers specified by StartAddress and
1281 Size from the buffer specified by Buffer. This function only allows the PCI
1282 configuration registers from a single PCI function to be written. Size is
1283 returned. When possible 32-bit PCI configuration write cycles are used to
1284 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1285 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1286 and the end of the range.
1288 If StartAddress > 0x0FFFFFFF, then ASSERT().
1289 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1290 If Size > 0 and Buffer is NULL, then ASSERT().
1292 @param StartAddress Starting address that encodes the PCI Bus, Device,
1293 Function and Register.
1294 @param Size Size in bytes of the transfer.
1295 @param Buffer Pointer to a buffer containing the data to write.
1303 IN UINTN StartAddress
,
1310 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1311 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x100);
1317 ASSERT (Buffer
!= NULL
);
1320 // Save Size for return
1324 if ((StartAddress
& 1) != 0) {
1326 // Write a byte if StartAddress is byte aligned
1328 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1329 StartAddress
+= sizeof (UINT8
);
1330 Size
-= sizeof (UINT8
);
1331 Buffer
= (UINT8
*)Buffer
+ 1;
1334 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1336 // Write a word if StartAddress is word aligned
1338 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1339 StartAddress
+= sizeof (UINT16
);
1340 Size
-= sizeof (UINT16
);
1341 Buffer
= (UINT16
*)Buffer
+ 1;
1344 while (Size
>= sizeof (UINT32
)) {
1346 // Write as many double words as possible
1348 PciWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1349 StartAddress
+= sizeof (UINT32
);
1350 Size
-= sizeof (UINT32
);
1351 Buffer
= (UINT32
*)Buffer
+ 1;
1354 if (Size
>= sizeof (UINT16
)) {
1356 // Write the last remaining word if exist
1358 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1359 StartAddress
+= sizeof (UINT16
);
1360 Size
-= sizeof (UINT16
);
1361 Buffer
= (UINT16
*)Buffer
+ 1;
1364 if (Size
>= sizeof (UINT8
)) {
1366 // Write the last remaining byte if exist
1368 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);