2 PCI Library using PCI CFG2 PPI.
4 Copyright (c) 2007 - 2008, Intel Corporation All rights
5 reserved. This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Ppi/PciCfg2.h>
20 #include <Library/PciLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/PeiServicesTablePointerLib.h>
23 #include <Library/DebugLib.h>
24 #include <Library/PeiServicesLib.h>
27 Assert the validity of a PCI address. A valid PCI address should contain 1's
28 only in the low 28 bits.
30 @param A The address to validate.
31 @param M Additional bits to assert to be zero.
34 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
35 ASSERT (((A) & (~0xfffffff | (M))) == 0)
38 Translate PCI Lib address into format of PCI CFG2 PPI.
40 @param A Address that encodes the PCI Bus, Device, Function and
44 #define PCI_TO_PCICFG2_ADDRESS(A) \
45 ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
48 Internal worker function to read a PCI configuration register.
50 This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.
51 It reads and returns the PCI configuration register specified by Address,
52 the width of data is specified by Width.
54 @param Address Address that encodes the PCI Bus, Device, Function and
56 @param Width Width of data to read
58 @return The value read from the PCI configuration register.
62 PeiPciLibPciCfg2ReadWorker (
64 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
69 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
70 UINT64 PciCfg2Address
;
72 Status
= PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid
, 0, NULL
, (VOID
**) &PciCfg2Ppi
);
73 ASSERT_EFI_ERROR (Status
);
74 ASSERT (PciCfg2Ppi
!= NULL
);
76 PciCfg2Address
= PCI_TO_PCICFG2_ADDRESS (Address
);
78 GetPeiServicesTablePointer (),
89 Internal worker function to writes a PCI configuration register.
91 This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.
92 It writes the PCI configuration register specified by Address with the
93 value specified by Data. The width of data is specifed by Width.
96 @param Address Address that encodes the PCI Bus, Device, Function and
98 @param Width Width of data to write
99 @param Data The value to write.
101 @return The value written to the PCI configuration register.
105 PeiPciLibPciCfg2WriteWorker (
107 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
,
112 CONST EFI_PEI_PCI_CFG2_PPI
*PciCfg2Ppi
;
113 UINT64 PciCfg2Address
;
115 Status
= PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid
, 0, NULL
, (VOID
**) &PciCfg2Ppi
);
116 ASSERT_EFI_ERROR (Status
);
117 ASSERT (PciCfg2Ppi
!= NULL
);
119 PciCfg2Address
= PCI_TO_PCICFG2_ADDRESS (Address
);
121 GetPeiServicesTablePointer (),
132 Register a PCI device so PCI configuration registers may be accessed after
133 SetVirtualAddressMap().
135 If Address > 0x0FFFFFFF, then ASSERT().
137 @param Address Address that encodes the PCI Bus, Device, Function and
140 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
141 @retval RETURN_UNSUPPORTED An attempt was made to call this function
142 after ExitBootServices().
143 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
144 at runtime could not be mapped.
145 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
146 complete the registration.
151 PciRegisterForRuntimeAccess (
155 return RETURN_UNSUPPORTED
;
159 Reads an 8-bit PCI configuration register.
161 Reads and returns the 8-bit PCI configuration register specified by Address.
162 This function must guarantee that all PCI read and write operations are
165 If Address > 0x0FFFFFFF, then ASSERT().
167 @param Address Address that encodes the PCI Bus, Device, Function and
170 @return The value read from the PCI configuration register.
179 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
181 return (UINT8
) PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint8
);
185 Writes an 8-bit PCI configuration register.
187 Writes the 8-bit PCI configuration register specified by Address with the
188 value specified by Value. Value is returned. This function must guarantee
189 that all PCI read and write operations are serialized.
191 If Address > 0x0FFFFFFF, then ASSERT().
193 @param Address Address that encodes the PCI Bus, Device, Function and
195 @param Data The value to write.
197 @return The value written to the PCI configuration register.
207 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
209 return (UINT8
) PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint8
, Data
);
213 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
216 Reads the 8-bit PCI configuration register specified by Address, performs a
217 bitwise inclusive OR between the read result and the value specified by
218 OrData, and writes the result to the 8-bit PCI configuration register
219 specified by Address. The value written to the PCI configuration register is
220 returned. This function must guarantee that all PCI read and write operations
223 If Address > 0x0FFFFFFF, then ASSERT().
225 @param Address Address that encodes the PCI Bus, Device, Function and
227 @param OrData The value to OR with the PCI configuration register.
229 @return The value written back to the PCI configuration register.
239 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) | OrData
));
243 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
246 Reads the 8-bit PCI configuration register specified by Address, performs a
247 bitwise AND between the read result and the value specified by AndData, and
248 writes the result to the 8-bit PCI configuration register specified by
249 Address. The value written to the PCI configuration register is returned.
250 This function must guarantee that all PCI read and write operations are
253 If Address > 0x0FFFFFFF, then ASSERT().
255 @param Address Address that encodes the PCI Bus, Device, Function and
257 @param AndData The value to AND with the PCI configuration register.
259 @return The value written back to the PCI configuration register.
269 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) & AndData
));
273 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
274 value, followed a bitwise inclusive OR with another 8-bit value.
276 Reads the 8-bit PCI configuration register specified by Address, performs a
277 bitwise AND between the read result and the value specified by AndData,
278 performs a bitwise inclusive OR between the result of the AND operation and
279 the value specified by OrData, and writes the result to the 8-bit PCI
280 configuration register specified by Address. The value written to the PCI
281 configuration register is returned. This function must guarantee that all PCI
282 read and write operations are serialized.
284 If Address > 0x0FFFFFFF, then ASSERT().
286 @param Address Address that encodes the PCI Bus, Device, Function and
288 @param AndData The value to AND with the PCI configuration register.
289 @param OrData The value to OR with the result of the AND operation.
291 @return The value written back to the PCI configuration register.
302 return PciWrite8 (Address
, (UINT8
) ((PciRead8 (Address
) & AndData
) | OrData
));
306 Reads a bit field of a PCI configuration register.
308 Reads the bit field in an 8-bit PCI configuration register. The bit field is
309 specified by the StartBit and the EndBit. The value of the bit field is
312 If Address > 0x0FFFFFFF, then ASSERT().
313 If StartBit is greater than 7, then ASSERT().
314 If EndBit is greater than 7, then ASSERT().
315 If EndBit is less than StartBit, then ASSERT().
317 @param Address PCI configuration register to read.
318 @param StartBit The ordinal of the least significant bit in the bit field.
320 @param EndBit The ordinal of the most significant bit in the bit field.
323 @return The value of the bit field read from the PCI configuration register.
334 return BitFieldRead8 (PciRead8 (Address
), StartBit
, EndBit
);
338 Writes a bit field to a PCI configuration register.
340 Writes Value to the bit field of the PCI configuration register. The bit
341 field is specified by the StartBit and the EndBit. All other bits in the
342 destination PCI configuration register are preserved. The new value of the
343 8-bit register is returned.
345 If Address > 0x0FFFFFFF, then ASSERT().
346 If StartBit is greater than 7, then ASSERT().
347 If EndBit is greater than 7, then ASSERT().
348 If EndBit is less than StartBit, then ASSERT().
350 @param Address PCI configuration register to write.
351 @param StartBit The ordinal of the least significant bit in the bit field.
353 @param EndBit The ordinal of the most significant bit in the bit field.
355 @param Value New value of the bit field.
357 @return The value written back to the PCI configuration register.
371 BitFieldWrite8 (PciRead8 (Address
), StartBit
, EndBit
, Value
)
376 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
377 writes the result back to the bit field in the 8-bit port.
379 Reads the 8-bit PCI configuration register specified by Address, performs a
380 bitwise inclusive OR between the read result and the value specified by
381 OrData, and writes the result to the 8-bit PCI configuration register
382 specified by Address. The value written to the PCI configuration register is
383 returned. This function must guarantee that all PCI read and write operations
384 are serialized. Extra left bits in OrData are stripped.
386 If Address > 0x0FFFFFFF, then ASSERT().
387 If StartBit is greater than 7, then ASSERT().
388 If EndBit is greater than 7, then ASSERT().
389 If EndBit is less than StartBit, then ASSERT().
391 @param Address PCI configuration register to write.
392 @param StartBit The ordinal of the least significant bit in the bit field.
394 @param EndBit The ordinal of the most significant bit in the bit field.
396 @param OrData The value to OR with the PCI configuration register.
398 @return The value written back to the PCI configuration register.
412 BitFieldOr8 (PciRead8 (Address
), StartBit
, EndBit
, OrData
)
417 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
418 AND, and writes the result back to the bit field in the 8-bit register.
420 Reads the 8-bit PCI configuration register specified by Address, performs a
421 bitwise AND between the read result and the value specified by AndData, and
422 writes the result to the 8-bit PCI configuration register specified by
423 Address. The value written to the PCI configuration register is returned.
424 This function must guarantee that all PCI read and write operations are
425 serialized. Extra left bits in AndData are stripped.
427 If Address > 0x0FFFFFFF, then ASSERT().
428 If StartBit is greater than 7, then ASSERT().
429 If EndBit is greater than 7, then ASSERT().
430 If EndBit is less than StartBit, then ASSERT().
432 @param Address PCI configuration register to write.
433 @param StartBit The ordinal of the least significant bit in the bit field.
435 @param EndBit The ordinal of the most significant bit in the bit field.
437 @param AndData The value to AND with the PCI configuration register.
439 @return The value written back to the PCI configuration register.
453 BitFieldAnd8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
)
458 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
459 bitwise inclusive OR, and writes the result back to the bit field in the
462 Reads the 8-bit PCI configuration register specified by Address, performs a
463 bitwise AND followed by a bitwise inclusive OR between the read result and
464 the value specified by AndData, and writes the result to the 8-bit PCI
465 configuration register specified by Address. The value written to the PCI
466 configuration register is returned. This function must guarantee that all PCI
467 read and write operations are serialized. Extra left bits in both AndData and
470 If Address > 0x0FFFFFFF, then ASSERT().
471 If StartBit is greater than 7, then ASSERT().
472 If EndBit is greater than 7, then ASSERT().
473 If EndBit is less than StartBit, then ASSERT().
475 @param Address PCI configuration register to write.
476 @param StartBit The ordinal of the least significant bit in the bit field.
478 @param EndBit The ordinal of the most significant bit in the bit field.
480 @param AndData The value to AND with the PCI configuration register.
481 @param OrData The value to OR with the result of the AND operation.
483 @return The value written back to the PCI configuration register.
488 PciBitFieldAndThenOr8 (
498 BitFieldAndThenOr8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
503 Reads a 16-bit PCI configuration register.
505 Reads and returns the 16-bit PCI configuration register specified by Address.
506 This function must guarantee that all PCI read and write operations are
509 If Address > 0x0FFFFFFF, then ASSERT().
510 If Address is not aligned on a 16-bit boundary, then ASSERT().
512 @param Address Address that encodes the PCI Bus, Device, Function and
515 @return The value read from the PCI configuration register.
524 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
526 return (UINT16
) PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint16
);
530 Writes a 16-bit PCI configuration register.
532 Writes the 16-bit PCI configuration register specified by Address with the
533 value specified by Value. Value is returned. This function must guarantee
534 that all PCI read and write operations are serialized.
536 If Address > 0x0FFFFFFF, then ASSERT().
537 If Address is not aligned on a 16-bit boundary, then ASSERT().
539 @param Address Address that encodes the PCI Bus, Device, Function and
541 @param Data The value to write.
543 @return The value written to the PCI configuration register.
553 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
555 return (UINT16
) PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint16
, Data
);
559 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
562 Reads the 16-bit PCI configuration register specified by Address, performs a
563 bitwise inclusive OR between the read result and the value specified by
564 OrData, and writes the result to the 16-bit PCI configuration register
565 specified by Address. The value written to the PCI configuration register is
566 returned. This function must guarantee that all PCI read and write operations
569 If Address > 0x0FFFFFFF, then ASSERT().
570 If Address is not aligned on a 16-bit boundary, then ASSERT().
572 @param Address Address that encodes the PCI Bus, Device, Function and
574 @param OrData The value to OR with the PCI configuration register.
576 @return The value written back to the PCI configuration register.
586 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) | OrData
));
590 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
593 Reads the 16-bit PCI configuration register specified by Address, performs a
594 bitwise AND between the read result and the value specified by AndData, and
595 writes the result to the 16-bit PCI configuration register specified by
596 Address. The value written to the PCI configuration register is returned.
597 This function must guarantee that all PCI read and write operations are
600 If Address > 0x0FFFFFFF, then ASSERT().
601 If Address is not aligned on a 16-bit boundary, then ASSERT().
603 @param Address Address that encodes the PCI Bus, Device, Function and
605 @param AndData The value to AND with the PCI configuration register.
607 @return The value written back to the PCI configuration register.
617 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) & AndData
));
621 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
622 value, followed a bitwise inclusive OR with another 16-bit value.
624 Reads the 16-bit PCI configuration register specified by Address, performs a
625 bitwise AND between the read result and the value specified by AndData,
626 performs a bitwise inclusive OR between the result of the AND operation and
627 the value specified by OrData, and writes the result to the 16-bit PCI
628 configuration register specified by Address. The value written to the PCI
629 configuration register is returned. This function must guarantee that all PCI
630 read and write operations are serialized.
632 If Address > 0x0FFFFFFF, then ASSERT().
633 If Address is not aligned on a 16-bit boundary, then ASSERT().
635 @param Address Address that encodes the PCI Bus, Device, Function and
637 @param AndData The value to AND with the PCI configuration register.
638 @param OrData The value to OR with the result of the AND operation.
640 @return The value written back to the PCI configuration register.
651 return PciWrite16 (Address
, (UINT16
) ((PciRead16 (Address
) & AndData
) | OrData
));
655 Reads a bit field of a PCI configuration register.
657 Reads the bit field in a 16-bit PCI configuration register. The bit field is
658 specified by the StartBit and the EndBit. The value of the bit field is
661 If Address > 0x0FFFFFFF, then ASSERT().
662 If Address is not aligned on a 16-bit boundary, then ASSERT().
663 If StartBit is greater than 15, then ASSERT().
664 If EndBit is greater than 15, then ASSERT().
665 If EndBit is less than StartBit, then ASSERT().
667 @param Address PCI configuration register to read.
668 @param StartBit The ordinal of the least significant bit in the bit field.
670 @param EndBit The ordinal of the most significant bit in the bit field.
673 @return The value of the bit field read from the PCI configuration register.
684 return BitFieldRead16 (PciRead16 (Address
), StartBit
, EndBit
);
688 Writes a bit field to a PCI configuration register.
690 Writes Value to the bit field of the PCI configuration register. The bit
691 field is specified by the StartBit and the EndBit. All other bits in the
692 destination PCI configuration register are preserved. The new value of the
693 16-bit register is returned.
695 If Address > 0x0FFFFFFF, then ASSERT().
696 If Address is not aligned on a 16-bit boundary, then ASSERT().
697 If StartBit is greater than 15, then ASSERT().
698 If EndBit is greater than 15, then ASSERT().
699 If EndBit is less than StartBit, then ASSERT().
701 @param Address PCI configuration register to write.
702 @param StartBit The ordinal of the least significant bit in the bit field.
704 @param EndBit The ordinal of the most significant bit in the bit field.
706 @param Value New value of the bit field.
708 @return The value written back to the PCI configuration register.
722 BitFieldWrite16 (PciRead16 (Address
), StartBit
, EndBit
, Value
)
727 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
728 writes the result back to the bit field in the 16-bit port.
730 Reads the 16-bit PCI configuration register specified by Address, performs a
731 bitwise inclusive OR between the read result and the value specified by
732 OrData, and writes the result to the 16-bit PCI configuration register
733 specified by Address. The value written to the PCI configuration register is
734 returned. This function must guarantee that all PCI read and write operations
735 are serialized. Extra left bits in OrData are stripped.
737 If Address > 0x0FFFFFFF, then ASSERT().
738 If Address is not aligned on a 16-bit boundary, then ASSERT().
739 If StartBit is greater than 15, then ASSERT().
740 If EndBit is greater than 15, then ASSERT().
741 If EndBit is less than StartBit, then ASSERT().
743 @param Address PCI configuration register to write.
744 @param StartBit The ordinal of the least significant bit in the bit field.
746 @param EndBit The ordinal of the most significant bit in the bit field.
748 @param OrData The value to OR with the PCI configuration register.
750 @return The value written back to the PCI configuration register.
764 BitFieldOr16 (PciRead16 (Address
), StartBit
, EndBit
, OrData
)
769 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
770 AND, and writes the result back to the bit field in the 16-bit register.
772 Reads the 16-bit PCI configuration register specified by Address, performs a
773 bitwise AND between the read result and the value specified by AndData, and
774 writes the result to the 16-bit PCI configuration register specified by
775 Address. The value written to the PCI configuration register is returned.
776 This function must guarantee that all PCI read and write operations are
777 serialized. Extra left bits in AndData are stripped.
779 If Address > 0x0FFFFFFF, then ASSERT().
780 If Address is not aligned on a 16-bit boundary, then ASSERT().
781 If StartBit is greater than 15, then ASSERT().
782 If EndBit is greater than 15, then ASSERT().
783 If EndBit is less than StartBit, then ASSERT().
785 @param Address PCI configuration register to write.
786 @param StartBit The ordinal of the least significant bit in the bit field.
788 @param EndBit The ordinal of the most significant bit in the bit field.
790 @param AndData The value to AND with the PCI configuration register.
792 @return The value written back to the PCI configuration register.
806 BitFieldAnd16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
)
811 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
812 bitwise inclusive OR, and writes the result back to the bit field in the
815 Reads the 16-bit PCI configuration register specified by Address, performs a
816 bitwise AND followed by a bitwise inclusive OR between the read result and
817 the value specified by AndData, and writes the result to the 16-bit PCI
818 configuration register specified by Address. The value written to the PCI
819 configuration register is returned. This function must guarantee that all PCI
820 read and write operations are serialized. Extra left bits in both AndData and
823 If Address > 0x0FFFFFFF, then ASSERT().
824 If Address is not aligned on a 16-bit boundary, then ASSERT().
825 If StartBit is greater than 15, then ASSERT().
826 If EndBit is greater than 15, then ASSERT().
827 If EndBit is less than StartBit, then ASSERT().
829 @param Address PCI configuration register to write.
830 @param StartBit The ordinal of the least significant bit in the bit field.
832 @param EndBit The ordinal of the most significant bit in the bit field.
834 @param AndData The value to AND with the PCI configuration register.
835 @param OrData The value to OR with the result of the AND operation.
837 @return The value written back to the PCI configuration register.
842 PciBitFieldAndThenOr16 (
852 BitFieldAndThenOr16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
857 Reads a 32-bit PCI configuration register.
859 Reads and returns the 32-bit PCI configuration register specified by Address.
860 This function must guarantee that all PCI read and write operations are
863 If Address > 0x0FFFFFFF, then ASSERT().
864 If Address is not aligned on a 32-bit boundary, then ASSERT().
866 @param Address Address that encodes the PCI Bus, Device, Function and
869 @return The value read from the PCI configuration register.
878 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
880 return PeiPciLibPciCfg2ReadWorker (Address
, EfiPeiPciCfgWidthUint32
);
884 Writes a 32-bit PCI configuration register.
886 Writes the 32-bit PCI configuration register specified by Address with the
887 value specified by Value. Value is returned. This function must guarantee
888 that all PCI read and write operations are serialized.
890 If Address > 0x0FFFFFFF, then ASSERT().
891 If Address is not aligned on a 32-bit boundary, then ASSERT().
893 @param Address Address that encodes the PCI Bus, Device, Function and
895 @param Data The value to write.
897 @return The value written to the PCI configuration register.
907 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
909 return PeiPciLibPciCfg2WriteWorker (Address
, EfiPeiPciCfgWidthUint32
, Data
);
913 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
916 Reads the 32-bit PCI configuration register specified by Address, performs a
917 bitwise inclusive OR between the read result and the value specified by
918 OrData, and writes the result to the 32-bit PCI configuration register
919 specified by Address. The value written to the PCI configuration register is
920 returned. This function must guarantee that all PCI read and write operations
923 If Address > 0x0FFFFFFF, then ASSERT().
924 If Address is not aligned on a 32-bit boundary, then ASSERT().
926 @param Address Address that encodes the PCI Bus, Device, Function and
928 @param OrData The value to OR with the PCI configuration register.
930 @return The value written back to the PCI configuration register.
940 return PciWrite32 (Address
, PciRead32 (Address
) | OrData
);
944 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
947 Reads the 32-bit PCI configuration register specified by Address, performs a
948 bitwise AND between the read result and the value specified by AndData, and
949 writes the result to the 32-bit PCI configuration register specified by
950 Address. The value written to the PCI configuration register is returned.
951 This function must guarantee that all PCI read and write operations are
954 If Address > 0x0FFFFFFF, then ASSERT().
955 If Address is not aligned on a 32-bit boundary, then ASSERT().
957 @param Address Address that encodes the PCI Bus, Device, Function and
959 @param AndData The value to AND with the PCI configuration register.
961 @return The value written back to the PCI configuration register.
971 return PciWrite32 (Address
, PciRead32 (Address
) & AndData
);
975 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
976 value, followed a bitwise inclusive OR with another 32-bit value.
978 Reads the 32-bit PCI configuration register specified by Address, performs a
979 bitwise AND between the read result and the value specified by AndData,
980 performs a bitwise inclusive OR between the result of the AND operation and
981 the value specified by OrData, and writes the result to the 32-bit PCI
982 configuration register specified by Address. The value written to the PCI
983 configuration register is returned. This function must guarantee that all PCI
984 read and write operations are serialized.
986 If Address > 0x0FFFFFFF, then ASSERT().
987 If Address is not aligned on a 32-bit boundary, then ASSERT().
989 @param Address Address that encodes the PCI Bus, Device, Function and
991 @param AndData The value to AND with the PCI configuration register.
992 @param OrData The value to OR with the result of the AND operation.
994 @return The value written back to the PCI configuration register.
1005 return PciWrite32 (Address
, (PciRead32 (Address
) & AndData
) | OrData
);
1009 Reads a bit field of a PCI configuration register.
1011 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1012 specified by the StartBit and the EndBit. The value of the bit field is
1015 If Address > 0x0FFFFFFF, then ASSERT().
1016 If Address is not aligned on a 32-bit boundary, then ASSERT().
1017 If StartBit is greater than 31, then ASSERT().
1018 If EndBit is greater than 31, then ASSERT().
1019 If EndBit is less than StartBit, then ASSERT().
1021 @param Address PCI configuration register to read.
1022 @param StartBit The ordinal of the least significant bit in the bit field.
1024 @param EndBit The ordinal of the most significant bit in the bit field.
1027 @return The value of the bit field read from the PCI configuration register.
1038 return BitFieldRead32 (PciRead32 (Address
), StartBit
, EndBit
);
1042 Writes a bit field to a PCI configuration register.
1044 Writes Value to the bit field of the PCI configuration register. The bit
1045 field is specified by the StartBit and the EndBit. All other bits in the
1046 destination PCI configuration register are preserved. The new value of the
1047 32-bit register is returned.
1049 If Address > 0x0FFFFFFF, then ASSERT().
1050 If Address is not aligned on a 32-bit boundary, then ASSERT().
1051 If StartBit is greater than 31, then ASSERT().
1052 If EndBit is greater than 31, then ASSERT().
1053 If EndBit is less than StartBit, then ASSERT().
1055 @param Address PCI configuration register to write.
1056 @param StartBit The ordinal of the least significant bit in the bit field.
1058 @param EndBit The ordinal of the most significant bit in the bit field.
1060 @param Value New value of the bit field.
1062 @return The value written back to the PCI configuration register.
1067 PciBitFieldWrite32 (
1076 BitFieldWrite32 (PciRead32 (Address
), StartBit
, EndBit
, Value
)
1081 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1082 writes the result back to the bit field in the 32-bit port.
1084 Reads the 32-bit PCI configuration register specified by Address, performs a
1085 bitwise inclusive OR between the read result and the value specified by
1086 OrData, and writes the result to the 32-bit PCI configuration register
1087 specified by Address. The value written to the PCI configuration register is
1088 returned. This function must guarantee that all PCI read and write operations
1089 are serialized. Extra left bits in OrData are stripped.
1091 If Address > 0x0FFFFFFF, then ASSERT().
1092 If Address is not aligned on a 32-bit boundary, then ASSERT().
1093 If StartBit is greater than 31, then ASSERT().
1094 If EndBit is greater than 31, then ASSERT().
1095 If EndBit is less than StartBit, then ASSERT().
1097 @param Address PCI configuration register to write.
1098 @param StartBit The ordinal of the least significant bit in the bit field.
1100 @param EndBit The ordinal of the most significant bit in the bit field.
1102 @param OrData The value to OR with the PCI configuration register.
1104 @return The value written back to the PCI configuration register.
1118 BitFieldOr32 (PciRead32 (Address
), StartBit
, EndBit
, OrData
)
1123 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1124 AND, and writes the result back to the bit field in the 32-bit register.
1126 Reads the 32-bit PCI configuration register specified by Address, performs a
1127 bitwise AND between the read result and the value specified by AndData, and
1128 writes the result to the 32-bit PCI configuration register specified by
1129 Address. The value written to the PCI configuration register is returned.
1130 This function must guarantee that all PCI read and write operations are
1131 serialized. Extra left bits in AndData are stripped.
1133 If Address > 0x0FFFFFFF, then ASSERT().
1134 If Address is not aligned on a 32-bit boundary, then ASSERT().
1135 If StartBit is greater than 31, then ASSERT().
1136 If EndBit is greater than 31, then ASSERT().
1137 If EndBit is less than StartBit, then ASSERT().
1139 @param Address PCI configuration register to write.
1140 @param StartBit The ordinal of the least significant bit in the bit field.
1142 @param EndBit The ordinal of the most significant bit in the bit field.
1144 @param AndData The value to AND with the PCI configuration register.
1146 @return The value written back to the PCI configuration register.
1160 BitFieldAnd32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
)
1165 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1166 bitwise inclusive OR, and writes the result back to the bit field in the
1169 Reads the 32-bit PCI configuration register specified by Address, performs a
1170 bitwise AND followed by a bitwise inclusive OR between the read result and
1171 the value specified by AndData, and writes the result to the 32-bit PCI
1172 configuration register specified by Address. The value written to the PCI
1173 configuration register is returned. This function must guarantee that all PCI
1174 read and write operations are serialized. Extra left bits in both AndData and
1175 OrData are stripped.
1177 If Address > 0x0FFFFFFF, then ASSERT().
1178 If Address is not aligned on a 32-bit boundary, then ASSERT().
1179 If StartBit is greater than 31, then ASSERT().
1180 If EndBit is greater than 31, then ASSERT().
1181 If EndBit is less than StartBit, then ASSERT().
1183 @param Address PCI configuration register to write.
1184 @param StartBit The ordinal of the least significant bit in the bit field.
1186 @param EndBit The ordinal of the most significant bit in the bit field.
1188 @param AndData The value to AND with the PCI configuration register.
1189 @param OrData The value to OR with the result of the AND operation.
1191 @return The value written back to the PCI configuration register.
1196 PciBitFieldAndThenOr32 (
1206 BitFieldAndThenOr32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1211 Reads a range of PCI configuration registers into a caller supplied buffer.
1213 Reads the range of PCI configuration registers specified by StartAddress and
1214 Size into the buffer specified by Buffer. This function only allows the PCI
1215 configuration registers from a single PCI function to be read. Size is
1216 returned. When possible 32-bit PCI configuration read cycles are used to read
1217 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1218 and 16-bit PCI configuration read cycles may be used at the beginning and the
1221 If StartAddress > 0x0FFFFFFF, then ASSERT().
1222 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1223 If Size > 0 and Buffer is NULL, then ASSERT().
1225 @param StartAddress Starting address that encodes the PCI Bus, Device,
1226 Function and Register.
1227 @param Size Size in bytes of the transfer.
1228 @param Buffer Pointer to a buffer receiving the data read.
1236 IN UINTN StartAddress
,
1243 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1244 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1250 ASSERT (Buffer
!= NULL
);
1253 // Save Size for return
1257 if ((StartAddress
& BIT0
) != 0) {
1259 // Read a byte if StartAddress is byte aligned
1261 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1262 StartAddress
+= sizeof (UINT8
);
1263 Size
-= sizeof (UINT8
);
1264 Buffer
= (UINT8
*)Buffer
+ 1;
1267 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1269 // Read a word if StartAddress is word aligned
1271 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1272 StartAddress
+= sizeof (UINT16
);
1273 Size
-= sizeof (UINT16
);
1274 Buffer
= (UINT16
*)Buffer
+ 1;
1277 while (Size
>= sizeof (UINT32
)) {
1279 // Read as many double words as possible
1281 *(volatile UINT32
*)Buffer
= PciRead32 (StartAddress
);
1282 StartAddress
+= sizeof (UINT32
);
1283 Size
-= sizeof (UINT32
);
1284 Buffer
= (UINT32
*)Buffer
+ 1;
1287 if (Size
>= sizeof (UINT16
)) {
1289 // Read the last remaining word if exist
1291 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1292 StartAddress
+= sizeof (UINT16
);
1293 Size
-= sizeof (UINT16
);
1294 Buffer
= (UINT16
*)Buffer
+ 1;
1297 if (Size
>= sizeof (UINT8
)) {
1299 // Read the last remaining byte if exist
1301 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1308 Copies the data in a caller supplied buffer to a specified range of PCI
1309 configuration space.
1311 Writes the range of PCI configuration registers specified by StartAddress and
1312 Size from the buffer specified by Buffer. This function only allows the PCI
1313 configuration registers from a single PCI function to be written. Size is
1314 returned. When possible 32-bit PCI configuration write cycles are used to
1315 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1316 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1317 and the end of the range.
1319 If StartAddress > 0x0FFFFFFF, then ASSERT().
1320 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1321 If Size > 0 and Buffer is NULL, then ASSERT().
1323 @param StartAddress Starting address that encodes the PCI Bus, Device,
1324 Function and Register.
1325 @param Size Size in bytes of the transfer.
1326 @param Buffer Pointer to a buffer containing the data to write.
1334 IN UINTN StartAddress
,
1341 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1342 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1348 ASSERT (Buffer
!= NULL
);
1351 // Save Size for return
1355 if ((StartAddress
& BIT0
) != 0) {
1357 // Write a byte if StartAddress is byte aligned
1359 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1360 StartAddress
+= sizeof (UINT8
);
1361 Size
-= sizeof (UINT8
);
1362 Buffer
= (UINT8
*)Buffer
+ 1;
1365 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1367 // Write a word if StartAddress is word aligned
1369 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1370 StartAddress
+= sizeof (UINT16
);
1371 Size
-= sizeof (UINT16
);
1372 Buffer
= (UINT16
*)Buffer
+ 1;
1375 while (Size
>= sizeof (UINT32
)) {
1377 // Write as many double words as possible
1379 PciWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1380 StartAddress
+= sizeof (UINT32
);
1381 Size
-= sizeof (UINT32
);
1382 Buffer
= (UINT32
*)Buffer
+ 1;
1385 if (Size
>= sizeof (UINT16
)) {
1387 // Write the last remaining word if exist
1389 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1390 StartAddress
+= sizeof (UINT16
);
1391 Size
-= sizeof (UINT16
);
1392 Buffer
= (UINT16
*)Buffer
+ 1;
1395 if (Size
>= sizeof (UINT8
)) {
1397 // Write the last remaining byte if exist
1399 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);