2 PCI Library using PCI Root Bridge I/O Protocol.
4 Copyright (c) 2007 - 2008, Intel Corporation All rights
5 reserved. This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Protocol/PciRootBridgeIo.h>
20 #include <Library/PciLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/UefiBootServicesTableLib.h>
23 #include <Library/DebugLib.h>
26 Assert the validity of a PCI address. A valid PCI address should contain 1's
27 only in the low 28 bits.
29 @param A The address to validate.
30 @param M Additional bits to assert to be zero.
33 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
34 ASSERT (((A) & (~0xfffffff | (M))) == 0)
37 Translate PCI Lib address into format of PCI Root Bridge I/O Protocol.
39 @param A Address that encodes the PCI Bus, Device, Function and
43 #define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \
44 ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
47 // Global varible to cache pointer to PCI Root Bridge I/O protocol.
49 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*mPciRootBridgeIo
= NULL
;
52 The constructor function caches the pointer to PCI Root Bridge I/O protocol.
54 The constructor function locates PCI Root Bridge I/O protocol from protocol database.
55 It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.
57 @param ImageHandle The firmware allocated handle for the EFI image.
58 @param SystemTable A pointer to the EFI System Table.
60 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
66 IN EFI_HANDLE ImageHandle
,
67 IN EFI_SYSTEM_TABLE
*SystemTable
72 Status
= gBS
->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid
, NULL
, (VOID
**) &mPciRootBridgeIo
);
73 ASSERT_EFI_ERROR (Status
);
74 ASSERT (mPciRootBridgeIo
!= NULL
);
80 Internal worker function to read a PCI configuration register.
82 This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() service.
83 It reads and returns the PCI configuration register specified by Address,
84 the width of data is specified by Width.
86 @param Address Address that encodes the PCI Bus, Device, Function and
88 @param Width Width of data to read
90 @return The value read from the PCI configuration register.
94 DxePciLibPciRootBridgeIoReadWorker (
96 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
101 mPciRootBridgeIo
->Pci
.Read (
104 PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address
),
113 Internal worker function to writes a PCI configuration register.
115 This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.
116 It writes the PCI configuration register specified by Address with the
117 value specified by Data. The width of data is specifed by Width.
120 @param Address Address that encodes the PCI Bus, Device, Function and
122 @param Width Width of data to write
123 @param Data The value to write.
125 @return The value written to the PCI configuration register.
129 DxePciLibPciRootBridgeIoWriteWorker (
131 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
135 mPciRootBridgeIo
->Pci
.Write (
138 PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address
),
146 Register a PCI device so PCI configuration registers may be accessed after
147 SetVirtualAddressMap().
149 If Address > 0x0FFFFFFF, then ASSERT().
151 @param Address Address that encodes the PCI Bus, Device, Function and
154 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
155 @retval RETURN_UNSUPPORTED An attempt was made to call this function
156 after ExitBootServices().
157 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
158 at runtime could not be mapped.
159 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
160 complete the registration.
165 PciRegisterForRuntimeAccess (
169 return RETURN_UNSUPPORTED
;
173 Reads an 8-bit PCI configuration register.
175 Reads and returns the 8-bit PCI configuration register specified by Address.
176 This function must guarantee that all PCI read and write operations are
179 If Address > 0x0FFFFFFF, then ASSERT().
181 @param Address Address that encodes the PCI Bus, Device, Function and
184 @return The value read from the PCI configuration register.
193 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
195 return (UINT8
) DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint8
);
199 Writes an 8-bit PCI configuration register.
201 Writes the 8-bit PCI configuration register specified by Address with the
202 value specified by Value. Value is returned. This function must guarantee
203 that all PCI read and write operations are serialized.
205 If Address > 0x0FFFFFFF, then ASSERT().
207 @param Address Address that encodes the PCI Bus, Device, Function and
209 @param Data The value to write.
211 @return The value written to the PCI configuration register.
221 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
223 return (UINT8
) DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint8
, Data
);
227 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
230 Reads the 8-bit PCI configuration register specified by Address, performs a
231 bitwise inclusive OR between the read result and the value specified by
232 OrData, and writes the result to the 8-bit PCI configuration register
233 specified by Address. The value written to the PCI configuration register is
234 returned. This function must guarantee that all PCI read and write operations
237 If Address > 0x0FFFFFFF, then ASSERT().
239 @param Address Address that encodes the PCI Bus, Device, Function and
241 @param OrData The value to OR with the PCI configuration register.
243 @return The value written back to the PCI configuration register.
253 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) | OrData
));
257 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
260 Reads the 8-bit PCI configuration register specified by Address, performs a
261 bitwise AND between the read result and the value specified by AndData, and
262 writes the result to the 8-bit PCI configuration register specified by
263 Address. The value written to the PCI configuration register is returned.
264 This function must guarantee that all PCI read and write operations are
267 If Address > 0x0FFFFFFF, then ASSERT().
269 @param Address Address that encodes the PCI Bus, Device, Function and
271 @param AndData The value to AND with the PCI configuration register.
273 @return The value written back to the PCI configuration register.
283 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) & AndData
));
287 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
288 value, followed a bitwise inclusive OR with another 8-bit value.
290 Reads the 8-bit PCI configuration register specified by Address, performs a
291 bitwise AND between the read result and the value specified by AndData,
292 performs a bitwise inclusive OR between the result of the AND operation and
293 the value specified by OrData, and writes the result to the 8-bit PCI
294 configuration register specified by Address. The value written to the PCI
295 configuration register is returned. This function must guarantee that all PCI
296 read and write operations are serialized.
298 If Address > 0x0FFFFFFF, then ASSERT().
300 @param Address Address that encodes the PCI Bus, Device, Function and
302 @param AndData The value to AND with the PCI configuration register.
303 @param OrData The value to OR with the result of the AND operation.
305 @return The value written back to the PCI configuration register.
316 return PciWrite8 (Address
, (UINT8
) ((PciRead8 (Address
) & AndData
) | OrData
));
320 Reads a bit field of a PCI configuration register.
322 Reads the bit field in an 8-bit PCI configuration register. The bit field is
323 specified by the StartBit and the EndBit. The value of the bit field is
326 If Address > 0x0FFFFFFF, then ASSERT().
327 If StartBit is greater than 7, then ASSERT().
328 If EndBit is greater than 7, then ASSERT().
329 If EndBit is less than StartBit, then ASSERT().
331 @param Address PCI configuration register to read.
332 @param StartBit The ordinal of the least significant bit in the bit field.
334 @param EndBit The ordinal of the most significant bit in the bit field.
337 @return The value of the bit field read from the PCI configuration register.
348 return BitFieldRead8 (PciRead8 (Address
), StartBit
, EndBit
);
352 Writes a bit field to a PCI configuration register.
354 Writes Value to the bit field of the PCI configuration register. The bit
355 field is specified by the StartBit and the EndBit. All other bits in the
356 destination PCI configuration register are preserved. The new value of the
357 8-bit register is returned.
359 If Address > 0x0FFFFFFF, then ASSERT().
360 If StartBit is greater than 7, then ASSERT().
361 If EndBit is greater than 7, then ASSERT().
362 If EndBit is less than StartBit, then ASSERT().
364 @param Address PCI configuration register to write.
365 @param StartBit The ordinal of the least significant bit in the bit field.
367 @param EndBit The ordinal of the most significant bit in the bit field.
369 @param Value New value of the bit field.
371 @return The value written back to the PCI configuration register.
385 BitFieldWrite8 (PciRead8 (Address
), StartBit
, EndBit
, Value
)
390 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
391 writes the result back to the bit field in the 8-bit port.
393 Reads the 8-bit PCI configuration register specified by Address, performs a
394 bitwise inclusive OR between the read result and the value specified by
395 OrData, and writes the result to the 8-bit PCI configuration register
396 specified by Address. The value written to the PCI configuration register is
397 returned. This function must guarantee that all PCI read and write operations
398 are serialized. Extra left bits in OrData are stripped.
400 If Address > 0x0FFFFFFF, then ASSERT().
401 If StartBit is greater than 7, then ASSERT().
402 If EndBit is greater than 7, then ASSERT().
403 If EndBit is less than StartBit, then ASSERT().
405 @param Address PCI configuration register to write.
406 @param StartBit The ordinal of the least significant bit in the bit field.
408 @param EndBit The ordinal of the most significant bit in the bit field.
410 @param OrData The value to OR with the PCI configuration register.
412 @return The value written back to the PCI configuration register.
426 BitFieldOr8 (PciRead8 (Address
), StartBit
, EndBit
, OrData
)
431 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
432 AND, and writes the result back to the bit field in the 8-bit register.
434 Reads the 8-bit PCI configuration register specified by Address, performs a
435 bitwise AND between the read result and the value specified by AndData, and
436 writes the result to the 8-bit PCI configuration register specified by
437 Address. The value written to the PCI configuration register is returned.
438 This function must guarantee that all PCI read and write operations are
439 serialized. Extra left bits in AndData are stripped.
441 If Address > 0x0FFFFFFF, then ASSERT().
442 If StartBit is greater than 7, then ASSERT().
443 If EndBit is greater than 7, then ASSERT().
444 If EndBit is less than StartBit, then ASSERT().
446 @param Address PCI configuration register to write.
447 @param StartBit The ordinal of the least significant bit in the bit field.
449 @param EndBit The ordinal of the most significant bit in the bit field.
451 @param AndData The value to AND with the PCI configuration register.
453 @return The value written back to the PCI configuration register.
467 BitFieldAnd8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
)
472 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
473 bitwise inclusive OR, and writes the result back to the bit field in the
476 Reads the 8-bit PCI configuration register specified by Address, performs a
477 bitwise AND followed by a bitwise inclusive OR between the read result and
478 the value specified by AndData, and writes the result to the 8-bit PCI
479 configuration register specified by Address. The value written to the PCI
480 configuration register is returned. This function must guarantee that all PCI
481 read and write operations are serialized. Extra left bits in both AndData and
484 If Address > 0x0FFFFFFF, then ASSERT().
485 If StartBit is greater than 7, then ASSERT().
486 If EndBit is greater than 7, then ASSERT().
487 If EndBit is less than StartBit, then ASSERT().
489 @param Address PCI configuration register to write.
490 @param StartBit The ordinal of the least significant bit in the bit field.
492 @param EndBit The ordinal of the most significant bit in the bit field.
494 @param AndData The value to AND with the PCI configuration register.
495 @param OrData The value to OR with the result of the AND operation.
497 @return The value written back to the PCI configuration register.
502 PciBitFieldAndThenOr8 (
512 BitFieldAndThenOr8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
517 Reads a 16-bit PCI configuration register.
519 Reads and returns the 16-bit PCI configuration register specified by Address.
520 This function must guarantee that all PCI read and write operations are
523 If Address > 0x0FFFFFFF, then ASSERT().
524 If Address is not aligned on a 16-bit boundary, then ASSERT().
526 @param Address Address that encodes the PCI Bus, Device, Function and
529 @return The value read from the PCI configuration register.
538 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
540 return (UINT16
) DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint16
);
544 Writes a 16-bit PCI configuration register.
546 Writes the 16-bit PCI configuration register specified by Address with the
547 value specified by Value. Value is returned. This function must guarantee
548 that all PCI read and write operations are serialized.
550 If Address > 0x0FFFFFFF, then ASSERT().
551 If Address is not aligned on a 16-bit boundary, then ASSERT().
553 @param Address Address that encodes the PCI Bus, Device, Function and
555 @param Data The value to write.
557 @return The value written to the PCI configuration register.
567 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
569 return (UINT16
) DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint16
, Data
);
573 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
576 Reads the 16-bit PCI configuration register specified by Address, performs a
577 bitwise inclusive OR between the read result and the value specified by
578 OrData, and writes the result to the 16-bit PCI configuration register
579 specified by Address. The value written to the PCI configuration register is
580 returned. This function must guarantee that all PCI read and write operations
583 If Address > 0x0FFFFFFF, then ASSERT().
584 If Address is not aligned on a 16-bit boundary, then ASSERT().
586 @param Address Address that encodes the PCI Bus, Device, Function and
588 @param OrData The value to OR with the PCI configuration register.
590 @return The value written back to the PCI configuration register.
600 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) | OrData
));
604 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
607 Reads the 16-bit PCI configuration register specified by Address, performs a
608 bitwise AND between the read result and the value specified by AndData, and
609 writes the result to the 16-bit PCI configuration register specified by
610 Address. The value written to the PCI configuration register is returned.
611 This function must guarantee that all PCI read and write operations are
614 If Address > 0x0FFFFFFF, then ASSERT().
615 If Address is not aligned on a 16-bit boundary, then ASSERT().
617 @param Address Address that encodes the PCI Bus, Device, Function and
619 @param AndData The value to AND with the PCI configuration register.
621 @return The value written back to the PCI configuration register.
631 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) & AndData
));
635 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
636 value, followed a bitwise inclusive OR with another 16-bit value.
638 Reads the 16-bit PCI configuration register specified by Address, performs a
639 bitwise AND between the read result and the value specified by AndData,
640 performs a bitwise inclusive OR between the result of the AND operation and
641 the value specified by OrData, and writes the result to the 16-bit PCI
642 configuration register specified by Address. The value written to the PCI
643 configuration register is returned. This function must guarantee that all PCI
644 read and write operations are serialized.
646 If Address > 0x0FFFFFFF, then ASSERT().
647 If Address is not aligned on a 16-bit boundary, then ASSERT().
649 @param Address Address that encodes the PCI Bus, Device, Function and
651 @param AndData The value to AND with the PCI configuration register.
652 @param OrData The value to OR with the result of the AND operation.
654 @return The value written back to the PCI configuration register.
665 return PciWrite16 (Address
, (UINT16
) ((PciRead16 (Address
) & AndData
) | OrData
));
669 Reads a bit field of a PCI configuration register.
671 Reads the bit field in a 16-bit PCI configuration register. The bit field is
672 specified by the StartBit and the EndBit. The value of the bit field is
675 If Address > 0x0FFFFFFF, then ASSERT().
676 If Address is not aligned on a 16-bit boundary, then ASSERT().
677 If StartBit is greater than 15, then ASSERT().
678 If EndBit is greater than 15, then ASSERT().
679 If EndBit is less than StartBit, then ASSERT().
681 @param Address PCI configuration register to read.
682 @param StartBit The ordinal of the least significant bit in the bit field.
684 @param EndBit The ordinal of the most significant bit in the bit field.
687 @return The value of the bit field read from the PCI configuration register.
698 return BitFieldRead16 (PciRead16 (Address
), StartBit
, EndBit
);
702 Writes a bit field to a PCI configuration register.
704 Writes Value to the bit field of the PCI configuration register. The bit
705 field is specified by the StartBit and the EndBit. All other bits in the
706 destination PCI configuration register are preserved. The new value of the
707 16-bit register is returned.
709 If Address > 0x0FFFFFFF, then ASSERT().
710 If Address is not aligned on a 16-bit boundary, then ASSERT().
711 If StartBit is greater than 15, then ASSERT().
712 If EndBit is greater than 15, then ASSERT().
713 If EndBit is less than StartBit, then ASSERT().
715 @param Address PCI configuration register to write.
716 @param StartBit The ordinal of the least significant bit in the bit field.
718 @param EndBit The ordinal of the most significant bit in the bit field.
720 @param Value New value of the bit field.
722 @return The value written back to the PCI configuration register.
736 BitFieldWrite16 (PciRead16 (Address
), StartBit
, EndBit
, Value
)
741 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
742 writes the result back to the bit field in the 16-bit port.
744 Reads the 16-bit PCI configuration register specified by Address, performs a
745 bitwise inclusive OR between the read result and the value specified by
746 OrData, and writes the result to the 16-bit PCI configuration register
747 specified by Address. The value written to the PCI configuration register is
748 returned. This function must guarantee that all PCI read and write operations
749 are serialized. Extra left bits in OrData are stripped.
751 If Address > 0x0FFFFFFF, then ASSERT().
752 If Address is not aligned on a 16-bit boundary, then ASSERT().
753 If StartBit is greater than 15, then ASSERT().
754 If EndBit is greater than 15, then ASSERT().
755 If EndBit is less than StartBit, then ASSERT().
757 @param Address PCI configuration register to write.
758 @param StartBit The ordinal of the least significant bit in the bit field.
760 @param EndBit The ordinal of the most significant bit in the bit field.
762 @param OrData The value to OR with the PCI configuration register.
764 @return The value written back to the PCI configuration register.
778 BitFieldOr16 (PciRead16 (Address
), StartBit
, EndBit
, OrData
)
783 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
784 AND, and writes the result back to the bit field in the 16-bit register.
786 Reads the 16-bit PCI configuration register specified by Address, performs a
787 bitwise AND between the read result and the value specified by AndData, and
788 writes the result to the 16-bit PCI configuration register specified by
789 Address. The value written to the PCI configuration register is returned.
790 This function must guarantee that all PCI read and write operations are
791 serialized. Extra left bits in AndData are stripped.
793 If Address > 0x0FFFFFFF, then ASSERT().
794 If Address is not aligned on a 16-bit boundary, then ASSERT().
795 If StartBit is greater than 15, then ASSERT().
796 If EndBit is greater than 15, then ASSERT().
797 If EndBit is less than StartBit, then ASSERT().
799 @param Address PCI configuration register to write.
800 @param StartBit The ordinal of the least significant bit in the bit field.
802 @param EndBit The ordinal of the most significant bit in the bit field.
804 @param AndData The value to AND with the PCI configuration register.
806 @return The value written back to the PCI configuration register.
820 BitFieldAnd16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
)
825 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
826 bitwise inclusive OR, and writes the result back to the bit field in the
829 Reads the 16-bit PCI configuration register specified by Address, performs a
830 bitwise AND followed by a bitwise inclusive OR between the read result and
831 the value specified by AndData, and writes the result to the 16-bit PCI
832 configuration register specified by Address. The value written to the PCI
833 configuration register is returned. This function must guarantee that all PCI
834 read and write operations are serialized. Extra left bits in both AndData and
837 If Address > 0x0FFFFFFF, then ASSERT().
838 If Address is not aligned on a 16-bit boundary, then ASSERT().
839 If StartBit is greater than 15, then ASSERT().
840 If EndBit is greater than 15, then ASSERT().
841 If EndBit is less than StartBit, then ASSERT().
843 @param Address PCI configuration register to write.
844 @param StartBit The ordinal of the least significant bit in the bit field.
846 @param EndBit The ordinal of the most significant bit in the bit field.
848 @param AndData The value to AND with the PCI configuration register.
849 @param OrData The value to OR with the result of the AND operation.
851 @return The value written back to the PCI configuration register.
856 PciBitFieldAndThenOr16 (
866 BitFieldAndThenOr16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
871 Reads a 32-bit PCI configuration register.
873 Reads and returns the 32-bit PCI configuration register specified by Address.
874 This function must guarantee that all PCI read and write operations are
877 If Address > 0x0FFFFFFF, then ASSERT().
878 If Address is not aligned on a 32-bit boundary, then ASSERT().
880 @param Address Address that encodes the PCI Bus, Device, Function and
883 @return The value read from the PCI configuration register.
892 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
894 return DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint32
);
898 Writes a 32-bit PCI configuration register.
900 Writes the 32-bit PCI configuration register specified by Address with the
901 value specified by Value. Value is returned. This function must guarantee
902 that all PCI read and write operations are serialized.
904 If Address > 0x0FFFFFFF, then ASSERT().
905 If Address is not aligned on a 32-bit boundary, then ASSERT().
907 @param Address Address that encodes the PCI Bus, Device, Function and
909 @param Data The value to write.
911 @return The value written to the PCI configuration register.
921 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
923 return DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint32
, Data
);
927 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
930 Reads the 32-bit PCI configuration register specified by Address, performs a
931 bitwise inclusive OR between the read result and the value specified by
932 OrData, and writes the result to the 32-bit PCI configuration register
933 specified by Address. The value written to the PCI configuration register is
934 returned. This function must guarantee that all PCI read and write operations
937 If Address > 0x0FFFFFFF, then ASSERT().
938 If Address is not aligned on a 32-bit boundary, then ASSERT().
940 @param Address Address that encodes the PCI Bus, Device, Function and
942 @param OrData The value to OR with the PCI configuration register.
944 @return The value written back to the PCI configuration register.
954 return PciWrite32 (Address
, PciRead32 (Address
) | OrData
);
958 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
961 Reads the 32-bit PCI configuration register specified by Address, performs a
962 bitwise AND between the read result and the value specified by AndData, and
963 writes the result to the 32-bit PCI configuration register specified by
964 Address. The value written to the PCI configuration register is returned.
965 This function must guarantee that all PCI read and write operations are
968 If Address > 0x0FFFFFFF, then ASSERT().
969 If Address is not aligned on a 32-bit boundary, then ASSERT().
971 @param Address Address that encodes the PCI Bus, Device, Function and
973 @param AndData The value to AND with the PCI configuration register.
975 @return The value written back to the PCI configuration register.
985 return PciWrite32 (Address
, PciRead32 (Address
) & AndData
);
989 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
990 value, followed a bitwise inclusive OR with another 32-bit value.
992 Reads the 32-bit PCI configuration register specified by Address, performs a
993 bitwise AND between the read result and the value specified by AndData,
994 performs a bitwise inclusive OR between the result of the AND operation and
995 the value specified by OrData, and writes the result to the 32-bit PCI
996 configuration register specified by Address. The value written to the PCI
997 configuration register is returned. This function must guarantee that all PCI
998 read and write operations are serialized.
1000 If Address > 0x0FFFFFFF, then ASSERT().
1001 If Address is not aligned on a 32-bit boundary, then ASSERT().
1003 @param Address Address that encodes the PCI Bus, Device, Function and
1005 @param AndData The value to AND with the PCI configuration register.
1006 @param OrData The value to OR with the result of the AND operation.
1008 @return The value written back to the PCI configuration register.
1019 return PciWrite32 (Address
, (PciRead32 (Address
) & AndData
) | OrData
);
1023 Reads a bit field of a PCI configuration register.
1025 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1026 specified by the StartBit and the EndBit. The value of the bit field is
1029 If Address > 0x0FFFFFFF, then ASSERT().
1030 If Address is not aligned on a 32-bit boundary, then ASSERT().
1031 If StartBit is greater than 31, then ASSERT().
1032 If EndBit is greater than 31, then ASSERT().
1033 If EndBit is less than StartBit, then ASSERT().
1035 @param Address PCI configuration register to read.
1036 @param StartBit The ordinal of the least significant bit in the bit field.
1038 @param EndBit The ordinal of the most significant bit in the bit field.
1041 @return The value of the bit field read from the PCI configuration register.
1052 return BitFieldRead32 (PciRead32 (Address
), StartBit
, EndBit
);
1056 Writes a bit field to a PCI configuration register.
1058 Writes Value to the bit field of the PCI configuration register. The bit
1059 field is specified by the StartBit and the EndBit. All other bits in the
1060 destination PCI configuration register are preserved. The new value of the
1061 32-bit register is returned.
1063 If Address > 0x0FFFFFFF, then ASSERT().
1064 If Address is not aligned on a 32-bit boundary, then ASSERT().
1065 If StartBit is greater than 31, then ASSERT().
1066 If EndBit is greater than 31, then ASSERT().
1067 If EndBit is less than StartBit, then ASSERT().
1069 @param Address PCI configuration register to write.
1070 @param StartBit The ordinal of the least significant bit in the bit field.
1072 @param EndBit The ordinal of the most significant bit in the bit field.
1074 @param Value New value of the bit field.
1076 @return The value written back to the PCI configuration register.
1081 PciBitFieldWrite32 (
1090 BitFieldWrite32 (PciRead32 (Address
), StartBit
, EndBit
, Value
)
1095 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1096 writes the result back to the bit field in the 32-bit port.
1098 Reads the 32-bit PCI configuration register specified by Address, performs a
1099 bitwise inclusive OR between the read result and the value specified by
1100 OrData, and writes the result to the 32-bit PCI configuration register
1101 specified by Address. The value written to the PCI configuration register is
1102 returned. This function must guarantee that all PCI read and write operations
1103 are serialized. Extra left bits in OrData are stripped.
1105 If Address > 0x0FFFFFFF, then ASSERT().
1106 If Address is not aligned on a 32-bit boundary, then ASSERT().
1107 If StartBit is greater than 31, then ASSERT().
1108 If EndBit is greater than 31, then ASSERT().
1109 If EndBit is less than StartBit, then ASSERT().
1111 @param Address PCI configuration register to write.
1112 @param StartBit The ordinal of the least significant bit in the bit field.
1114 @param EndBit The ordinal of the most significant bit in the bit field.
1116 @param OrData The value to OR with the PCI configuration register.
1118 @return The value written back to the PCI configuration register.
1132 BitFieldOr32 (PciRead32 (Address
), StartBit
, EndBit
, OrData
)
1137 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1138 AND, and writes the result back to the bit field in the 32-bit register.
1140 Reads the 32-bit PCI configuration register specified by Address, performs a
1141 bitwise AND between the read result and the value specified by AndData, and
1142 writes the result to the 32-bit PCI configuration register specified by
1143 Address. The value written to the PCI configuration register is returned.
1144 This function must guarantee that all PCI read and write operations are
1145 serialized. Extra left bits in AndData are stripped.
1147 If Address > 0x0FFFFFFF, then ASSERT().
1148 If Address is not aligned on a 32-bit boundary, then ASSERT().
1149 If StartBit is greater than 31, then ASSERT().
1150 If EndBit is greater than 31, then ASSERT().
1151 If EndBit is less than StartBit, then ASSERT().
1153 @param Address PCI configuration register to write.
1154 @param StartBit The ordinal of the least significant bit in the bit field.
1156 @param EndBit The ordinal of the most significant bit in the bit field.
1158 @param AndData The value to AND with the PCI configuration register.
1160 @return The value written back to the PCI configuration register.
1174 BitFieldAnd32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
)
1179 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1180 bitwise inclusive OR, and writes the result back to the bit field in the
1183 Reads the 32-bit PCI configuration register specified by Address, performs a
1184 bitwise AND followed by a bitwise inclusive OR between the read result and
1185 the value specified by AndData, and writes the result to the 32-bit PCI
1186 configuration register specified by Address. The value written to the PCI
1187 configuration register is returned. This function must guarantee that all PCI
1188 read and write operations are serialized. Extra left bits in both AndData and
1189 OrData are stripped.
1191 If Address > 0x0FFFFFFF, then ASSERT().
1192 If Address is not aligned on a 32-bit boundary, then ASSERT().
1193 If StartBit is greater than 31, then ASSERT().
1194 If EndBit is greater than 31, then ASSERT().
1195 If EndBit is less than StartBit, then ASSERT().
1197 @param Address PCI configuration register to write.
1198 @param StartBit The ordinal of the least significant bit in the bit field.
1200 @param EndBit The ordinal of the most significant bit in the bit field.
1202 @param AndData The value to AND with the PCI configuration register.
1203 @param OrData The value to OR with the result of the AND operation.
1205 @return The value written back to the PCI configuration register.
1210 PciBitFieldAndThenOr32 (
1220 BitFieldAndThenOr32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1225 Reads a range of PCI configuration registers into a caller supplied buffer.
1227 Reads the range of PCI configuration registers specified by StartAddress and
1228 Size into the buffer specified by Buffer. This function only allows the PCI
1229 configuration registers from a single PCI function to be read. Size is
1230 returned. When possible 32-bit PCI configuration read cycles are used to read
1231 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1232 and 16-bit PCI configuration read cycles may be used at the beginning and the
1235 If StartAddress > 0x0FFFFFFF, then ASSERT().
1236 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1237 If Size > 0 and Buffer is NULL, then ASSERT().
1239 @param StartAddress Starting address that encodes the PCI Bus, Device,
1240 Function and Register.
1241 @param Size Size in bytes of the transfer.
1242 @param Buffer Pointer to a buffer receiving the data read.
1250 IN UINTN StartAddress
,
1257 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1258 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1264 ASSERT (Buffer
!= NULL
);
1267 // Save Size for return
1271 if ((StartAddress
& BIT0
) != 0) {
1273 // Read a byte if StartAddress is byte aligned
1275 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1276 StartAddress
+= sizeof (UINT8
);
1277 Size
-= sizeof (UINT8
);
1278 Buffer
= (UINT8
*)Buffer
+ 1;
1281 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1283 // Read a word if StartAddress is word aligned
1285 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1286 StartAddress
+= sizeof (UINT16
);
1287 Size
-= sizeof (UINT16
);
1288 Buffer
= (UINT16
*)Buffer
+ 1;
1291 while (Size
>= sizeof (UINT32
)) {
1293 // Read as many double words as possible
1295 *(volatile UINT32
*)Buffer
= PciRead32 (StartAddress
);
1296 StartAddress
+= sizeof (UINT32
);
1297 Size
-= sizeof (UINT32
);
1298 Buffer
= (UINT32
*)Buffer
+ 1;
1301 if (Size
>= sizeof (UINT16
)) {
1303 // Read the last remaining word if exist
1305 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1306 StartAddress
+= sizeof (UINT16
);
1307 Size
-= sizeof (UINT16
);
1308 Buffer
= (UINT16
*)Buffer
+ 1;
1311 if (Size
>= sizeof (UINT8
)) {
1313 // Read the last remaining byte if exist
1315 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1322 Copies the data in a caller supplied buffer to a specified range of PCI
1323 configuration space.
1325 Writes the range of PCI configuration registers specified by StartAddress and
1326 Size from the buffer specified by Buffer. This function only allows the PCI
1327 configuration registers from a single PCI function to be written. Size is
1328 returned. When possible 32-bit PCI configuration write cycles are used to
1329 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1330 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1331 and the end of the range.
1333 If StartAddress > 0x0FFFFFFF, then ASSERT().
1334 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1335 If Size > 0 and Buffer is NULL, then ASSERT().
1337 @param StartAddress Starting address that encodes the PCI Bus, Device,
1338 Function and Register.
1339 @param Size Size in bytes of the transfer.
1340 @param Buffer Pointer to a buffer containing the data to write.
1348 IN UINTN StartAddress
,
1355 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1356 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1362 ASSERT (Buffer
!= NULL
);
1365 // Save Size for return
1369 if ((StartAddress
& BIT0
) != 0) {
1371 // Write a byte if StartAddress is byte aligned
1373 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1374 StartAddress
+= sizeof (UINT8
);
1375 Size
-= sizeof (UINT8
);
1376 Buffer
= (UINT8
*)Buffer
+ 1;
1379 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1381 // Write a word if StartAddress is word aligned
1383 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1384 StartAddress
+= sizeof (UINT16
);
1385 Size
-= sizeof (UINT16
);
1386 Buffer
= (UINT16
*)Buffer
+ 1;
1389 while (Size
>= sizeof (UINT32
)) {
1391 // Write as many double words as possible
1393 PciWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1394 StartAddress
+= sizeof (UINT32
);
1395 Size
-= sizeof (UINT32
);
1396 Buffer
= (UINT32
*)Buffer
+ 1;
1399 if (Size
>= sizeof (UINT16
)) {
1401 // Write the last remaining word if exist
1403 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1404 StartAddress
+= sizeof (UINT16
);
1405 Size
-= sizeof (UINT16
);
1406 Buffer
= (UINT16
*)Buffer
+ 1;
1409 if (Size
>= sizeof (UINT8
)) {
1411 // Write the last remaining byte if exist
1413 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);