MdePkg/Test/UnitTest/Include/Library/UnitTestHostBaseLib.h

   1 /** @file
   2   Unit Test Host BaseLib hooks.
   3
   4   Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #ifndef __UNIT_TEST_HOST_BASE_LIB_H__
  10 #define __UNIT_TEST_HOST_BASE_LIB_H__
  11
  12 /**
  13   Prototype of service with no parameters and no return value.
  14 **/
  15 typedef
  16 VOID
  17 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_VOID)(
  18   VOID
  19   );
  20
  21 /**
  22   Prototype of service that reads and returns a BOOLEAN value.
  23
  24   @return The value read.
  25 **/
  26 typedef
  27 BOOLEAN
  28 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_READ_BOOLEAN)(
  29   VOID
  30   );
  31
  32 /**
  33   Prototype of service that reads and returns a UINT16 value.
  34
  35   @return The value read.
  36 **/
  37 typedef
  38 UINT16
  39 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_READ_UINT16)(
  40   VOID
  41   );
  42
  43 /**
  44   Prototype of service that reads and returns a UINTN value.
  45
  46   @return The value read.
  47 **/
  48 typedef
  49 UINTN
  50 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_READ_UINTN)(
  51   VOID
  52   );
  53
  54 /**
  55   Prototype of service that writes and returns a UINT16 value.
  56
  57   @param[in]  Value  The value to write.
  58
  59   @return The value written.
  60 **/
  61 typedef
  62 VOID
  63 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16)(
  64   IN UINT16  Value
  65   );
  66
  67 /**
  68   Prototype of service that writes and returns a UINTN value.
  69
  70   @param[in]  Value  The value to write.
  71
  72   @return The value written.
  73 **/
  74 typedef
  75 UINTN
  76 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN)(
  77   IN UINTN  Value
  78   );
  79
  80 /**
  81   Prototype of service that reads and returns an IA32_DESCRIPTOR.
  82
  83   @param[out]  Ia32Descriptor  Pointer to the descriptor read.
  84 **/
  85 typedef
  86 VOID
  87 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR)(
  88   OUT IA32_DESCRIPTOR           *Ia32Descriptor
  89   );
  90
  91 /**
  92   Prototype of service that writes an IA32_DESCRIPTOR.
  93
  94   @param[in]  Ia32Descriptor  Pointer to the descriptor to write.
  95 **/
  96 typedef
  97 VOID
  98 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR)(
  99   IN CONST IA32_DESCRIPTOR     *Ia32Descriptor
 100   );
 101
 102 /**
 103   Retrieves CPUID information.
 104
 105   Executes the CPUID instruction with EAX set to the value specified by Index.
 106   This function always returns Index.
 107   If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
 108   If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
 109   If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
 110   If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
 111   This function is only available on IA-32 and x64.
 112
 113   @param  Index The 32-bit value to load into EAX prior to invoking the CPUID
 114                 instruction.
 115   @param  Eax   The pointer to the 32-bit EAX value returned by the CPUID
 116                 instruction. This is an optional parameter that may be NULL.
 117   @param  Ebx   The pointer to the 32-bit EBX value returned by the CPUID
 118                 instruction. This is an optional parameter that may be NULL.
 119   @param  Ecx   The pointer to the 32-bit ECX value returned by the CPUID
 120                 instruction. This is an optional parameter that may be NULL.
 121   @param  Edx   The pointer to the 32-bit EDX value returned by the CPUID
 122                 instruction. This is an optional parameter that may be NULL.
 123
 124   @return Index.
 125
 126 **/
 127 typedef
 128 UINT32
 129 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_CPUID)(
 130   IN      UINT32                    Index,
 131   OUT     UINT32                    *Eax   OPTIONAL,
 132   OUT     UINT32                    *Ebx   OPTIONAL,
 133   OUT     UINT32                    *Ecx   OPTIONAL,
 134   OUT     UINT32                    *Edx   OPTIONAL
 135   );
 136
 137 /**
 138   Retrieves CPUID information using an extended leaf identifier.
 139
 140   Executes the CPUID instruction with EAX set to the value specified by Index
 141   and ECX set to the value specified by SubIndex. This function always returns
 142   Index. This function is only available on IA-32 and x64.
 143
 144   If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
 145   If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
 146   If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
 147   If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
 148
 149   @param  Index     The 32-bit value to load into EAX prior to invoking the
 150                     CPUID instruction.
 151   @param  SubIndex  The 32-bit value to load into ECX prior to invoking the
 152                     CPUID instruction.
 153   @param  Eax       The pointer to the 32-bit EAX value returned by the CPUID
 154                     instruction. This is an optional parameter that may be
 155                     NULL.
 156   @param  Ebx       The pointer to the 32-bit EBX value returned by the CPUID
 157                     instruction. This is an optional parameter that may be
 158                     NULL.
 159   @param  Ecx       The pointer to the 32-bit ECX value returned by the CPUID
 160                     instruction. This is an optional parameter that may be
 161                     NULL.
 162   @param  Edx       The pointer to the 32-bit EDX value returned by the CPUID
 163                     instruction. This is an optional parameter that may be
 164                     NULL.
 165
 166   @return Index.
 167
 168 **/
 169 typedef
 170 UINT32
 171 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_CPUID_EX)(
 172   IN      UINT32                    Index,
 173   IN      UINT32                    SubIndex,
 174   OUT     UINT32                    *Eax   OPTIONAL,
 175   OUT     UINT32                    *Ebx   OPTIONAL,
 176   OUT     UINT32                    *Ecx   OPTIONAL,
 177   OUT     UINT32                    *Edx   OPTIONAL
 178   );
 179
 180 /**
 181   Returns a 64-bit Machine Specific Register(MSR).
 182
 183   Reads and returns the 64-bit MSR specified by Index. No parameter checking is
 184   performed on Index, and some Index values may cause CPU exceptions. The
 185   caller must either guarantee that Index is valid, or the caller must set up
 186   exception handlers to catch the exceptions. This function is only available
 187   on IA-32 and x64.
 188
 189   @param  Index The 32-bit MSR index to read.
 190
 191   @return The value of the MSR identified by Index.
 192
 193 **/
 194 typedef
 195 UINT64
 196 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_READ_MSR_64)(
 197   IN      UINT32                    Index
 198   );
 199
 200 /**
 201   Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
 202   value.
 203
 204   Writes the 64-bit value specified by Value to the MSR specified by Index. The
 205   64-bit value written to the MSR is returned. No parameter checking is
 206   performed on Index or Value, and some of these may cause CPU exceptions. The
 207   caller must either guarantee that Index and Value are valid, or the caller
 208   must establish proper exception handlers. This function is only available on
 209   IA-32 and x64.
 210
 211   @param  Index The 32-bit MSR index to write.
 212   @param  Value The 64-bit value to write to the MSR.
 213
 214   @return Value
 215
 216 **/
 217 typedef
 218 UINT64
 219 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_MSR_64)(
 220   IN      UINT32                    Index,
 221   IN      UINT64                    Value
 222   );
 223
 224 /**
 225   Reads the current value of a Performance Counter (PMC).
 226
 227   Reads and returns the current value of performance counter specified by
 228   Index. This function is only available on IA-32 and x64.
 229
 230   @param  Index The 32-bit Performance Counter index to read.
 231
 232   @return The value of the PMC specified by Index.
 233
 234 **/
 235 typedef
 236 UINT64
 237 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_READ_PMC)(
 238   IN      UINT32                    Index
 239   );
 240
 241 /**
 242   Sets up a monitor buffer that is used by AsmMwait().
 243
 244   Executes a MONITOR instruction with the register state specified by Eax, Ecx
 245   and Edx. Returns Eax. This function is only available on IA-32 and x64.
 246
 247   @param  Eax The value to load into EAX or RAX before executing the MONITOR
 248               instruction.
 249   @param  Ecx The value to load into ECX or RCX before executing the MONITOR
 250               instruction.
 251   @param  Edx The value to load into EDX or RDX before executing the MONITOR
 252               instruction.
 253
 254   @return Eax
 255
 256 **/
 257 typedef
 258 UINTN
 259 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_MONITOR)(
 260   IN      UINTN                     Eax,
 261   IN      UINTN                     Ecx,
 262   IN      UINTN                     Edx
 263   );
 264
 265 /**
 266   Executes an MWAIT instruction.
 267
 268   Executes an MWAIT instruction with the register state specified by Eax and
 269   Ecx. Returns Eax. This function is only available on IA-32 and x64.
 270
 271   @param  Eax The value to load into EAX or RAX before executing the MONITOR
 272               instruction.
 273   @param  Ecx The value to load into ECX or RCX before executing the MONITOR
 274               instruction.
 275
 276   @return Eax
 277
 278 **/
 279 typedef
 280 UINTN
 281 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_MWAIT)(
 282   IN      UINTN                     Eax,
 283   IN      UINTN                     Ecx
 284   );
 285
 286 /**
 287   Flushes a cache line from all the instruction and data caches within the
 288   coherency domain of the CPU.
 289
 290   Flushed the cache line specified by LinearAddress, and returns LinearAddress.
 291   This function is only available on IA-32 and x64.
 292
 293   @param  LinearAddress The address of the cache line to flush. If the CPU is
 294                         in a physical addressing mode, then LinearAddress is a
 295                         physical address. If the CPU is in a virtual
 296                         addressing mode, then LinearAddress is a virtual
 297                         address.
 298
 299   @return LinearAddress.
 300 **/
 301 typedef
 302 VOID *
 303 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_FLUSH_CACHE_LINE)(
 304   IN      VOID                      *LinearAddress
 305   );
 306
 307 /**
 308   Prototype of service that enables ot disables 32-bit paging modes.
 309
 310   @param  EntryPoint  A pointer to function to call with the new stack after
 311                       paging is enabled.
 312   @param  Context1    A pointer to the context to pass into the EntryPoint
 313                       function as the first parameter after paging is enabled.
 314   @param  Context2    A pointer to the context to pass into the EntryPoint
 315                       function as the second parameter after paging is enabled.
 316   @param  NewStack    A pointer to the new stack to use for the EntryPoint
 317                       function after paging is enabled.
 318
 319 **/
 320 typedef
 321 VOID
 322 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32)(
 323   IN      SWITCH_STACK_ENTRY_POINT  EntryPoint,
 324   IN      VOID                      *Context1   OPTIONAL,
 325   IN      VOID                      *Context2   OPTIONAL,
 326   IN      VOID                      *NewStack
 327   );
 328
 329 /**
 330   Enables the 64-bit paging mode on the CPU.
 331
 332   Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
 333   must be properly initialized prior to calling this service. This function
 334   assumes the current execution mode is 32-bit protected mode with flat
 335   descriptors. This function is only available on IA-32. After the 64-bit
 336   paging mode is enabled, control is transferred to the function specified by
 337   EntryPoint using the new stack specified by NewStack and passing in the
 338   parameters specified by Context1 and Context2. Context1 and Context2 are
 339   optional and may be 0. The function EntryPoint must never return.
 340
 341   If the current execution mode is not 32-bit protected mode with flat
 342   descriptors, then ASSERT().
 343   If EntryPoint is 0, then ASSERT().
 344   If NewStack is 0, then ASSERT().
 345
 346   @param  Cs          The 16-bit selector to load in the CS before EntryPoint
 347                       is called. The descriptor in the GDT that this selector
 348                       references must be setup for long mode.
 349   @param  EntryPoint  The 64-bit virtual address of the function to call with
 350                       the new stack after paging is enabled.
 351   @param  Context1    The 64-bit virtual address of the context to pass into
 352                       the EntryPoint function as the first parameter after
 353                       paging is enabled.
 354   @param  Context2    The 64-bit virtual address of the context to pass into
 355                       the EntryPoint function as the second parameter after
 356                       paging is enabled.
 357   @param  NewStack    The 64-bit virtual address of the new stack to use for
 358                       the EntryPoint function after paging is enabled.
 359
 360 **/
 361 typedef
 362 VOID
 363 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_ENABLE_PAGING_64)(
 364   IN      UINT16                    Cs,
 365   IN      UINT64                    EntryPoint,
 366   IN      UINT64                    Context1   OPTIONAL,
 367   IN      UINT64                    Context2   OPTIONAL,
 368   IN      UINT64                    NewStack
 369   );
 370
 371 /**
 372   Disables the 64-bit paging mode on the CPU.
 373
 374   Disables the 64-bit paging mode on the CPU and returns to 32-bit protected
 375   mode. This function assumes the current execution mode is 64-paging mode.
 376   This function is only available on x64. After the 64-bit paging mode is
 377   disabled, control is transferred to the function specified by EntryPoint
 378   using the new stack specified by NewStack and passing in the parameters
 379   specified by Context1 and Context2. Context1 and Context2 are optional and
 380   may be 0. The function EntryPoint must never return.
 381
 382   If the current execution mode is not 64-bit paged mode, then ASSERT().
 383   If EntryPoint is 0, then ASSERT().
 384   If NewStack is 0, then ASSERT().
 385
 386   @param  Cs          The 16-bit selector to load in the CS before EntryPoint
 387                       is called. The descriptor in the GDT that this selector
 388                       references must be setup for 32-bit protected mode.
 389   @param  EntryPoint  The 64-bit virtual address of the function to call with
 390                       the new stack after paging is disabled.
 391   @param  Context1    The 64-bit virtual address of the context to pass into
 392                       the EntryPoint function as the first parameter after
 393                       paging is disabled.
 394   @param  Context2    The 64-bit virtual address of the context to pass into
 395                       the EntryPoint function as the second parameter after
 396                       paging is disabled.
 397   @param  NewStack    The 64-bit virtual address of the new stack to use for
 398                       the EntryPoint function after paging is disabled.
 399
 400 **/
 401 typedef
 402 VOID
 403 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_DISABLE_PAGING_64)(
 404   IN      UINT16                    Cs,
 405   IN      UINT32                    EntryPoint,
 406   IN      UINT32                    Context1   OPTIONAL,
 407   IN      UINT32                    Context2   OPTIONAL,
 408   IN      UINT32                    NewStack
 409   );
 410
 411 /**
 412   Retrieves the properties for 16-bit thunk functions.
 413
 414   Computes the size of the buffer and stack below 1MB required to use the
 415   AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This
 416   buffer size is returned in RealModeBufferSize, and the stack size is returned
 417   in ExtraStackSize. If parameters are passed to the 16-bit real mode code,
 418   then the actual minimum stack size is ExtraStackSize plus the maximum number
 419   of bytes that need to be passed to the 16-bit real mode code.
 420
 421   If RealModeBufferSize is NULL, then ASSERT().
 422   If ExtraStackSize is NULL, then ASSERT().
 423
 424   @param  RealModeBufferSize  A pointer to the size of the buffer below 1MB
 425                               required to use the 16-bit thunk functions.
 426   @param  ExtraStackSize      A pointer to the extra size of stack below 1MB
 427                               that the 16-bit thunk functions require for
 428                               temporary storage in the transition to and from
 429                               16-bit real mode.
 430
 431 **/
 432 typedef
 433 VOID
 434 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_GET_THUNK_16_PROPERTIES)(
 435   OUT     UINT32                    *RealModeBufferSize,
 436   OUT     UINT32                    *ExtraStackSize
 437   );
 438
 439 /**
 440   Prototype of services that operates on a THUNK_CONTEXT structure.
 441
 442   @param  ThunkContext  A pointer to the context structure that describes the
 443                         16-bit real mode code to call.
 444
 445 **/
 446 typedef
 447 VOID
 448 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16)(
 449   IN OUT  THUNK_CONTEXT             *ThunkContext
 450   );
 451
 452 /**
 453   Patch the immediate operand of an IA32 or X64 instruction such that the byte,
 454   word, dword or qword operand is encoded at the end of the instruction's
 455   binary representation.
 456
 457   This function should be used to update object code that was compiled with
 458   NASM from assembly source code. Example:
 459
 460   NASM source code:
 461
 462         mov     eax, strict dword 0 ; the imm32 zero operand will be patched
 463     ASM_PFX(gPatchCr3):
 464         mov     cr3, eax
 465
 466   C source code:
 467
 468     X86_ASSEMBLY_PATCH_LABEL gPatchCr3;
 469     PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);
 470
 471   @param[out] InstructionEnd  Pointer right past the instruction to patch. The
 472                               immediate operand to patch is expected to
 473                               comprise the trailing bytes of the instruction.
 474                               If InstructionEnd is closer to address 0 than
 475                               ValueSize permits, then ASSERT().
 476
 477   @param[in] PatchValue       The constant to write to the immediate operand.
 478                               The caller is responsible for ensuring that
 479                               PatchValue can be represented in the byte, word,
 480                               dword or qword operand (as indicated through
 481                               ValueSize); otherwise ASSERT().
 482
 483   @param[in] ValueSize        The size of the operand in bytes; must be 1, 2,
 484                               4, or 8. ASSERT() otherwise.
 485 **/
 486 typedef
 487 VOID
 488 (EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_PATCH_INSTRUCTION_X86)(
 489   OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
 490   IN  UINT64                   PatchValue,
 491   IN  UINTN                    ValueSize
 492   );
 493
 494 ///
 495 /// Common services
 496 ///
 497 typedef struct {
 498   UNIT_TEST_HOST_BASE_LIB_VOID            EnableInterrupts;
 499   UNIT_TEST_HOST_BASE_LIB_VOID            DisableInterrupts;
 500   UNIT_TEST_HOST_BASE_LIB_VOID            EnableDisableInterrupts;
 501   UNIT_TEST_HOST_BASE_LIB_READ_BOOLEAN    GetInterruptState;
 502 } UNIT_TEST_HOST_BASE_LIB_COMMON;
 503
 504 ///
 505 /// IA32/X64 services
 506 ///
 507 typedef struct {
 508   UNIT_TEST_HOST_BASE_LIB_ASM_CPUID                      AsmCpuid;
 509   UNIT_TEST_HOST_BASE_LIB_ASM_CPUID_EX                   AsmCpuidEx;
 510   UNIT_TEST_HOST_BASE_LIB_VOID                           AsmDisableCache;
 511   UNIT_TEST_HOST_BASE_LIB_VOID                           AsmEnableCache;
 512   UNIT_TEST_HOST_BASE_LIB_ASM_READ_MSR_64                AsmReadMsr64;
 513   UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_MSR_64               AsmWriteMsr64;
 514   UNIT_TEST_HOST_BASE_LIB_READ_UINTN                     AsmReadCr0;
 515   UNIT_TEST_HOST_BASE_LIB_READ_UINTN                     AsmReadCr2;
 516   UNIT_TEST_HOST_BASE_LIB_READ_UINTN                     AsmReadCr3;
 517   UNIT_TEST_HOST_BASE_LIB_READ_UINTN                     AsmReadCr4;
 518   UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN                    AsmWriteCr0;
 519   UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN                    AsmWriteCr2;
 520   UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN                    AsmWriteCr3;
 521   UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN                    AsmWriteCr4;
 522   UNIT_TEST_HOST_BASE_LIB_READ_UINTN                     AsmReadDr0;
 523   UNIT_TEST_HOST_BASE_LIB_READ_UINTN                     AsmReadDr1;
 524   UNIT_TEST_HOST_BASE_LIB_READ_UINTN                     AsmReadDr2;
 525   UNIT_TEST_HOST_BASE_LIB_READ_UINTN                     AsmReadDr3;
 526   UNIT_TEST_HOST_BASE_LIB_READ_UINTN                     AsmReadDr4;
 527   UNIT_TEST_HOST_BASE_LIB_READ_UINTN                     AsmReadDr5;
 528   UNIT_TEST_HOST_BASE_LIB_READ_UINTN                     AsmReadDr6;
 529   UNIT_TEST_HOST_BASE_LIB_READ_UINTN                     AsmReadDr7;
 530   UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN                    AsmWriteDr0;
 531   UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN                    AsmWriteDr1;
 532   UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN                    AsmWriteDr2;
 533   UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN                    AsmWriteDr3;
 534   UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN                    AsmWriteDr4;
 535   UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN                    AsmWriteDr5;
 536   UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN                    AsmWriteDr6;
 537   UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN                    AsmWriteDr7;
 538   UNIT_TEST_HOST_BASE_LIB_READ_UINT16                    AsmReadCs;
 539   UNIT_TEST_HOST_BASE_LIB_READ_UINT16                    AsmReadDs;
 540   UNIT_TEST_HOST_BASE_LIB_READ_UINT16                    AsmReadEs;
 541   UNIT_TEST_HOST_BASE_LIB_READ_UINT16                    AsmReadFs;
 542   UNIT_TEST_HOST_BASE_LIB_READ_UINT16                    AsmReadGs;
 543   UNIT_TEST_HOST_BASE_LIB_READ_UINT16                    AsmReadSs;
 544   UNIT_TEST_HOST_BASE_LIB_READ_UINT16                    AsmReadTr;
 545   UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR       AsmReadGdtr;
 546   UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR      AsmWriteGdtr;
 547   UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR       AsmReadIdtr;
 548   UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR      AsmWriteIdtr;
 549   UNIT_TEST_HOST_BASE_LIB_READ_UINT16                    AsmReadLdtr;
 550   UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16                   AsmWriteLdtr;
 551   UNIT_TEST_HOST_BASE_LIB_ASM_READ_PMC                   AsmReadPmc;
 552   UNIT_TEST_HOST_BASE_LIB_ASM_MONITOR                    AsmMonitor;
 553   UNIT_TEST_HOST_BASE_LIB_ASM_MWAIT                      AsmMwait;
 554   UNIT_TEST_HOST_BASE_LIB_VOID                           AsmWbinvd;
 555   UNIT_TEST_HOST_BASE_LIB_VOID                           AsmInvd;
 556   UNIT_TEST_HOST_BASE_LIB_ASM_FLUSH_CACHE_LINE           AsmFlushCacheLine;
 557   UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32                  AsmEnablePaging32;
 558   UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32                  AsmDisablePaging32;
 559   UNIT_TEST_HOST_BASE_LIB_ASM_ENABLE_PAGING_64           AsmEnablePaging64;
 560   UNIT_TEST_HOST_BASE_LIB_ASM_DISABLE_PAGING_64          AsmDisablePaging64;
 561   UNIT_TEST_HOST_BASE_LIB_ASM_GET_THUNK_16_PROPERTIES    AsmGetThunk16Properties;
 562   UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16                   AsmPrepareThunk16;
 563   UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16                   AsmThunk16;
 564   UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16                   AsmPrepareAndThunk16;
 565   UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16                   AsmWriteTr;
 566   UNIT_TEST_HOST_BASE_LIB_VOID                           AsmLfence;
 567   UNIT_TEST_HOST_BASE_LIB_ASM_PATCH_INSTRUCTION_X86      PatchInstructionX86;
 568 } UNIT_TEST_HOST_BASE_LIB_X86;
 569
 570 ///
 571 /// Data structure that contains pointers structures of common services and CPU
 572 /// architctuire specific services.  Support for additional CPU architectures
 573 /// can be added to the end of this structure.
 574 ///
 575 typedef struct {
 576   UNIT_TEST_HOST_BASE_LIB_COMMON    *Common;
 577   UNIT_TEST_HOST_BASE_LIB_X86       *X86;
 578 } UNIT_TEST_HOST_BASE_LIB;
 579
 580 extern UNIT_TEST_HOST_BASE_LIB  gUnitTestHostBaseLib;
 581
 582 #endif