Moving OMAP 3530 code out of BeagleBoard package into its own package
[mirror_edk2.git] / Omap35xxPkg / Include / Omap3530 / Omap3530Prcm.h
1 /** @file
2
3 Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
4
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #ifndef __OMAP3530PRCM_H__
16 #define __OMAP3530PRCM_H__
17
18 #define CM_FCLKEN1_CORE (0x48004A00)
19 #define CM_FCLKEN3_CORE (0x48004A08)
20 #define CM_ICLKEN1_CORE (0x48004A10)
21 #define CM_ICLKEN3_CORE (0x48004A18)
22 #define CM_CLKEN2_PLL (0x48004D04)
23 #define CM_CLKSEL4_PLL (0x48004D4C)
24 #define CM_CLKSEL5_PLL (0x48004D50)
25 #define CM_FCLKEN_USBHOST (0x48005400)
26 #define CM_ICLKEN_USBHOST (0x48005410)
27
28 //Wakeup clock defintion
29 #define CM_FCLKEN_WKUP (0x48004C00)
30 #define CM_ICLKEN_WKUP (0x48004C10)
31
32 //Peripheral clock definition
33 #define CM_FCLKEN_PER (0x48005000)
34 #define CM_ICLKEN_PER (0x48005010)
35 #define CM_CLKSEL_PER (0x48005040)
36
37 //Reset management definition
38 #define PRM_RSTCTRL (0x48307250)
39 #define PRM_RSTST (0x48307258)
40
41 //CORE clock
42 #define CM_FCLKEN1_CORE_EN_I2C1_MASK (1UL << 15)
43 #define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
44 #define CM_FCLKEN1_CORE_EN_I2C1_ENABLE (1UL << 15)
45
46 #define CM_ICLKEN1_CORE_EN_I2C1_MASK (1UL << 15)
47 #define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
48 #define CM_ICLKEN1_CORE_EN_I2C1_ENABLE (1UL << 15)
49
50 #define CM_FCLKEN1_CORE_EN_MMC1_MASK (1UL << 24)
51 #define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
52 #define CM_FCLKEN1_CORE_EN_MMC1_ENABLE (1UL << 24)
53
54 #define CM_FCLKEN3_CORE_EN_USBTLL_MASK (1UL << 2)
55 #define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
56 #define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE (1UL << 2)
57
58 #define CM_ICLKEN1_CORE_EN_MMC1_MASK (1UL << 24)
59 #define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
60 #define CM_ICLKEN1_CORE_EN_MMC1_ENABLE (1UL << 24)
61
62 #define CM_ICLKEN3_CORE_EN_USBTLL_MASK (1UL << 2)
63 #define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
64 #define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE (1UL << 2)
65
66 #define CM_CLKEN_FREQSEL_075_100 (0x03UL << 4)
67 #define CM_CLKEN_ENABLE (7UL << 0)
68
69 #define CM_CLKSEL_PLL_MULT(x) (((x) & 0x07FF) << 8)
70 #define CM_CLKSEL_PLL_DIV(x) ((((x) - 1) & 0x7F) << 0)
71
72 #define CM_CLKSEL_DIV_120M(x) (((x) & 0x1F) << 0)
73
74 #define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK (1UL << 1)
75 #define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1)
76 #define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE (1UL << 1)
77
78 #define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK (1UL << 0)
79 #define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0)
80 #define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE (1UL << 0)
81
82 #define CM_ICLKEN_USBHOST_EN_USBHOST_MASK (1UL << 0)
83 #define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE (0UL << 0)
84 #define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE (1UL << 0)
85
86 //Wakeup functional clock
87 #define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
88 #define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE (1UL << 3)
89
90 #define CM_FCLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
91 #define CM_FCLKEN_WKUP_EN_WDT2_ENABLE (1UL << 5)
92
93 //Wakeup interface clock
94 #define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
95 #define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE (1UL << 3)
96
97 #define CM_ICLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
98 #define CM_ICLKEN_WKUP_EN_WDT2_ENABLE (1UL << 5)
99
100 //Peripheral functional clock
101 #define CM_FCLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
102 #define CM_FCLKEN_PER_EN_GPT3_ENABLE (1UL << 4)
103
104 #define CM_FCLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
105 #define CM_FCLKEN_PER_EN_GPT4_ENABLE (1UL << 5)
106
107 #define CM_FCLKEN_PER_EN_UART3_DISABLE (0UL << 11)
108 #define CM_FCLKEN_PER_EN_UART3_ENABLE (1UL << 11)
109
110 #define CM_FCLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
111 #define CM_FCLKEN_PER_EN_GPIO2_ENABLE (1UL << 13)
112
113 #define CM_FCLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
114 #define CM_FCLKEN_PER_EN_GPIO3_ENABLE (1UL << 14)
115
116 #define CM_FCLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
117 #define CM_FCLKEN_PER_EN_GPIO4_ENABLE (1UL << 15)
118
119 #define CM_FCLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
120 #define CM_FCLKEN_PER_EN_GPIO5_ENABLE (1UL << 16)
121
122 #define CM_FCLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
123 #define CM_FCLKEN_PER_EN_GPIO6_ENABLE (1UL << 17)
124
125 //Peripheral interface clock
126 #define CM_ICLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
127 #define CM_ICLKEN_PER_EN_GPT3_ENABLE (1UL << 4)
128
129 #define CM_ICLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
130 #define CM_ICLKEN_PER_EN_GPT4_ENABLE (1UL << 5)
131
132 #define CM_ICLKEN_PER_EN_UART3_DISABLE (0UL << 11)
133 #define CM_ICLKEN_PER_EN_UART3_ENABLE (1UL << 11)
134
135 #define CM_ICLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
136 #define CM_ICLKEN_PER_EN_GPIO2_ENABLE (1UL << 13)
137
138 #define CM_ICLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
139 #define CM_ICLKEN_PER_EN_GPIO3_ENABLE (1UL << 14)
140
141 #define CM_ICLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
142 #define CM_ICLKEN_PER_EN_GPIO4_ENABLE (1UL << 15)
143
144 #define CM_ICLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
145 #define CM_ICLKEN_PER_EN_GPIO5_ENABLE (1UL << 16)
146
147 #define CM_ICLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
148 #define CM_ICLKEN_PER_EN_GPIO6_ENABLE (1UL << 17)
149
150 //Timer source clock selection
151 #define CM_CLKSEL_PER_CLKSEL_GPT3_32K (0UL << 1)
152 #define CM_CLKSEL_PER_CLKSEL_GPT3_SYS (1UL << 1)
153
154 #define CM_CLKSEL_PER_CLKSEL_GPT4_32K (0UL << 2)
155 #define CM_CLKSEL_PER_CLKSEL_GPT4_SYS (1UL << 2)
156
157 //Reset management (Global and Cold reset)
158 #define RST_GS (0x1UL << 1)
159 #define RST_DPLL3 (0x1UL << 2)
160 #define GLOBAL_SW_RST (0x1UL << 1)
161 #define GLOBAL_COLD_RST (0x0UL << 0)
162
163 #endif // __OMAP3530PRCM_H__
164