Omap35xxPkg/Include/Omap3530/Omap3530Prcm.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #ifndef __OMAP3530PRCM_H__
  10 #define __OMAP3530PRCM_H__
  11
  12 #define CM_FCLKEN1_CORE   (0x48004A00)
  13 #define CM_FCLKEN3_CORE   (0x48004A08)
  14 #define CM_ICLKEN1_CORE   (0x48004A10)
  15 #define CM_ICLKEN3_CORE   (0x48004A18)
  16 #define CM_CLKEN2_PLL     (0x48004D04)
  17 #define CM_CLKSEL4_PLL    (0x48004D4C)
  18 #define CM_CLKSEL5_PLL    (0x48004D50)
  19 #define CM_FCLKEN_USBHOST  (0x48005400)
  20 #define CM_ICLKEN_USBHOST  (0x48005410)
  21 #define CM_CLKSTST_USBHOST (0x4800544c)
  22
  23 //Wakeup clock defintion
  24 #define CM_FCLKEN_WKUP    (0x48004C00)
  25 #define CM_ICLKEN_WKUP    (0x48004C10)
  26
  27 //Peripheral clock definition
  28 #define CM_FCLKEN_PER     (0x48005000)
  29 #define CM_ICLKEN_PER     (0x48005010)
  30 #define CM_CLKSEL_PER     (0x48005040)
  31
  32 //Reset management definition
  33 #define PRM_RSTCTRL       (0x48307250)
  34 #define PRM_RSTST         (0x48307258)
  35
  36 //CORE clock
  37 #define CM_FCLKEN1_CORE_EN_I2C1_MASK    BIT15
  38 #define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
  39 #define CM_FCLKEN1_CORE_EN_I2C1_ENABLE  BIT15
  40
  41 #define CM_ICLKEN1_CORE_EN_I2C1_MASK    BIT15
  42 #define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
  43 #define CM_ICLKEN1_CORE_EN_I2C1_ENABLE  BIT15
  44
  45 #define CM_FCLKEN1_CORE_EN_MMC1_MASK    BIT24
  46 #define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
  47 #define CM_FCLKEN1_CORE_EN_MMC1_ENABLE  BIT24
  48
  49 #define CM_FCLKEN3_CORE_EN_USBTLL_MASK    BIT2
  50 #define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
  51 #define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE  BIT2
  52
  53 #define CM_ICLKEN1_CORE_EN_MMC1_MASK    BIT24
  54 #define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
  55 #define CM_ICLKEN1_CORE_EN_MMC1_ENABLE  BIT24
  56
  57 #define CM_ICLKEN3_CORE_EN_USBTLL_MASK    BIT2
  58 #define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
  59 #define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE  BIT2
  60
  61 #define CM_CLKEN_FREQSEL_075_100        (0x03UL << 4)
  62 #define CM_CLKEN_ENABLE                 (7UL << 0)
  63
  64 #define CM_CLKSEL_PLL_MULT(x)           (((x) & 0x07FF) << 8)
  65 #define CM_CLKSEL_PLL_DIV(x)            ((((x) - 1) & 0x7F) << 0)
  66
  67 #define CM_CLKSEL_DIV_120M(x)           (((x) & 0x1F) << 0)
  68
  69 #define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK    BIT1
  70 #define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1)
  71 #define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE  BIT1
  72
  73 #define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK    BIT0
  74 #define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0)
  75 #define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE  BIT0
  76
  77 #define CM_ICLKEN_USBHOST_EN_USBHOST_MASK     BIT0
  78 #define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE  (0UL << 0)
  79 #define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE   BIT0
  80
  81 //Wakeup functional clock
  82 #define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE       (0UL << 3)
  83 #define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE        BIT3
  84
  85 #define CM_FCLKEN_WKUP_EN_WDT2_DISABLE        (0UL << 5)
  86 #define CM_FCLKEN_WKUP_EN_WDT2_ENABLE         BIT5
  87
  88 //Wakeup interface clock
  89 #define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE       (0UL << 3)
  90 #define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE        BIT3
  91
  92 #define CM_ICLKEN_WKUP_EN_WDT2_DISABLE        (0UL << 5)
  93 #define CM_ICLKEN_WKUP_EN_WDT2_ENABLE         BIT5
  94
  95 //Peripheral functional clock
  96 #define CM_FCLKEN_PER_EN_GPT3_DISABLE         (0UL << 4)
  97 #define CM_FCLKEN_PER_EN_GPT3_ENABLE          BIT4
  98
  99 #define CM_FCLKEN_PER_EN_GPT4_DISABLE         (0UL << 5)
 100 #define CM_FCLKEN_PER_EN_GPT4_ENABLE          BIT5
 101
 102 #define CM_FCLKEN_PER_EN_UART3_DISABLE        (0UL << 11)
 103 #define CM_FCLKEN_PER_EN_UART3_ENABLE         BIT11
 104
 105 #define CM_FCLKEN_PER_EN_GPIO2_DISABLE        (0UL << 13)
 106 #define CM_FCLKEN_PER_EN_GPIO2_ENABLE         BIT13
 107
 108 #define CM_FCLKEN_PER_EN_GPIO3_DISABLE        (0UL << 14)
 109 #define CM_FCLKEN_PER_EN_GPIO3_ENABLE         BIT14
 110
 111 #define CM_FCLKEN_PER_EN_GPIO4_DISABLE        (0UL << 15)
 112 #define CM_FCLKEN_PER_EN_GPIO4_ENABLE         BIT15
 113
 114 #define CM_FCLKEN_PER_EN_GPIO5_DISABLE        (0UL << 16)
 115 #define CM_FCLKEN_PER_EN_GPIO5_ENABLE         BIT16
 116
 117 #define CM_FCLKEN_PER_EN_GPIO6_DISABLE        (0UL << 17)
 118 #define CM_FCLKEN_PER_EN_GPIO6_ENABLE         BIT17
 119
 120 //Peripheral interface clock
 121 #define CM_ICLKEN_PER_EN_GPT3_DISABLE         (0UL << 4)
 122 #define CM_ICLKEN_PER_EN_GPT3_ENABLE          BIT4
 123
 124 #define CM_ICLKEN_PER_EN_GPT4_DISABLE         (0UL << 5)
 125 #define CM_ICLKEN_PER_EN_GPT4_ENABLE          BIT5
 126
 127 #define CM_ICLKEN_PER_EN_UART3_DISABLE        (0UL << 11)
 128 #define CM_ICLKEN_PER_EN_UART3_ENABLE         BIT11
 129
 130 #define CM_ICLKEN_PER_EN_GPIO2_DISABLE        (0UL << 13)
 131 #define CM_ICLKEN_PER_EN_GPIO2_ENABLE         BIT13
 132
 133 #define CM_ICLKEN_PER_EN_GPIO3_DISABLE        (0UL << 14)
 134 #define CM_ICLKEN_PER_EN_GPIO3_ENABLE         BIT14
 135
 136 #define CM_ICLKEN_PER_EN_GPIO4_DISABLE        (0UL << 15)
 137 #define CM_ICLKEN_PER_EN_GPIO4_ENABLE         BIT15
 138
 139 #define CM_ICLKEN_PER_EN_GPIO5_DISABLE        (0UL << 16)
 140 #define CM_ICLKEN_PER_EN_GPIO5_ENABLE         BIT16
 141
 142 #define CM_ICLKEN_PER_EN_GPIO6_DISABLE        (0UL << 17)
 143 #define CM_ICLKEN_PER_EN_GPIO6_ENABLE         BIT17
 144
 145 //Timer source clock selection
 146 #define CM_CLKSEL_PER_CLKSEL_GPT3_32K         (0UL << 1)
 147 #define CM_CLKSEL_PER_CLKSEL_GPT3_SYS         BIT1
 148
 149 #define CM_CLKSEL_PER_CLKSEL_GPT4_32K         (0UL << 2)
 150 #define CM_CLKSEL_PER_CLKSEL_GPT4_SYS         BIT2
 151
 152 //Reset management (Global and Cold reset)
 153 #define RST_GS            BIT1
 154 #define RST_DPLL3         BIT2
 155 #define GLOBAL_SW_RST     BIT1
 156 #define GLOBAL_COLD_RST   (0x0UL << 0)
 157
 158 #endif // __OMAP3530PRCM_H__
 159