Updating the USB subsystem init done in PciEmulation so we can use the standard EHCI...
[mirror_edk2.git] / Omap35xxPkg / Include / Omap3530 / Omap3530Prcm.h
1 /** @file
2
3 Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
4
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #ifndef __OMAP3530PRCM_H__
16 #define __OMAP3530PRCM_H__
17
18 #define CM_FCLKEN1_CORE (0x48004A00)
19 #define CM_FCLKEN3_CORE (0x48004A08)
20 #define CM_ICLKEN1_CORE (0x48004A10)
21 #define CM_ICLKEN3_CORE (0x48004A18)
22 #define CM_CLKEN2_PLL (0x48004D04)
23 #define CM_CLKSEL4_PLL (0x48004D4C)
24 #define CM_CLKSEL5_PLL (0x48004D50)
25 #define CM_FCLKEN_USBHOST (0x48005400)
26 #define CM_ICLKEN_USBHOST (0x48005410)
27 #define CM_CLKSTST_USBHOST (0x4800544c)
28
29 //Wakeup clock defintion
30 #define CM_FCLKEN_WKUP (0x48004C00)
31 #define CM_ICLKEN_WKUP (0x48004C10)
32
33 //Peripheral clock definition
34 #define CM_FCLKEN_PER (0x48005000)
35 #define CM_ICLKEN_PER (0x48005010)
36 #define CM_CLKSEL_PER (0x48005040)
37
38 //Reset management definition
39 #define PRM_RSTCTRL (0x48307250)
40 #define PRM_RSTST (0x48307258)
41
42 //CORE clock
43 #define CM_FCLKEN1_CORE_EN_I2C1_MASK (1UL << 15)
44 #define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
45 #define CM_FCLKEN1_CORE_EN_I2C1_ENABLE (1UL << 15)
46
47 #define CM_ICLKEN1_CORE_EN_I2C1_MASK (1UL << 15)
48 #define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
49 #define CM_ICLKEN1_CORE_EN_I2C1_ENABLE (1UL << 15)
50
51 #define CM_FCLKEN1_CORE_EN_MMC1_MASK (1UL << 24)
52 #define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
53 #define CM_FCLKEN1_CORE_EN_MMC1_ENABLE (1UL << 24)
54
55 #define CM_FCLKEN3_CORE_EN_USBTLL_MASK (1UL << 2)
56 #define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
57 #define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE (1UL << 2)
58
59 #define CM_ICLKEN1_CORE_EN_MMC1_MASK (1UL << 24)
60 #define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
61 #define CM_ICLKEN1_CORE_EN_MMC1_ENABLE (1UL << 24)
62
63 #define CM_ICLKEN3_CORE_EN_USBTLL_MASK (1UL << 2)
64 #define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
65 #define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE (1UL << 2)
66
67 #define CM_CLKEN_FREQSEL_075_100 (0x03UL << 4)
68 #define CM_CLKEN_ENABLE (7UL << 0)
69
70 #define CM_CLKSEL_PLL_MULT(x) (((x) & 0x07FF) << 8)
71 #define CM_CLKSEL_PLL_DIV(x) ((((x) - 1) & 0x7F) << 0)
72
73 #define CM_CLKSEL_DIV_120M(x) (((x) & 0x1F) << 0)
74
75 #define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK (1UL << 1)
76 #define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1)
77 #define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE (1UL << 1)
78
79 #define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK (1UL << 0)
80 #define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0)
81 #define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE (1UL << 0)
82
83 #define CM_ICLKEN_USBHOST_EN_USBHOST_MASK (1UL << 0)
84 #define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE (0UL << 0)
85 #define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE (1UL << 0)
86
87 //Wakeup functional clock
88 #define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
89 #define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE (1UL << 3)
90
91 #define CM_FCLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
92 #define CM_FCLKEN_WKUP_EN_WDT2_ENABLE (1UL << 5)
93
94 //Wakeup interface clock
95 #define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
96 #define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE (1UL << 3)
97
98 #define CM_ICLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
99 #define CM_ICLKEN_WKUP_EN_WDT2_ENABLE (1UL << 5)
100
101 //Peripheral functional clock
102 #define CM_FCLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
103 #define CM_FCLKEN_PER_EN_GPT3_ENABLE (1UL << 4)
104
105 #define CM_FCLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
106 #define CM_FCLKEN_PER_EN_GPT4_ENABLE (1UL << 5)
107
108 #define CM_FCLKEN_PER_EN_UART3_DISABLE (0UL << 11)
109 #define CM_FCLKEN_PER_EN_UART3_ENABLE (1UL << 11)
110
111 #define CM_FCLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
112 #define CM_FCLKEN_PER_EN_GPIO2_ENABLE (1UL << 13)
113
114 #define CM_FCLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
115 #define CM_FCLKEN_PER_EN_GPIO3_ENABLE (1UL << 14)
116
117 #define CM_FCLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
118 #define CM_FCLKEN_PER_EN_GPIO4_ENABLE (1UL << 15)
119
120 #define CM_FCLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
121 #define CM_FCLKEN_PER_EN_GPIO5_ENABLE (1UL << 16)
122
123 #define CM_FCLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
124 #define CM_FCLKEN_PER_EN_GPIO6_ENABLE (1UL << 17)
125
126 //Peripheral interface clock
127 #define CM_ICLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
128 #define CM_ICLKEN_PER_EN_GPT3_ENABLE (1UL << 4)
129
130 #define CM_ICLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
131 #define CM_ICLKEN_PER_EN_GPT4_ENABLE (1UL << 5)
132
133 #define CM_ICLKEN_PER_EN_UART3_DISABLE (0UL << 11)
134 #define CM_ICLKEN_PER_EN_UART3_ENABLE (1UL << 11)
135
136 #define CM_ICLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
137 #define CM_ICLKEN_PER_EN_GPIO2_ENABLE (1UL << 13)
138
139 #define CM_ICLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
140 #define CM_ICLKEN_PER_EN_GPIO3_ENABLE (1UL << 14)
141
142 #define CM_ICLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
143 #define CM_ICLKEN_PER_EN_GPIO4_ENABLE (1UL << 15)
144
145 #define CM_ICLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
146 #define CM_ICLKEN_PER_EN_GPIO5_ENABLE (1UL << 16)
147
148 #define CM_ICLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
149 #define CM_ICLKEN_PER_EN_GPIO6_ENABLE (1UL << 17)
150
151 //Timer source clock selection
152 #define CM_CLKSEL_PER_CLKSEL_GPT3_32K (0UL << 1)
153 #define CM_CLKSEL_PER_CLKSEL_GPT3_SYS (1UL << 1)
154
155 #define CM_CLKSEL_PER_CLKSEL_GPT4_32K (0UL << 2)
156 #define CM_CLKSEL_PER_CLKSEL_GPT4_SYS (1UL << 2)
157
158 //Reset management (Global and Cold reset)
159 #define RST_GS (0x1UL << 1)
160 #define RST_DPLL3 (0x1UL << 2)
161 #define GLOBAL_SW_RST (0x1UL << 1)
162 #define GLOBAL_COLD_RST (0x0UL << 0)
163
164 #endif // __OMAP3530PRCM_H__
165