Omap35xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c

   1 /** @file
   2   Debug Agent timer lib for OMAP 35xx.
   3
   4   Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   5
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9 #include <Base.h>
  10 #include <Library/BaseLib.h>
  11 #include <Library/IoLib.h>
  12 #include <Library/OmapLib.h>
  13 #include <Library/ArmLib.h>
  14 #include <Library/PcdLib.h>
  15
  16 #include <Omap3530/Omap3530.h>
  17
  18
  19 volatile UINT32 gVector;
  20
  21 // Cached registers
  22 volatile UINT32 gTISR;
  23 volatile UINT32 gTCLR;
  24 volatile UINT32 gTLDR;
  25 volatile UINT32 gTCRR;
  26 volatile UINT32 gTIER;
  27
  28 VOID
  29 EnableInterruptSource (
  30   VOID
  31   )
  32 {
  33   UINTN Bank;
  34   UINTN Bit;
  35
  36   // Map vector to FIQ, IRQ is default
  37   MmioWrite32 (INTCPS_ILR (gVector), 1);
  38
  39   Bank = gVector / 32;
  40   Bit  = 1UL << (gVector % 32);
  41
  42   MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);
  43 }
  44
  45 VOID
  46 DisableInterruptSource (
  47   VOID
  48   )
  49 {
  50   UINTN Bank;
  51   UINTN Bit;
  52
  53   Bank = gVector / 32;
  54   Bit  = 1UL << (gVector % 32);
  55
  56   MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);
  57 }
  58
  59
  60
  61 /**
  62   Setup all the hardware needed for the debug agents timer.
  63
  64   This function is used to set up debug enviroment. It may enable interrupts.
  65
  66 **/
  67 VOID
  68 EFIAPI
  69 DebugAgentTimerIntialize (
  70   VOID
  71   )
  72 {
  73   UINT32      TimerBaseAddress;
  74   UINT32      TimerNumber;
  75
  76   TimerNumber = PcdGet32(PcdOmap35xxDebugAgentTimer);
  77   gVector = InterruptVectorForTimer (TimerNumber);
  78
  79   // Set up the timer registers
  80   TimerBaseAddress = TimerBase (TimerNumber);
  81   gTISR = TimerBaseAddress + GPTIMER_TISR;
  82   gTCLR = TimerBaseAddress + GPTIMER_TCLR;
  83   gTLDR = TimerBaseAddress + GPTIMER_TLDR;
  84   gTCRR = TimerBaseAddress + GPTIMER_TCRR;
  85   gTIER = TimerBaseAddress + GPTIMER_TIER;
  86
  87   if ((TimerNumber < 2) || (TimerNumber > 9)) {
  88     // This code assumes one the General Purpose timers is used
  89     // GPT2 - GPT9
  90     CpuDeadLoop ();
  91   }
  92   // Set source clock for GPT2 - GPT9 to SYS_CLK
  93   MmioOr32 (CM_CLKSEL_PER, 1 << (TimerNumber - 2));
  94
  95 }
  96
  97
  98 /**
  99   Set the period for the debug agent timer. Zero means disable the timer.
 100
 101   @param[in] TimerPeriodMilliseconds    Frequency of the debug agent timer.
 102
 103 **/
 104 VOID
 105 EFIAPI
 106 DebugAgentTimerSetPeriod (
 107   IN  UINT32  TimerPeriodMilliseconds
 108   )
 109 {
 110   UINT64      TimerCount;
 111   INT32       LoadValue;
 112
 113   if (TimerPeriodMilliseconds == 0) {
 114     // Turn off GPTIMER3
 115     MmioWrite32 (gTCLR, TCLR_ST_OFF);
 116
 117     DisableInterruptSource ();
 118   } else {
 119     // Calculate required timer count
 120     TimerCount = DivU64x32(TimerPeriodMilliseconds * 1000000, PcdGet32(PcdDebugAgentTimerFreqNanoSeconds));
 121
 122     // Set GPTIMER5 Load register
 123     LoadValue = (INT32) -TimerCount;
 124     MmioWrite32 (gTLDR, LoadValue);
 125     MmioWrite32 (gTCRR, LoadValue);
 126
 127     // Enable Overflow interrupt
 128     MmioWrite32 (gTIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);
 129
 130     // Turn on GPTIMER3, it will reload at overflow
 131     MmioWrite32 (gTCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
 132
 133     EnableInterruptSource ();
 134   }
 135 }
 136
 137
 138 /**
 139   Perform End Of Interrupt for the debug agent timer. This is called in the
 140   interrupt handler after the interrupt has been processed.
 141
 142 **/
 143 VOID
 144 EFIAPI
 145 DebugAgentTimerEndOfInterrupt (
 146   VOID
 147   )
 148 {
 149    // Clear all timer interrupts
 150   MmioWrite32 (gTISR, TISR_CLEAR_ALL);
 151
 152   // Poll interrupt status bits to ensure clearing
 153   while ((MmioRead32 (gTISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);
 154
 155   MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWFIQAGR);
 156   ArmDataSynchronizationBarrier ();
 157
 158 }
 159