3 Copyright (c) 2008-2009, Apple Inc. All rights reserved.
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "PciEmulation.h"
16 #include <Omap3530/Omap3530.h>
18 EFI_CPU_ARCH_PROTOCOL
*gCpu
;
19 EMBEDDED_EXTERNAL_DEVICE
*gTPS65950
;
21 #define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44
24 ACPI_HID_DEVICE_PATH AcpiDevicePath
;
25 PCI_DEVICE_PATH PciDevicePath
;
26 EFI_DEVICE_PATH_PROTOCOL EndDevicePath
;
27 } EFI_PCI_IO_DEVICE_PATH
;
31 EFI_PCI_IO_DEVICE_PATH DevicePath
;
32 EFI_PCI_IO_PROTOCOL PciIoProtocol
;
33 PCI_TYPE00
*ConfigSpace
;
34 PCI_ROOT_BRIDGE RootBridge
;
36 } EFI_PCI_IO_PRIVATE_DATA
;
38 #define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', 'o')
39 #define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)
41 EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate
=
44 { ACPI_DEVICE_PATH
, ACPI_DP
, sizeof (ACPI_HID_DEVICE_PATH
), 0},
45 EISA_PNP_ID(0x0A03), // HID
49 { HARDWARE_DEVICE_PATH
, HW_PCI_DP
, sizeof (PCI_DEVICE_PATH
), 0},
53 { END_DEVICE_PATH_TYPE
, END_ENTIRE_DEVICE_PATH_SUBTYPE
, sizeof (EFI_DEVICE_PATH_PROTOCOL
), 0}
66 MmioOr32 (UHH_SYSCONFIG
, UHH_SYSCONFIG_SOFTRESET
);
67 // When the bit clears reset is complete
68 while ((MmioRead32 (UHH_SYSCONFIG
) & UHH_SYSCONFIG_SOFTRESET
) == UHH_SYSCONFIG_SOFTRESET
);
71 // Take USB host out of force-standby mode
72 MmioWrite32 (UHH_SYSCONFIG
, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
73 | UHH_SYSCONFIG_CLOCKACTIVITY_ON
74 | UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
75 | UHH_SYSCONFIG_ENAWAKEUP_ENABLE
76 | UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN
);
77 MmioWrite32 (UHH_HOSTCONFIG
, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
78 | UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT
79 | UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT
80 | UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE
81 | UHH_HOSTCONFIG_ENA_INCR16_ENABLE
82 | UHH_HOSTCONFIG_ENA_INCR8_ENABLE
83 | UHH_HOSTCONFIG_ENA_INCR4_ENABLE
84 | UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON
85 | UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE
);
87 // USB reset (GPIO 147 - Port 5 pin 19) output high
88 MmioAnd32(GPIO5_BASE
+ GPIO_OE
, ~BIT19
);
89 MmioWrite32 (GPIO5_BASE
+ GPIO_SETDATAOUT
, BIT19
);
91 // Get the Power IC protocol.
92 Status
= gBS
->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid
, NULL
, (VOID
**)&gTPS65950
);
93 ASSERT_EFI_ERROR(Status
);
95 //Enable power to the USB host.
96 Status
= gTPS65950
->Read(gTPS65950
, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3
, LEDEN
), 1, &Data
);
97 ASSERT_EFI_ERROR(Status
);
99 //LEDAON & LEDAPWM control the power to the USB host so enable those bits.
100 Data
|= (LEDAON
| LEDAPWM
);
102 Status
= gTPS65950
->Write(gTPS65950
, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3
, LEDEN
), 1, &Data
);
103 ASSERT_EFI_ERROR(Status
);
108 IN EFI_PCI_IO_PROTOCOL
*This
,
109 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
119 return EFI_UNSUPPORTED
;
124 IN EFI_PCI_IO_PROTOCOL
*This
,
125 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
135 return EFI_UNSUPPORTED
;
140 IN EFI_PCI_IO_PROTOCOL
*This
,
141 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
148 EFI_PCI_IO_PRIVATE_DATA
*Private
= EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This
);
150 return PciRootBridgeIoMemRead (&Private
->RootBridge
.Io
,
151 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) Width
,
152 Private
->ConfigSpace
->Device
.Bar
[BarIndex
] + Offset
,
160 IN EFI_PCI_IO_PROTOCOL
*This
,
161 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
168 EFI_PCI_IO_PRIVATE_DATA
*Private
= EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This
);
170 return PciRootBridgeIoMemWrite (&Private
->RootBridge
.Io
,
171 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) Width
,
172 Private
->ConfigSpace
->Device
.Bar
[BarIndex
] + Offset
,
180 IN EFI_PCI_IO_PROTOCOL
*This
,
181 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
189 return EFI_UNSUPPORTED
;
194 IN EFI_PCI_IO_PROTOCOL
*This
,
195 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
203 return EFI_UNSUPPORTED
;
208 IN EFI_PCI_IO_PROTOCOL
*This
,
209 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
215 EFI_PCI_IO_PRIVATE_DATA
*Private
= EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This
);
217 return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
)Width
,
222 (PTR
)(UINTN
)(((UINT8
*)Private
->ConfigSpace
) + Offset
)
228 IN EFI_PCI_IO_PROTOCOL
*This
,
229 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
235 EFI_PCI_IO_PRIVATE_DATA
*Private
= EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This
);
237 return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) Width
,
240 (PTR
)(UINTN
)(((UINT8
*)Private
->ConfigSpace
) + Offset
),
248 IN EFI_PCI_IO_PROTOCOL
*This
,
249 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
250 IN UINT8 DestBarIndex
,
251 IN UINT64 DestOffset
,
252 IN UINT8 SrcBarIndex
,
258 return EFI_UNSUPPORTED
;
263 IN EFI_PCI_IO_PROTOCOL
*This
,
264 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation
,
265 IN VOID
*HostAddress
,
266 IN OUT UINTN
*NumberOfBytes
,
267 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
271 MAP_INFO_INSTANCE
*Map
;
274 if ( HostAddress
== NULL
|| NumberOfBytes
== NULL
||
275 DeviceAddress
== NULL
|| Mapping
== NULL
) {
277 return EFI_INVALID_PARAMETER
;
281 if (Operation
>= EfiPciOperationMaximum
) {
282 return EFI_INVALID_PARAMETER
;
285 *DeviceAddress
= ConvertToPhysicalAddress (HostAddress
);
287 // Data cache flush (HostAddress, NumberOfBytes);
289 // Remember range so we can flush on the other side
290 Status
= gBS
->AllocatePool (EfiBootServicesData
, sizeof (PCI_DMA_MAP
), (VOID
**) &Map
);
291 if (EFI_ERROR(Status
)) {
292 return EFI_OUT_OF_RESOURCES
;
297 Map
->HostAddress
= (UINTN
)HostAddress
;
298 Map
->DeviceAddress
= *DeviceAddress
;
299 Map
->NumberOfBytes
= *NumberOfBytes
;
300 Map
->Operation
= Operation
;
302 // EfiCpuFlushTypeWriteBack, EfiCpuFlushTypeInvalidate
303 gCpu
->FlushDataCache (gCpu
, (EFI_PHYSICAL_ADDRESS
)(UINTN
)HostAddress
, *NumberOfBytes
, EfiCpuFlushTypeWriteBackInvalidate
);
310 IN EFI_PCI_IO_PROTOCOL
*This
,
316 if (Mapping
== NULL
) {
318 return EFI_INVALID_PARAMETER
;
321 Map
= (PCI_DMA_MAP
*)Mapping
;
322 if (Map
->Operation
== EfiPciOperationBusMasterWrite
) {
324 // Make sure we read buffer from uncached memory and not the cache
326 gCpu
->FlushDataCache (gCpu
, Map
->HostAddress
, Map
->NumberOfBytes
, EfiCpuFlushTypeInvalidate
);
335 PciIoAllocateBuffer (
336 IN EFI_PCI_IO_PROTOCOL
*This
,
337 IN EFI_ALLOCATE_TYPE Type
,
338 IN EFI_MEMORY_TYPE MemoryType
,
340 OUT VOID
**HostAddress
,
344 if (Attributes
& EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER
) {
345 return EFI_UNSUPPORTED
;
348 if (HostAddress
== NULL
) {
349 return EFI_INVALID_PARAMETER
;
353 // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
355 // We used uncached memory to keep coherency
357 if (MemoryType
== EfiBootServicesData
) {
358 *HostAddress
= UncachedAllocatePages (Pages
);
359 } else if (MemoryType
!= EfiRuntimeServicesData
) {
360 *HostAddress
= UncachedAllocateRuntimePages (Pages
);
362 return EFI_INVALID_PARAMETER
;
370 IN EFI_PCI_IO_PROTOCOL
*This
,
375 if (HostAddress
== NULL
) {
376 return EFI_INVALID_PARAMETER
;
379 UncachedFreePages (HostAddress
, Pages
);
386 IN EFI_PCI_IO_PROTOCOL
*This
394 IN EFI_PCI_IO_PROTOCOL
*This
,
395 OUT UINTN
*SegmentNumber
,
396 OUT UINTN
*BusNumber
,
397 OUT UINTN
*DeviceNumber
,
398 OUT UINTN
*FunctionNumber
401 EFI_PCI_IO_PRIVATE_DATA
*Private
= EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This
);
403 if (SegmentNumber
!= NULL
) {
404 *SegmentNumber
= Private
->Segment
;
407 if (BusNumber
!= NULL
) {
411 if (DeviceNumber
!= NULL
) {
415 if (FunctionNumber
!= NULL
) {
424 IN EFI_PCI_IO_PROTOCOL
*This
,
425 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation
,
426 IN UINT64 Attributes
,
427 OUT UINT64
*Result OPTIONAL
431 case EfiPciIoAttributeOperationGet
:
432 case EfiPciIoAttributeOperationSupported
:
433 if (Result
== NULL
) {
434 return EFI_INVALID_PARAMETER
;
436 // We are not a real PCI device so just say things we kind of do
437 *Result
= EFI_PCI_IO_ATTRIBUTE_MEMORY
| EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
| EFI_PCI_DEVICE_ENABLE
;
440 case EfiPciIoAttributeOperationSet
:
441 case EfiPciIoAttributeOperationEnable
:
442 case EfiPciIoAttributeOperationDisable
:
443 // Since we are not a real PCI device no enable/set or disable operations exist.
448 return EFI_INVALID_PARAMETER
;
454 PciIoGetBarAttributes (
455 IN EFI_PCI_IO_PROTOCOL
*This
,
457 OUT UINT64
*Supports
, OPTIONAL
458 OUT VOID
**Resources OPTIONAL
462 return EFI_UNSUPPORTED
;
466 PciIoSetBarAttributes (
467 IN EFI_PCI_IO_PROTOCOL
*This
,
468 IN UINT64 Attributes
,
470 IN OUT UINT64
*Offset
,
471 IN OUT UINT64
*Length
475 return EFI_UNSUPPORTED
;
478 EFI_PCI_IO_PROTOCOL PciIoTemplate
=
496 PciIoGetBarAttributes
,
497 PciIoSetBarAttributes
,
504 PciEmulationEntryPoint (
505 IN EFI_HANDLE ImageHandle
,
506 IN EFI_SYSTEM_TABLE
*SystemTable
511 EFI_PCI_IO_PRIVATE_DATA
*Private
;
512 UINT8 CapabilityLength
;
516 // Get the Cpu protocol for later use
517 Status
= gBS
->LocateProtocol(&gEfiCpuArchProtocolGuid
, NULL
, (VOID
**)&gCpu
);
518 ASSERT_EFI_ERROR(Status
);
520 //Configure USB host for OMAP3530.
523 // Create a private structure
524 Private
= AllocatePool(sizeof(EFI_PCI_IO_PRIVATE_DATA
));
525 if (Private
== NULL
) {
526 Status
= EFI_OUT_OF_RESOURCES
;
530 Private
->Signature
= EFI_PCI_IO_PRIVATE_DATA_SIGNATURE
; // Fill in signature
531 Private
->RootBridge
.Signature
= PCI_ROOT_BRIDGE_SIGNATURE
; // Fake Root Bridge structure needs a signature too
532 Private
->RootBridge
.MemoryStart
= USB_EHCI_HCCAPBASE
; // Get the USB capability register base
533 Private
->Segment
= 0; // Default to segment zero
535 // Find out the capability register length and number of physical ports.
536 CapabilityLength
= MmioRead8(Private
->RootBridge
.MemoryStart
);
537 PhysicalPorts
= (MmioRead32(Private
->RootBridge
.MemoryStart
+ 0x4)) & 0x0000000F;
539 // Calculate the total size of the USB registers.
540 Private
->RootBridge
.MemorySize
= CapabilityLength
+ (HOST_CONTROLLER_OPERATION_REG_SIZE
+ ((4 * PhysicalPorts
) - 1));
542 // Enable Port Power bit in Port status and control registers in EHCI register space.
543 // Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates
544 // host controller implementation includes port power control.
545 for (Count
= 0; Count
< PhysicalPorts
; Count
++) {
546 MmioOr32((Private
->RootBridge
.MemoryStart
+ CapabilityLength
+ HOST_CONTROLLER_OPERATION_REG_SIZE
+ 4*Count
), 0x00001000);
549 // Create fake PCI config space.
550 Private
->ConfigSpace
= AllocateZeroPool(sizeof(PCI_TYPE00
));
551 if (Private
->ConfigSpace
== NULL
) {
552 Status
= EFI_OUT_OF_RESOURCES
;
557 // Configure PCI config space
558 Private
->ConfigSpace
->Hdr
.VendorId
= 0x3530;
559 Private
->ConfigSpace
->Hdr
.DeviceId
= 0x3530;
560 Private
->ConfigSpace
->Hdr
.ClassCode
[0] = 0x20;
561 Private
->ConfigSpace
->Hdr
.ClassCode
[1] = 0x03;
562 Private
->ConfigSpace
->Hdr
.ClassCode
[2] = 0x0C;
563 Private
->ConfigSpace
->Device
.Bar
[0] = Private
->RootBridge
.MemoryStart
;
567 // Unique device path.
568 CopyMem(&Private
->DevicePath
, &PciIoDevicePathTemplate
, sizeof(PciIoDevicePathTemplate
));
569 Private
->DevicePath
.AcpiDevicePath
.UID
= 0;
571 // Copy protocol structure
572 CopyMem(&Private
->PciIoProtocol
, &PciIoTemplate
, sizeof(PciIoTemplate
));
574 Status
= gBS
->InstallMultipleProtocolInterfaces(&Handle
,
575 &gEfiPciIoProtocolGuid
, &Private
->PciIoProtocol
,
576 &gEfiDevicePathProtocolGuid
, &Private
->DevicePath
,
578 if (EFI_ERROR(Status
)) {
579 DEBUG((EFI_D_ERROR
, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces() failed.\n"));