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1 /** @file
2 FACP Table
3
4 Copyright (c) 2013, Red Hat, Inc.
5 Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 **/
9
10 #include "Platform.h"
11
12 EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
13 {
14 EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
15 sizeof (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE),
16 EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
17 0, // to make sum of entire table == 0
18 {EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field
19 EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)
20 EFI_ACPI_OEM_REVISION, // OEM revision number
21 EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID
22 EFI_ACPI_CREATOR_REVISION // ASL compiler revision number
23 },
24 0, // Physical addesss of FACS
25 0, // Physical address of DSDT
26 RESERVED, // System Interrupt Model in ACPI 1.0, eliminated in 2.0
27 EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED, // Preferred PM profile
28 SCI_INT_VECTOR, // System vector of SCI interrupt
29 SMI_CMD_IO_PORT, // Port address of SMI command port
30 ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI
31 ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI
32 S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state
33 0, // PState control
34 PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk
35 0, // Power Mgt 1b Event Reg Blk unsupported
36 PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk
37 0, // Power Mgt 1b Ctrl Reg Blk unsupported
38 0, // Power Mgt 2 Ctrl Reg Blk unsupported
39 PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk
40 GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk
41 0, // General Purpose Event 1 Reg Blk unsupported
42 PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk
43 PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk
44 0, // Power Mgt 2 Ctrl Reg Blk unsupported
45 PM_TM_LEN, // Byte Length of ports at pm_tm_blk
46 GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk
47 0, // General Purpose Event 1 Reg Blk unsupported
48 0, // General Purpose Event 1 Reg Blk unsupported
49 0, // _CST support
50 P_LVL2_LAT, // worst case HW latency to enter/exit C2 state
51 P_LVL3_LAT, // worst case HW latency to enter/exit C3 state
52 FLUSH_SIZE, // Size of area read to flush caches
53 FLUSH_STRIDE, // Stride used in flushing caches
54 DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg
55 DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg
56 DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM
57 MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM
58 CENTURY, // index to century in RTC CMOS RAM
59 0x0000, // Boot architecture flag (16-bit)
60 RESERVED, // reserved
61 FLAG, // Fixed feature flags
62 GAS2_IO(RESET_REG, 1), // Extended address of the Reset Register
63 RESET_VALUE, // Value for the Reset Register to reset the system
64 { RESERVED }, // reserved[3]
65 0, // 64-bit physical addesss of FACS, set at installation
66 0, // 64-bit physical addesss of DSDT, set at installation
67
68 GAS2_IO(PM1a_EVT_BLK, PM1_EVT_LEN), // Ext. addr. of PM 1a Event Reg Blk
69 { 0 }, // PM 1b Event Reg Blk unsupported
70 GAS2_IO(PM1a_CNT_BLK, PM1_CNT_LEN), // Ext. addr. of PM 1a Ctrl Reg Blk
71 { 0 }, // PM 1b Ctrl Reg Blk unsupported
72 { 0 }, // PM 2 Ctrl Reg Blk unsupported
73 GAS2_IO(PM_TMR_BLK, PM_TM_LEN), // Ext. addr. of PM Timer Ctrl Reg Blk
74 GAS2_IO(GPE0_BLK, GPE0_BLK_LEN), // Ext. addr. of GPE 0 Reg Blk
75 { 0 } // GPE 1 Reg Blk unsupported
76 };
77
78
79 VOID*
80 ReferenceAcpiTable (
81 VOID
82 )
83 {
84 //
85 // Reference the table being generated to prevent the optimizer from removing the
86 // data structure from the exeutable
87 //
88 return (VOID*)&FACP;
89 }