OvmfPkg/AcpiTables/Facp.aslc

   1 /** @file
   2   FACP Table
   3
   4   Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials are
   6   licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include "Platform.h"
  16
  17 EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
  18   {
  19     EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
  20     sizeof (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE),
  21     EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
  22     0,                          // to make sum of entire table == 0
  23     {EFI_ACPI_OEM_ID},          // OEMID is a 6 bytes long field
  24     EFI_ACPI_OEM_TABLE_ID,      // OEM table identification(8 bytes long)
  25     EFI_ACPI_OEM_REVISION,      // OEM revision number
  26     EFI_ACPI_CREATOR_ID,        // ASL compiler vendor ID
  27     EFI_ACPI_CREATOR_REVISION   // ASL compiler revision number
  28   },
  29   0,                // Physical addesss of FACS
  30   0,                // Physical address of DSDT
  31   INT_MODEL,        // System Interrupt Model
  32   RESERVED,         // reserved
  33   SCI_INT_VECTOR,   // System vector of SCI interrupt
  34   SMI_CMD_IO_PORT,  // Port address of SMI command port
  35   ACPI_ENABLE,      // value to write to port smi_cmd to enable ACPI
  36   ACPI_DISABLE,     // value to write to port smi_cmd to disable ACPI
  37   S4BIOS_REQ,       // Value to write to SMI CMD port to enter the S4BIOS state
  38   0,                // PState control
  39   PM1a_EVT_BLK,     // Port address of Power Mgt 1a Event Reg Blk
  40   PM1b_EVT_BLK,     // Port address of Power Mgt 1b Event Reg Blk
  41   PM1a_CNT_BLK,     // Port address of Power Mgt 1a Ctrl Reg Blk
  42   PM1b_CNT_BLK,     // Port address of Power Mgt 1b Ctrl Reg Blk
  43   PM2_CNT_BLK,      // Port address of Power Mgt 2  Ctrl Reg Blk
  44   PM_TMR_BLK,       // Port address of Power Mgt Timer Ctrl Reg Blk
  45   GPE0_BLK,         // Port addr of General Purpose Event 0 Reg Blk
  46   GPE1_BLK,         // Port addr of General Purpose Event 1 Reg Blk
  47   PM1_EVT_LEN,      // Byte Length of ports at pm1X_evt_blk
  48   PM1_CNT_LEN,      // Byte Length of ports at pm1X_cnt_blk
  49   PM2_CNT_LEN,      // Byte Length of ports at pm2_cnt_blk
  50   PM_TM_LEN,        // Byte Length of ports at pm_tm_blk
  51   GPE0_BLK_LEN,     // Byte Length of ports at gpe0_blk
  52   GPE1_BLK_LEN,     // Byte Length of ports at gpe1_blk
  53   GPE1_BASE,        // offset in gpe model where gpe1 events start
  54   0,                // _CST support
  55   P_LVL2_LAT,       // worst case HW latency to enter/exit C2 state
  56   P_LVL3_LAT,       // worst case HW latency to enter/exit C3 state
  57   FLUSH_SIZE,       // Size of area read to flush caches
  58   FLUSH_STRIDE,     // Stride used in flushing caches
  59   DUTY_OFFSET,      // bit location of duty cycle field in p_cnt reg
  60   DUTY_WIDTH,       // bit width of duty cycle field in p_cnt reg
  61   DAY_ALRM,         // index to day-of-month alarm in RTC CMOS RAM
  62   MON_ALRM,         // index to month-of-year alarm in RTC CMOS RAM
  63   CENTURY,          // index to century in RTC CMOS RAM
  64   0x00,             // Boot architecture flag
  65   0x00,             // Boot architecture flag
  66   RESERVED,         // reserved
  67   FLAG
  68 };
  69
  70
  71 VOID*
  72 ReferenceAcpiTable (
  73   VOID
  74   )
  75 {
  76   //
  77   // Reference the table being generated to prevent the optimizer from removing the
  78   // data structure from the exeutable
  79   //
  80   return (VOID*)&FACP;
  81 }