OvmfPkg/Bhyve/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2020, Rebecca Cran <rebecca@bsdio.com>
   5   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   6   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   7
   8   SPDX-License-Identifier: BSD-2-Clause-Patent
   9
  10 **/
  11
  12 //
  13 // The package level header files this module uses
  14 //
  15 #include <PiPei.h>
  16
  17 //
  18 // The Library classes this module consumes
  19 //
  20 #include <Library/BaseLib.h>
  21 #include <Library/DebugLib.h>
  22 #include <Library/HobLib.h>
  23 #include <Library/IoLib.h>
  24 #include <Library/MemoryAllocationLib.h>
  25 #include <Library/PcdLib.h>
  26 #include <Library/PciLib.h>
  27 #include <Library/PeimEntryPoint.h>
  28 #include <Library/PeiServicesLib.h>
  29 #include <Library/ResourcePublicationLib.h>
  30 #include <Library/LocalApicLib.h>
  31 #include <Guid/MemoryTypeInformation.h>
  32 #include <Ppi/MasterBootMode.h>
  33 #include <IndustryStandard/Pci22.h>
  34 #include <OvmfPlatforms.h>
  35
  36 #include "Platform.h"
  37 #include "Cmos.h"
  38
  39 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  40   { EfiACPIMemoryNVS,       0x004 },
  41   { EfiACPIReclaimMemory,   0x008 },
  42   { EfiReservedMemoryType,  0x004 },
  43   { EfiRuntimeServicesData, 0x024 },
  44   { EfiRuntimeServicesCode, 0x030 },
  45   { EfiBootServicesCode,    0x180 },
  46   { EfiBootServicesData,    0xF00 },
  47   { EfiMaxMemoryType,       0x000 }
  48 };
  49
  50
  51 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  52   {
  53     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  54     &gEfiPeiMasterBootModePpiGuid,
  55     NULL
  56   }
  57 };
  58
  59
  60 UINT16 mHostBridgeDevId;
  61
  62 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  63
  64 BOOLEAN mS3Supported = FALSE;
  65
  66 UINT32 mMaxCpuCount;
  67
  68 VOID
  69 AddIoMemoryBaseSizeHob (
  70   EFI_PHYSICAL_ADDRESS        MemoryBase,
  71   UINT64                      MemorySize
  72   )
  73 {
  74   BuildResourceDescriptorHob (
  75     EFI_RESOURCE_MEMORY_MAPPED_IO,
  76       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  77       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  78       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  79       EFI_RESOURCE_ATTRIBUTE_TESTED,
  80     MemoryBase,
  81     MemorySize
  82     );
  83 }
  84
  85 VOID
  86 AddReservedMemoryBaseSizeHob (
  87   EFI_PHYSICAL_ADDRESS        MemoryBase,
  88   UINT64                      MemorySize,
  89   BOOLEAN                     Cacheable
  90   )
  91 {
  92   BuildResourceDescriptorHob (
  93     EFI_RESOURCE_MEMORY_RESERVED,
  94       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  95       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  96       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  97       (Cacheable ?
  98        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
  99        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 100        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
 101        0
 102        ) |
 103       EFI_RESOURCE_ATTRIBUTE_TESTED,
 104     MemoryBase,
 105     MemorySize
 106     );
 107 }
 108
 109 VOID
 110 AddIoMemoryRangeHob (
 111   EFI_PHYSICAL_ADDRESS        MemoryBase,
 112   EFI_PHYSICAL_ADDRESS        MemoryLimit
 113   )
 114 {
 115   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 116 }
 117
 118
 119 VOID
 120 AddMemoryBaseSizeHob (
 121   EFI_PHYSICAL_ADDRESS        MemoryBase,
 122   UINT64                      MemorySize
 123   )
 124 {
 125   BuildResourceDescriptorHob (
 126     EFI_RESOURCE_SYSTEM_MEMORY,
 127       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 128       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 129       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 130       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 131       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 132       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 133       EFI_RESOURCE_ATTRIBUTE_TESTED,
 134     MemoryBase,
 135     MemorySize
 136     );
 137 }
 138
 139
 140 VOID
 141 AddMemoryRangeHob (
 142   EFI_PHYSICAL_ADDRESS        MemoryBase,
 143   EFI_PHYSICAL_ADDRESS        MemoryLimit
 144   )
 145 {
 146   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 147 }
 148
 149
 150 VOID
 151 MemMapInitialization (
 152   VOID
 153   )
 154 {
 155   UINT64        PciIoBase;
 156   UINT64        PciIoSize;
 157   RETURN_STATUS PcdStatus;
 158
 159   PciIoBase = 0xC000;
 160   PciIoSize = 0x4000;
 161
 162   //
 163   // Create Memory Type Information HOB
 164   //
 165   BuildGuidDataHob (
 166     &gEfiMemoryTypeInformationGuid,
 167     mDefaultMemoryTypeInformation,
 168     sizeof(mDefaultMemoryTypeInformation)
 169     );
 170
 171   //
 172   // Video memory + Legacy BIOS region
 173   //
 174   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 175
 176   if (TRUE) {
 177     UINT32  TopOfLowRam;
 178     UINT64  PciExBarBase;
 179     UINT32  PciBase;
 180     UINT32  PciSize;
 181
 182     TopOfLowRam = GetSystemMemorySizeBelow4gb ();
 183     PciExBarBase = 0;
 184     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 185       //
 186       // The MMCONFIG area is expected to fall between the top of low RAM and
 187       // the base of the 32-bit PCI host aperture.
 188       //
 189       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
 190       ASSERT (TopOfLowRam <= PciExBarBase);
 191       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
 192       PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
 193     } else {
 194       PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
 195     }
 196
 197     //
 198     // address       purpose   size
 199     // ------------  --------  -------------------------
 200     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 201     // 0xFC000000    gap                           44 MB
 202     // 0xFEC00000    IO-APIC                        4 KB
 203     // 0xFEC01000    gap                         1020 KB
 204     // 0xFED00000    HPET                           1 KB
 205     // 0xFED00400    gap                          111 KB
 206     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 207     // 0xFED20000    gap                          896 KB
 208     // 0xFEE00000    LAPIC                          1 MB
 209     //
 210     PciSize = 0xFC000000 - PciBase;
 211     AddIoMemoryBaseSizeHob (PciBase, PciSize);
 212     PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);
 213     ASSERT_RETURN_ERROR (PcdStatus);
 214     PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);
 215     ASSERT_RETURN_ERROR (PcdStatus);
 216
 217     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 218     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 219     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 220       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 221       //
 222       // Note: there should be an
 223       //
 224       //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
 225       //
 226       // call below, just like the one above for RCBA. However, Linux insists
 227       // that the MMCONFIG area be marked in the E820 or UEFI memory map as
 228       // "reserved memory" -- Linux does not content itself with a simple gap
 229       // in the memory map wherever the MCFG ACPI table points to.
 230       //
 231       // This appears to be a safety measure. The PCI Firmware Specification
 232       // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
 233       // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
 234       // [...]". (Emphasis added here.)
 235       //
 236       // Normally we add memory resource descriptor HOBs in
 237       // QemuInitializeRam(), and pre-allocate from those with memory
 238       // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
 239       // is most definitely not RAM; so, as an exception, cover it with
 240       // uncacheable reserved memory right here.
 241       //
 242       AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
 243       BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
 244         EfiReservedMemoryType);
 245     }
 246     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 247
 248     //
 249     // On Q35, the IO Port space is available for PCI resource allocations from
 250     // 0x6000 up.
 251     //
 252     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 253       PciIoBase = 0x6000;
 254       PciIoSize = 0xA000;
 255       ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
 256     }
 257   }
 258
 259   //
 260   // Add PCI IO Port space available for PCI resource allocations.
 261   //
 262   BuildResourceDescriptorHob (
 263     EFI_RESOURCE_IO,
 264     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 265     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 266     PciIoBase,
 267     PciIoSize
 268     );
 269   PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);
 270   ASSERT_RETURN_ERROR (PcdStatus);
 271   PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);
 272   ASSERT_RETURN_ERROR (PcdStatus);
 273 }
 274
 275 VOID
 276 NoexecDxeInitialization (
 277   VOID
 278   )
 279 {
 280 }
 281
 282 VOID
 283 PciExBarInitialization (
 284   VOID
 285   )
 286 {
 287   union {
 288     UINT64 Uint64;
 289     UINT32 Uint32[2];
 290   } PciExBarBase;
 291
 292   //
 293   // We only support the 256MB size for the MMCONFIG area:
 294   // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
 295   //
 296   // The masks used below enforce the Q35 requirements that the MMCONFIG area
 297   // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
 298   //
 299   // Note that (b) also ensures that the minimum address width we have
 300   // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
 301   // for DXE's page tables to cover the MMCONFIG area.
 302   //
 303   PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
 304   ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
 305   ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
 306
 307   //
 308   // Clear the PCIEXBAREN bit first, before programming the high register.
 309   //
 310   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
 311
 312   //
 313   // Program the high register. Then program the low register, setting the
 314   // MMCONFIG area size and enabling decoding at once.
 315   //
 316   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
 317   PciWrite32 (
 318     DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
 319     PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
 320     );
 321 }
 322
 323 VOID
 324 MiscInitialization (
 325   VOID
 326   )
 327 {
 328   UINTN         PmCmd;
 329   UINTN         Pmba;
 330   UINT32        PmbaAndVal;
 331   UINT32        PmbaOrVal;
 332   UINTN         AcpiCtlReg;
 333   UINT8         AcpiEnBit;
 334   RETURN_STATUS PcdStatus;
 335
 336   //
 337   // Disable A20 Mask
 338   //
 339   IoOr8 (0x92, BIT1);
 340
 341   //
 342   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 343   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 344   // S3 resume as well, so we build it unconditionally.)
 345   //
 346   BuildCpuHob (mPhysMemAddressWidth, 16);
 347
 348   //
 349   // Determine platform type and save Host Bridge DID to PCD
 350   //
 351   switch (mHostBridgeDevId) {
 352     case 0x1275: // BHYVE
 353     case INTEL_82441_DEVICE_ID:
 354       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 355       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 356       PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
 357       PmbaOrVal  = PIIX4_PMBA_VALUE;
 358       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 359       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 360       break;
 361     case INTEL_Q35_MCH_DEVICE_ID:
 362       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 363       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 364       PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
 365       PmbaOrVal  = ICH9_PMBASE_VALUE;
 366       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 367       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 368       break;
 369     default:
 370       DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 371         __FUNCTION__, mHostBridgeDevId));
 372       ASSERT (FALSE);
 373       return;
 374   }
 375   PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 376   ASSERT_RETURN_ERROR (PcdStatus);
 377
 378   //
 379   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 380   // has been configured (e.g., by Xen) and skip the setup here.
 381   // This matches the logic in AcpiTimerLibConstructor ().
 382   //
 383   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 384     //
 385     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 386     // 1. set PMBA
 387     //
 388     PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
 389
 390     //
 391     // 2. set PCICMD/IOSE
 392     //
 393     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 394
 395     //
 396     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 397     //
 398     PciOr8 (AcpiCtlReg, AcpiEnBit);
 399   }
 400
 401   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 402     //
 403     // Set Root Complex Register Block BAR
 404     //
 405     PciWrite32 (
 406       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 407       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 408       );
 409
 410     //
 411     // Set PCI Express Register Range Base Address
 412     //
 413     PciExBarInitialization ();
 414   }
 415 }
 416
 417
 418 VOID
 419 BootModeInitialization (
 420   VOID
 421   )
 422 {
 423   EFI_STATUS    Status;
 424
 425   if (CmosRead8 (0xF) == 0xFE) {
 426     mBootMode = BOOT_ON_S3_RESUME;
 427   }
 428   CmosWrite8 (0xF, 0x00);
 429
 430   Status = PeiServicesSetBootMode (mBootMode);
 431   ASSERT_EFI_ERROR (Status);
 432
 433   Status = PeiServicesInstallPpi (mPpiBootMode);
 434   ASSERT_EFI_ERROR (Status);
 435 }
 436
 437
 438 VOID
 439 ReserveEmuVariableNvStore (
 440   )
 441 {
 442   EFI_PHYSICAL_ADDRESS VariableStore;
 443   RETURN_STATUS        PcdStatus;
 444
 445   //
 446   // Allocate storage for NV variables early on so it will be
 447   // at a consistent address.  Since VM memory is preserved
 448   // across reboots, this allows the NV variable storage to survive
 449   // a VM reboot.
 450   //
 451   VariableStore =
 452     (EFI_PHYSICAL_ADDRESS)(UINTN)
 453       AllocateRuntimePages (
 454         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
 455         );
 456   DEBUG ((DEBUG_INFO,
 457           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 458           VariableStore,
 459           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 460         ));
 461   PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
 462   ASSERT_RETURN_ERROR (PcdStatus);
 463 }
 464
 465
 466 VOID
 467 DebugDumpCmos (
 468   VOID
 469   )
 470 {
 471   UINT32 Loop;
 472
 473   DEBUG ((DEBUG_INFO, "CMOS:\n"));
 474
 475   for (Loop = 0; Loop < 0x80; Loop++) {
 476     if ((Loop % 0x10) == 0) {
 477       DEBUG ((DEBUG_INFO, "%02x:", Loop));
 478     }
 479     DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));
 480     if ((Loop % 0x10) == 0xf) {
 481       DEBUG ((DEBUG_INFO, "\n"));
 482     }
 483   }
 484 }
 485
 486
 487 VOID
 488 S3Verification (
 489   VOID
 490   )
 491 {
 492 #if defined (MDE_CPU_X64)
 493   if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
 494     DEBUG ((DEBUG_ERROR,
 495       "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
 496     DEBUG ((DEBUG_ERROR,
 497       "%a: Please disable S3 on the QEMU command line (see the README),\n",
 498       __FUNCTION__));
 499     DEBUG ((DEBUG_ERROR,
 500       "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
 501     ASSERT (FALSE);
 502     CpuDeadLoop ();
 503   }
 504 #endif
 505 }
 506
 507
 508 /**
 509   Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.
 510   Set the mMaxCpuCount variable.
 511 **/
 512 VOID
 513 MaxCpuCountInitialization (
 514   VOID
 515   )
 516 {
 517   UINT16        ProcessorCount = 0;
 518   RETURN_STATUS PcdStatus;
 519
 520   //
 521   // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount
 522   // from the PCD default. No change to PCDs.
 523   //
 524   if (ProcessorCount == 0) {
 525     mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
 526     return;
 527   }
 528   //
 529   // Otherwise, set mMaxCpuCount to the value reported by QEMU.
 530   //
 531   mMaxCpuCount = ProcessorCount;
 532   //
 533   // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)
 534   // to wait, in the initial AP bringup, exactly as long as it takes for all of
 535   // the APs to report in. For this, we set the longest representable timeout
 536   // (approx. 71 minutes).
 537   //
 538   PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount);
 539   ASSERT_RETURN_ERROR (PcdStatus);
 540   PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);
 541   ASSERT_RETURN_ERROR (PcdStatus);
 542   DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,
 543     ProcessorCount));
 544 }
 545
 546
 547 /**
 548   Perform Platform PEI initialization.
 549
 550   @param  FileHandle      Handle of the file being invoked.
 551   @param  PeiServices     Describes the list of possible PEI Services.
 552
 553   @return EFI_SUCCESS     The PEIM initialized successfully.
 554
 555 **/
 556 EFI_STATUS
 557 EFIAPI
 558 InitializePlatform (
 559   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 560   IN CONST EFI_PEI_SERVICES     **PeiServices
 561   )
 562 {
 563   DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
 564
 565   //
 566   // Initialize Local APIC Timer hardware and disable Local APIC Timer
 567   // interrupts before initializing the Debug Agent and the debug timer is
 568   // enabled.
 569   //
 570   InitializeApicTimer (0, MAX_UINT32, TRUE, 5);
 571   DisableApicTimerInterrupt ();
 572
 573   DebugDumpCmos ();
 574
 575   BootModeInitialization ();
 576   AddressWidthInitialization ();
 577   MaxCpuCountInitialization ();
 578
 579   //
 580   // Query Host Bridge DID
 581   //
 582   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 583
 584   if (FeaturePcdGet (PcdSmmSmramRequire)) {
 585     Q35TsegMbytesInitialization ();
 586   }
 587
 588   PublishPeiMemory ();
 589
 590   InitializeRamRegions ();
 591
 592   if (mBootMode != BOOT_ON_S3_RESUME) {
 593     if (!FeaturePcdGet (PcdSmmSmramRequire)) {
 594       ReserveEmuVariableNvStore ();
 595     }
 596     PeiFvInitialization ();
 597     MemMapInitialization ();
 598     NoexecDxeInitialization ();
 599   }
 600
 601   InstallClearCacheCallback ();
 602   AmdSevInitialize ();
 603   MiscInitialization ();
 604   InstallFeatureControlCallback ();
 605
 606   return EFI_SUCCESS;
 607 }