4 Copyright (c) 2020, Rebecca Cran <rebecca@bsdio.com>
5 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
6 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
8 SPDX-License-Identifier: BSD-2-Clause-Patent
13 // The package level header files this module uses
18 // The Library classes this module consumes
20 #include <Library/BaseLib.h>
21 #include <Library/DebugLib.h>
22 #include <Library/HobLib.h>
23 #include <Library/IoLib.h>
24 #include <Library/LocalApicLib.h>
25 #include <Library/MemoryAllocationLib.h>
26 #include <Library/PcdLib.h>
27 #include <Library/PciLib.h>
28 #include <Library/PeimEntryPoint.h>
29 #include <Library/PeiServicesLib.h>
30 #include <Library/ResourcePublicationLib.h>
31 #include <Guid/MemoryTypeInformation.h>
32 #include <Ppi/MasterBootMode.h>
33 #include <IndustryStandard/Pci22.h>
34 #include <OvmfPlatforms.h>
39 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation
[] = {
40 { EfiACPIMemoryNVS
, 0x004 },
41 { EfiACPIReclaimMemory
, 0x008 },
42 { EfiReservedMemoryType
, 0x004 },
43 { EfiRuntimeServicesData
, 0x024 },
44 { EfiRuntimeServicesCode
, 0x030 },
45 { EfiBootServicesCode
, 0x180 },
46 { EfiBootServicesData
, 0xF00 },
47 { EfiMaxMemoryType
, 0x000 }
51 EFI_PEI_PPI_DESCRIPTOR mPpiBootMode
[] = {
53 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
54 &gEfiPeiMasterBootModePpiGuid
,
60 UINT16 mHostBridgeDevId
;
62 EFI_BOOT_MODE mBootMode
= BOOT_WITH_FULL_CONFIGURATION
;
64 BOOLEAN mS3Supported
= FALSE
;
69 AddIoMemoryBaseSizeHob (
70 EFI_PHYSICAL_ADDRESS MemoryBase
,
74 BuildResourceDescriptorHob (
75 EFI_RESOURCE_MEMORY_MAPPED_IO
,
76 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
77 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
78 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
79 EFI_RESOURCE_ATTRIBUTE_TESTED
,
86 AddReservedMemoryBaseSizeHob (
87 EFI_PHYSICAL_ADDRESS MemoryBase
,
92 BuildResourceDescriptorHob (
93 EFI_RESOURCE_MEMORY_RESERVED
,
94 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
95 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
96 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
98 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
99 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
100 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
:
103 EFI_RESOURCE_ATTRIBUTE_TESTED
,
110 AddIoMemoryRangeHob (
111 EFI_PHYSICAL_ADDRESS MemoryBase
,
112 EFI_PHYSICAL_ADDRESS MemoryLimit
115 AddIoMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
120 AddMemoryBaseSizeHob (
121 EFI_PHYSICAL_ADDRESS MemoryBase
,
125 BuildResourceDescriptorHob (
126 EFI_RESOURCE_SYSTEM_MEMORY
,
127 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
128 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
129 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
130 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
131 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
132 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
|
133 EFI_RESOURCE_ATTRIBUTE_TESTED
,
142 EFI_PHYSICAL_ADDRESS MemoryBase
,
143 EFI_PHYSICAL_ADDRESS MemoryLimit
146 AddMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
151 MemMapInitialization (
157 RETURN_STATUS PcdStatus
;
163 // Create Memory Type Information HOB
166 &gEfiMemoryTypeInformationGuid
,
167 mDefaultMemoryTypeInformation
,
168 sizeof(mDefaultMemoryTypeInformation
)
172 // Video memory + Legacy BIOS region
174 AddIoMemoryRangeHob (0x0A0000, BASE_1MB
);
182 TopOfLowRam
= GetSystemMemorySizeBelow4gb ();
184 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
186 // The MMCONFIG area is expected to fall between the top of low RAM and
187 // the base of the 32-bit PCI host aperture.
189 PciExBarBase
= FixedPcdGet64 (PcdPciExpressBaseAddress
);
190 ASSERT (TopOfLowRam
<= PciExBarBase
);
191 ASSERT (PciExBarBase
<= MAX_UINT32
- SIZE_256MB
);
192 PciBase
= (UINT32
)(PciExBarBase
+ SIZE_256MB
);
194 PciBase
= (TopOfLowRam
< BASE_2GB
) ? BASE_2GB
: TopOfLowRam
;
198 // address purpose size
199 // ------------ -------- -------------------------
200 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
201 // 0xFC000000 gap 44 MB
202 // 0xFEC00000 IO-APIC 4 KB
203 // 0xFEC01000 gap 1020 KB
204 // 0xFED00000 HPET 1 KB
205 // 0xFED00400 gap 111 KB
206 // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
207 // 0xFED20000 gap 896 KB
208 // 0xFEE00000 LAPIC 1 MB
210 PciSize
= 0xFC000000 - PciBase
;
211 AddIoMemoryBaseSizeHob (PciBase
, PciSize
);
212 PcdStatus
= PcdSet64S (PcdPciMmio32Base
, PciBase
);
213 ASSERT_RETURN_ERROR (PcdStatus
);
214 PcdStatus
= PcdSet64S (PcdPciMmio32Size
, PciSize
);
215 ASSERT_RETURN_ERROR (PcdStatus
);
217 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB
);
218 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB
);
219 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
220 AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE
, SIZE_16KB
);
222 // Note: there should be an
224 // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
226 // call below, just like the one above for RCBA. However, Linux insists
227 // that the MMCONFIG area be marked in the E820 or UEFI memory map as
228 // "reserved memory" -- Linux does not content itself with a simple gap
229 // in the memory map wherever the MCFG ACPI table points to.
231 // This appears to be a safety measure. The PCI Firmware Specification
232 // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
233 // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
234 // [...]". (Emphasis added here.)
236 // Normally we add memory resource descriptor HOBs in
237 // QemuInitializeRam(), and pre-allocate from those with memory
238 // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
239 // is most definitely not RAM; so, as an exception, cover it with
240 // uncacheable reserved memory right here.
242 AddReservedMemoryBaseSizeHob (PciExBarBase
, SIZE_256MB
, FALSE
);
243 BuildMemoryAllocationHob (PciExBarBase
, SIZE_256MB
,
244 EfiReservedMemoryType
);
246 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress
), SIZE_1MB
);
249 // On Q35, the IO Port space is available for PCI resource allocations from
252 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
255 ASSERT ((ICH9_PMBASE_VALUE
& 0xF000) < PciIoBase
);
260 // Add PCI IO Port space available for PCI resource allocations.
262 BuildResourceDescriptorHob (
264 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
265 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
,
269 PcdStatus
= PcdSet64S (PcdPciIoBase
, PciIoBase
);
270 ASSERT_RETURN_ERROR (PcdStatus
);
271 PcdStatus
= PcdSet64S (PcdPciIoSize
, PciIoSize
);
272 ASSERT_RETURN_ERROR (PcdStatus
);
276 NoexecDxeInitialization (
283 PciExBarInitialization (
293 // We only support the 256MB size for the MMCONFIG area:
294 // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
296 // The masks used below enforce the Q35 requirements that the MMCONFIG area
297 // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
299 // Note that (b) also ensures that the minimum address width we have
300 // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
301 // for DXE's page tables to cover the MMCONFIG area.
303 PciExBarBase
.Uint64
= FixedPcdGet64 (PcdPciExpressBaseAddress
);
304 ASSERT ((PciExBarBase
.Uint32
[1] & MCH_PCIEXBAR_HIGHMASK
) == 0);
305 ASSERT ((PciExBarBase
.Uint32
[0] & MCH_PCIEXBAR_LOWMASK
) == 0);
308 // Clear the PCIEXBAREN bit first, before programming the high register.
310 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW
), 0);
313 // Program the high register. Then program the low register, setting the
314 // MMCONFIG area size and enabling decoding at once.
316 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH
), PciExBarBase
.Uint32
[1]);
318 DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW
),
319 PciExBarBase
.Uint32
[0] | MCH_PCIEXBAR_BUS_FF
| MCH_PCIEXBAR_EN
334 RETURN_STATUS PcdStatus
;
342 // Build the CPU HOB with guest RAM size dependent address width and 16-bits
343 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
344 // S3 resume as well, so we build it unconditionally.)
346 BuildCpuHob (mPhysMemAddressWidth
, 16);
349 // Determine platform type and save Host Bridge DID to PCD
351 switch (mHostBridgeDevId
) {
352 case 0x7432: // BHYVE (AMD hostbridge)
353 case 0x1275: // BHYVE (Intel hostbridge)
354 case INTEL_82441_DEVICE_ID
:
355 PmCmd
= POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET
);
356 Pmba
= POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA
);
357 PmbaAndVal
= ~(UINT32
)PIIX4_PMBA_MASK
;
358 PmbaOrVal
= PIIX4_PMBA_VALUE
;
359 AcpiCtlReg
= POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC
);
360 AcpiEnBit
= PIIX4_PMREGMISC_PMIOSE
;
362 case INTEL_Q35_MCH_DEVICE_ID
:
363 PmCmd
= POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET
);
364 Pmba
= POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE
);
365 PmbaAndVal
= ~(UINT32
)ICH9_PMBASE_MASK
;
366 PmbaOrVal
= ICH9_PMBASE_VALUE
;
367 AcpiCtlReg
= POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL
);
368 AcpiEnBit
= ICH9_ACPI_CNTL_ACPI_EN
;
371 DEBUG ((DEBUG_ERROR
, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
372 __FUNCTION__
, mHostBridgeDevId
));
376 PcdStatus
= PcdSet16S (PcdOvmfHostBridgePciDevId
, mHostBridgeDevId
);
377 ASSERT_RETURN_ERROR (PcdStatus
);
380 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
381 // has been configured (e.g., by Xen) and skip the setup here.
382 // This matches the logic in AcpiTimerLibConstructor ().
384 if ((PciRead8 (AcpiCtlReg
) & AcpiEnBit
) == 0) {
386 // The PEI phase should be exited with fully accessibe ACPI PM IO space:
389 PciAndThenOr32 (Pmba
, PmbaAndVal
, PmbaOrVal
);
392 // 2. set PCICMD/IOSE
394 PciOr8 (PmCmd
, EFI_PCI_COMMAND_IO_SPACE
);
397 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
399 PciOr8 (AcpiCtlReg
, AcpiEnBit
);
402 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
404 // Set Root Complex Register Block BAR
407 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA
),
408 ICH9_ROOT_COMPLEX_BASE
| ICH9_RCBA_EN
412 // Set PCI Express Register Range Base Address
414 PciExBarInitialization ();
420 BootModeInitialization (
426 if (CmosRead8 (0xF) == 0xFE) {
427 mBootMode
= BOOT_ON_S3_RESUME
;
429 CmosWrite8 (0xF, 0x00);
431 Status
= PeiServicesSetBootMode (mBootMode
);
432 ASSERT_EFI_ERROR (Status
);
434 Status
= PeiServicesInstallPpi (mPpiBootMode
);
435 ASSERT_EFI_ERROR (Status
);
440 ReserveEmuVariableNvStore (
443 EFI_PHYSICAL_ADDRESS VariableStore
;
444 RETURN_STATUS PcdStatus
;
447 // Allocate storage for NV variables early on so it will be
448 // at a consistent address. Since VM memory is preserved
449 // across reboots, this allows the NV variable storage to survive
453 (EFI_PHYSICAL_ADDRESS
)(UINTN
)
454 AllocateRuntimePages (
455 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
))
458 "Reserved variable store memory: 0x%lX; size: %dkb\n",
460 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
)) / 1024
462 PcdStatus
= PcdSet64S (PcdEmuVariableNvStoreReserved
, VariableStore
);
463 ASSERT_RETURN_ERROR (PcdStatus
);
474 DEBUG ((DEBUG_INFO
, "CMOS:\n"));
476 for (Loop
= 0; Loop
< 0x80; Loop
++) {
477 if ((Loop
% 0x10) == 0) {
478 DEBUG ((DEBUG_INFO
, "%02x:", Loop
));
480 DEBUG ((DEBUG_INFO
, " %02x", CmosRead8 (Loop
)));
481 if ((Loop
% 0x10) == 0xf) {
482 DEBUG ((DEBUG_INFO
, "\n"));
493 #if defined (MDE_CPU_X64)
494 if (FeaturePcdGet (PcdSmmSmramRequire
) && mS3Supported
) {
496 "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__
));
498 "%a: Please disable S3 on the QEMU command line (see the README),\n",
501 "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__
));
510 Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.
511 Set the mMaxCpuCount variable.
514 MaxCpuCountInitialization (
518 UINT16 ProcessorCount
= 0;
519 RETURN_STATUS PcdStatus
;
522 // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount
523 // from the PCD default. No change to PCDs.
525 if (ProcessorCount
== 0) {
526 mMaxCpuCount
= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
);
530 // Otherwise, set mMaxCpuCount to the value reported by QEMU.
532 mMaxCpuCount
= ProcessorCount
;
534 // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)
535 // to wait, in the initial AP bringup, exactly as long as it takes for all of
536 // the APs to report in. For this, we set the longest representable timeout
537 // (approx. 71 minutes).
539 PcdStatus
= PcdSet32S (PcdCpuMaxLogicalProcessorNumber
, ProcessorCount
);
540 ASSERT_RETURN_ERROR (PcdStatus
);
541 PcdStatus
= PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds
, MAX_UINT32
);
542 ASSERT_RETURN_ERROR (PcdStatus
);
543 DEBUG ((DEBUG_INFO
, "%a: QEMU reports %d processor(s)\n", __FUNCTION__
,
549 Perform Platform PEI initialization.
551 @param FileHandle Handle of the file being invoked.
552 @param PeiServices Describes the list of possible PEI Services.
554 @return EFI_SUCCESS The PEIM initialized successfully.
560 IN EFI_PEI_FILE_HANDLE FileHandle
,
561 IN CONST EFI_PEI_SERVICES
**PeiServices
564 DEBUG ((DEBUG_INFO
, "Platform PEIM Loaded\n"));
567 // Initialize Local APIC Timer hardware and disable Local APIC Timer
568 // interrupts before initializing the Debug Agent and the debug timer is
571 InitializeApicTimer (0, MAX_UINT32
, TRUE
, 5);
572 DisableApicTimerInterrupt ();
576 BootModeInitialization ();
577 AddressWidthInitialization ();
578 MaxCpuCountInitialization ();
581 // Query Host Bridge DID
583 mHostBridgeDevId
= PciRead16 (OVMF_HOSTBRIDGE_DID
);
585 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
586 Q35TsegMbytesInitialization ();
591 InitializeRamRegions ();
593 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
594 if (!FeaturePcdGet (PcdSmmSmramRequire
)) {
595 ReserveEmuVariableNvStore ();
597 PeiFvInitialization ();
598 MemMapInitialization ();
599 NoexecDxeInitialization ();
602 InstallClearCacheCallback ();
604 MiscInitialization ();
605 InstallFeatureControlCallback ();