OvmfPkg/Include/IndustryStandard/Q35MchIch9.h

   1 /** @file
   2   Various register numbers and value bits based on the following publications:
   3   - Intel(R) datasheet 316966-002
   4   - Intel(R) datasheet 316972-004
   5
   6   Copyright (C) 2015, Red Hat, Inc.
   7   Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>
   8
   9   SPDX-License-Identifier: BSD-2-Clause-Patent
  10 **/
  11
  12 #ifndef __Q35_MCH_ICH9_H__
  13 #define __Q35_MCH_ICH9_H__
  14
  15 #include <Library/PciLib.h>
  16 #include <Uefi/UefiBaseType.h>
  17 #include <Uefi/UefiSpec.h>
  18 #include <Protocol/PciRootBridgeIo.h>
  19
  20 //
  21 // Host Bridge Device ID (DID) value for Q35/MCH
  22 //
  23 #define INTEL_Q35_MCH_DEVICE_ID 0x29C0
  24
  25 //
  26 // B/D/F/Type: 0/0/0/PCI
  27 //
  28 #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
  29
  30 #define MCH_EXT_TSEG_MB       0x50
  31 #define MCH_EXT_TSEG_MB_QUERY   0xFFFF
  32
  33 #define MCH_GGC               0x52
  34 #define MCH_GGC_IVD             BIT1
  35
  36 #define MCH_PCIEXBAR_LOW      0x60
  37 #define MCH_PCIEXBAR_LOWMASK    0x0FFFFFFF
  38 #define MCH_PCIEXBAR_BUS_FF     0
  39 #define MCH_PCIEXBAR_EN         BIT0
  40
  41 #define MCH_PCIEXBAR_HIGH     0x64
  42 #define MCH_PCIEXBAR_HIGHMASK   0xFFFFFFF0
  43
  44 #define MCH_PAM0              0x90
  45 #define MCH_PAM1              0x91
  46 #define MCH_PAM2              0x92
  47 #define MCH_PAM3              0x93
  48 #define MCH_PAM4              0x94
  49 #define MCH_PAM5              0x95
  50 #define MCH_PAM6              0x96
  51
  52 #define MCH_SMRAM             0x9D
  53 #define MCH_SMRAM_D_LCK         BIT4
  54 #define MCH_SMRAM_G_SMRAME      BIT3
  55
  56 #define MCH_ESMRAMC           0x9E
  57 #define MCH_ESMRAMC_H_SMRAME    BIT7
  58 #define MCH_ESMRAMC_E_SMERR     BIT6
  59 #define MCH_ESMRAMC_SM_CACHE    BIT5
  60 #define MCH_ESMRAMC_SM_L1       BIT4
  61 #define MCH_ESMRAMC_SM_L2       BIT3
  62 #define MCH_ESMRAMC_TSEG_EXT    (BIT2 | BIT1)
  63 #define MCH_ESMRAMC_TSEG_8MB    BIT2
  64 #define MCH_ESMRAMC_TSEG_2MB    BIT1
  65 #define MCH_ESMRAMC_TSEG_1MB    0
  66 #define MCH_ESMRAMC_TSEG_MASK   (BIT2 | BIT1)
  67 #define MCH_ESMRAMC_T_EN        BIT0
  68
  69 #define MCH_GBSM              0xA4
  70 #define MCH_GBSM_MB_SHIFT       20
  71
  72 #define MCH_BGSM              0xA8
  73 #define MCH_BGSM_MB_SHIFT       20
  74
  75 #define MCH_TSEGMB            0xAC
  76 #define MCH_TSEGMB_MB_SHIFT     20
  77
  78 #define MCH_TOLUD             0xB0
  79 #define MCH_TOLUD_MB_SHIFT      4
  80
  81 //
  82 // B/D/F/Type: 0/0x1f/0/PCI
  83 //
  84 #define POWER_MGMT_REGISTER_Q35(Offset) \
  85   PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))
  86
  87 #define POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS(Offset) \
  88   EFI_PCI_ADDRESS (0, 0x1f, 0, (Offset))
  89
  90 #define ICH9_PMBASE               0x40
  91 #define ICH9_PMBASE_MASK            (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
  92                                      BIT10 | BIT9  | BIT8  | BIT7)
  93
  94 #define ICH9_ACPI_CNTL            0x44
  95 #define ICH9_ACPI_CNTL_ACPI_EN      BIT7
  96
  97 #define ICH9_GEN_PMCON_1          0xA0
  98 #define ICH9_GEN_PMCON_1_SMI_LOCK   BIT4
  99
 100 #define ICH9_RCBA                 0xF0
 101 #define ICH9_RCBA_EN                BIT0
 102
 103 //
 104 // IO ports
 105 //
 106 #define ICH9_APM_CNT 0xB2
 107 #define ICH9_APM_STS 0xB3
 108
 109 #define ICH9_CPU_HOTPLUG_BASE 0x0CD8
 110
 111 //
 112 // IO ports relative to PMBASE
 113 //
 114 #define ICH9_PMBASE_OFS_SMI_EN 0x30
 115 #define ICH9_SMI_EN_APMC_EN      BIT5
 116 #define ICH9_SMI_EN_GBL_SMI_EN   BIT0
 117
 118 #define ICH9_ROOT_COMPLEX_BASE 0xFED1C000
 119
 120 #endif