OvmfPkg/Include/IndustryStandard/Q35MchIch9.h

   1 /** @file
   2   Various register numbers and value bits based on the following publications:
   3   - Intel(R) datasheet 316966-002
   4   - Intel(R) datasheet 316972-004
   5
   6   Copyright (C) 2015, Red Hat, Inc.
   7   Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>
   8
   9   This program and the accompanying materials are licensed and made available
  10   under the terms and conditions of the BSD License which accompanies this
  11   distribution.   The full text of the license may be found at
  12   http://opensource.org/licenses/bsd-license.php
  13
  14   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
  15   WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  16 **/
  17
  18 #ifndef __Q35_MCH_ICH9_H__
  19 #define __Q35_MCH_ICH9_H__
  20
  21 #include <Library/PciLib.h>
  22
  23 //
  24 // Host Bridge Device ID (DID) value for Q35/MCH
  25 //
  26 #define INTEL_Q35_MCH_DEVICE_ID 0x29C0
  27
  28 //
  29 // B/D/F/Type: 0/0/0/PCI
  30 //
  31 #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
  32
  33 #define MCH_GGC               0x52
  34 #define MCH_GGC_IVD             BIT1
  35
  36 #define MCH_SMRAM             0x9D
  37 #define MCH_SMRAM_D_LCK         BIT4
  38 #define MCH_SMRAM_G_SMRAME      BIT3
  39
  40 #define MCH_ESMRAMC           0x9E
  41 #define MCH_ESMRAMC_H_SMRAME    BIT7
  42 #define MCH_ESMRAMC_E_SMERR     BIT6
  43 #define MCH_ESMRAMC_SM_CACHE    BIT5
  44 #define MCH_ESMRAMC_SM_L1       BIT4
  45 #define MCH_ESMRAMC_SM_L2       BIT3
  46 #define MCH_ESMRAMC_TSEG_8MB    BIT2
  47 #define MCH_ESMRAMC_TSEG_2MB    BIT1
  48 #define MCH_ESMRAMC_TSEG_1MB    0
  49 #define MCH_ESMRAMC_TSEG_MASK   (BIT2 | BIT1)
  50 #define MCH_ESMRAMC_T_EN        BIT0
  51
  52 #define MCH_GBSM              0xA4
  53 #define MCH_GBSM_MB_SHIFT       20
  54
  55 #define MCH_BGSM              0xA8
  56 #define MCH_BGSM_MB_SHIFT       20
  57
  58 #define MCH_TSEGMB            0xAC
  59 #define MCH_TSEGMB_MB_SHIFT     20
  60
  61 #define MCH_TOLUD             0xB0
  62 #define MCH_TOLUD_MB_SHIFT      4
  63
  64 //
  65 // B/D/F/Type: 0/0x1f/0/PCI
  66 //
  67 #define POWER_MGMT_REGISTER_Q35(Offset) \
  68   PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))
  69
  70 #define ICH9_PMBASE               0x40
  71 #define ICH9_PMBASE_MASK            (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
  72                                      BIT10 | BIT9  | BIT8  | BIT7)
  73
  74 #define ICH9_ACPI_CNTL            0x44
  75 #define ICH9_ACPI_CNTL_ACPI_EN      BIT7
  76
  77 #define ICH9_GEN_PMCON_1          0xA0
  78 #define ICH9_GEN_PMCON_1_SMI_LOCK   BIT4
  79
  80 //
  81 // IO ports
  82 //
  83 #define ICH9_APM_CNT 0xB2
  84 #define ICH9_APM_STS 0xB3
  85
  86 //
  87 // IO ports relative to PMBASE
  88 //
  89 #define ICH9_PMBASE_OFS_SMI_EN 0x30
  90 #define ICH9_SMI_EN_APMC_EN      BIT5
  91 #define ICH9_SMI_EN_GBL_SMI_EN   BIT0
  92
  93 #endif