OvmfPkg/Include/IndustryStandard/X64Paging.h

   1 /** @file
   2   X64 Long Mode Virtual Memory Management Definitions
   3
   4   References:
   5     1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel
   6     2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
   7     3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
   8     4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
   9
  10 Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
  11 This program and the accompanying materials
  12 are licensed and made available under the terms and conditions of the BSD License
  13 which accompanies this distribution.  The full text of the license may be found at
  14 http://opensource.org/licenses/bsd-license.php
  15
  16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  18
  19 **/
  20 #ifndef _X64_PAGING_H_
  21 #define _X64_PAGING_H_
  22
  23 #pragma pack(1)
  24
  25 //
  26 // Page-Map Level-4 Offset (PML4) and
  27 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
  28 //
  29
  30 typedef union {
  31   struct {
  32     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  33     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  34     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  35     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  36     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  37     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  38     UINT64  Reserved:1;               // Reserved
  39     UINT64  MustBeZero:2;             // Must Be Zero
  40     UINT64  Available:3;              // Available for use by system software
  41     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  42     UINT64  AvabilableHigh:11;        // Available for use by system software
  43     UINT64  Nx:1;                     // No Execute bit
  44   } Bits;
  45   UINT64    Uint64;
  46 } X64_PAGE_MAP_AND_DIRECTORY_POINTER;
  47
  48 //
  49 // Page Table Entry 2MB
  50 //
  51 typedef union {
  52   struct {
  53     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  54     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  55     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  56     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  57     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  58     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  59     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
  60     UINT64  MustBe1:1;                // Must be 1
  61     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
  62     UINT64  Available:3;              // Available for use by system software
  63     UINT64  PAT:1;                    //
  64     UINT64  MustBeZero:8;             // Must be zero;
  65     UINT64  PageTableBaseAddress:31;  // Page Table Base Address
  66     UINT64  AvabilableHigh:11;        // Available for use by system software
  67     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
  68   } Bits;
  69   UINT64    Uint64;
  70 } X64_PAGE_TABLE_ENTRY;
  71
  72 //
  73 // Page Table Entry 1GB
  74 //
  75 typedef union {
  76   struct {
  77     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  78     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  79     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  80     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  81     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  82     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  83     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
  84     UINT64  MustBe1:1;                // Must be 1
  85     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
  86     UINT64  Available:3;              // Available for use by system software
  87     UINT64  PAT:1;                    //
  88     UINT64  MustBeZero:17;            // Must be zero;
  89     UINT64  PageTableBaseAddress:22;  // Page Table Base Address
  90     UINT64  AvabilableHigh:11;        // Available for use by system software
  91     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
  92   } Bits;
  93   UINT64    Uint64;
  94 } X64_PAGE_TABLE_1G_ENTRY;
  95
  96 #pragma pack()
  97
  98 #endif
  99