OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c

   1 /** @file
   2   Provide constructor and GetTick for BaseRom instance of ACPI Timer Library
   3
   4   Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8 **/
   9
  10 #include <Library/DebugLib.h>
  11 #include <Library/IoLib.h>
  12 #include <Library/PciLib.h>
  13 #include <OvmfPlatforms.h>
  14
  15 /**
  16   The constructor function enables ACPI IO space.
  17
  18   If ACPI I/O space not enabled, this function will enable it.
  19   It will always return RETURN_SUCCESS.
  20
  21   @retval EFI_SUCCESS   The constructor always returns RETURN_SUCCESS.
  22
  23 **/
  24 RETURN_STATUS
  25 EFIAPI
  26 AcpiTimerLibConstructor (
  27   VOID
  28   )
  29 {
  30   UINT16  HostBridgeDevId;
  31   UINTN   Pmba;
  32   UINT32  PmbaAndVal;
  33   UINT32  PmbaOrVal;
  34   UINTN   AcpiCtlReg;
  35   UINT8   AcpiEnBit;
  36
  37   //
  38   // Query Host Bridge DID to determine platform type
  39   //
  40   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
  41   switch (HostBridgeDevId) {
  42     case INTEL_82441_DEVICE_ID:
  43       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
  44       PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
  45       PmbaOrVal  = PIIX4_PMBA_VALUE;
  46       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
  47       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
  48       break;
  49     case INTEL_Q35_MCH_DEVICE_ID:
  50       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
  51       PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
  52       PmbaOrVal  = ICH9_PMBASE_VALUE;
  53       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
  54       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
  55       break;
  56     default:
  57       DEBUG ((
  58         DEBUG_ERROR,
  59         "%a: Unknown Host Bridge Device ID: 0x%04x\n",
  60         __FUNCTION__,
  61         HostBridgeDevId
  62         ));
  63       ASSERT (FALSE);
  64       return RETURN_UNSUPPORTED;
  65   }
  66
  67   //
  68   // Check to see if the Power Management Base Address is already enabled
  69   //
  70   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
  71     //
  72     // If the Power Management Base Address is not programmed,
  73     // then program it now.
  74     //
  75     PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
  76
  77     //
  78     // Enable PMBA I/O port decodes
  79     //
  80     PciOr8 (AcpiCtlReg, AcpiEnBit);
  81   }
  82
  83   return RETURN_SUCCESS;
  84 }
  85
  86 /**
  87   Internal function to read the current tick counter of ACPI.
  88
  89   Dynamically compute the address of the ACPI tick counter based on the
  90   properties of the underlying platform, to avoid relying on global variables.
  91
  92   @return The tick counter read.
  93
  94 **/
  95 UINT32
  96 InternalAcpiGetTimerTick (
  97   VOID
  98   )
  99 {
 100   UINT16  HostBridgeDevId;
 101   UINTN   Pmba;
 102
 103   //
 104   // Query Host Bridge DID to determine platform type
 105   //
 106   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 107   switch (HostBridgeDevId) {
 108     case INTEL_82441_DEVICE_ID:
 109       Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 110       break;
 111     case INTEL_Q35_MCH_DEVICE_ID:
 112       Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 113       break;
 114     default:
 115       DEBUG ((
 116         DEBUG_ERROR,
 117         "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 118         __FUNCTION__,
 119         HostBridgeDevId
 120         ));
 121       ASSERT (FALSE);
 122       return 0;
 123   }
 124
 125   //
 126   //   Read PMBA to read and return the current ACPI timer value.
 127   //
 128   return IoRead32 ((PciRead32 (Pmba) & ~PMBA_RTE) + ACPI_TIMER_OFFSET);
 129 }