3 Virtual Memory Management Services to set or clear the memory encryption bit
5 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
6 Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.<BR>
8 SPDX-License-Identifier: BSD-2-Clause-Patent
10 Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
14 #include <Library/CpuLib.h>
15 #include <Library/MemEncryptSevLib.h>
16 #include <Register/Amd/Cpuid.h>
17 #include <Register/Cpuid.h>
19 #include "VirtualMemory.h"
21 STATIC BOOLEAN mAddressEncMaskChecked
= FALSE
;
22 STATIC UINT64 mAddressEncMask
;
23 STATIC PAGE_TABLE_POOL
*mPageTablePool
= NULL
;
31 Return the pagetable memory encryption mask.
33 @return The pagetable memory encryption mask.
38 InternalGetMemEncryptionAddressMask (
42 UINT64 EncryptionMask
;
44 if (mAddressEncMaskChecked
) {
45 return mAddressEncMask
;
48 EncryptionMask
= MemEncryptSevGetEncryptionMask ();
50 mAddressEncMask
= EncryptionMask
& PAGING_1G_ADDRESS_MASK_64
;
51 mAddressEncMaskChecked
= TRUE
;
53 return mAddressEncMask
;
57 Initialize a buffer pool for page table use only.
59 To reduce the potential split operation on page table, the pages reserved for
60 page table should be allocated in the times of PAGE_TABLE_POOL_UNIT_PAGES and
61 at the boundary of PAGE_TABLE_POOL_ALIGNMENT. So the page pool is always
62 initialized with number of pages greater than or equal to the given
65 Once the pages in the pool are used up, this method should be called again to
66 reserve at least another PAGE_TABLE_POOL_UNIT_PAGES. Usually this won't
67 happen often in practice.
69 @param[in] PoolPages The least page number of the pool to be created.
71 @retval TRUE The pool is initialized successfully.
72 @retval FALSE The memory is out of resource.
76 InitializePageTablePool (
83 // Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one page for
86 PoolPages
+= 1; // Add one page for header.
87 PoolPages
= ((PoolPages
- 1) / PAGE_TABLE_POOL_UNIT_PAGES
+ 1) *
88 PAGE_TABLE_POOL_UNIT_PAGES
;
89 Buffer
= AllocateAlignedPages (PoolPages
, PAGE_TABLE_POOL_ALIGNMENT
);
91 DEBUG ((DEBUG_ERROR
, "ERROR: Out of aligned pages\r\n"));
96 // Link all pools into a list for easier track later.
98 if (mPageTablePool
== NULL
) {
99 mPageTablePool
= Buffer
;
100 mPageTablePool
->NextPool
= mPageTablePool
;
102 ((PAGE_TABLE_POOL
*)Buffer
)->NextPool
= mPageTablePool
->NextPool
;
103 mPageTablePool
->NextPool
= Buffer
;
104 mPageTablePool
= Buffer
;
108 // Reserve one page for pool header.
110 mPageTablePool
->FreePages
= PoolPages
- 1;
111 mPageTablePool
->Offset
= EFI_PAGES_TO_SIZE (1);
117 This API provides a way to allocate memory for page table.
119 This API can be called more than once to allocate memory for page tables.
121 Allocates the number of 4KB pages and returns a pointer to the allocated
122 buffer. The buffer returned is aligned on a 4KB boundary.
124 If Pages is 0, then NULL is returned.
125 If there is not enough memory remaining to satisfy the request, then NULL is
128 @param Pages The number of 4 KB pages to allocate.
130 @return A pointer to the allocated buffer or NULL if allocation fails.
136 AllocatePageTableMemory (
147 // Renew the pool if necessary.
149 if (mPageTablePool
== NULL
||
150 Pages
> mPageTablePool
->FreePages
) {
151 if (!InitializePageTablePool (Pages
)) {
156 Buffer
= (UINT8
*)mPageTablePool
+ mPageTablePool
->Offset
;
158 mPageTablePool
->Offset
+= EFI_PAGES_TO_SIZE (Pages
);
159 mPageTablePool
->FreePages
-= Pages
;
163 "%a:%a: Buffer=0x%Lx Pages=%ld\n",
177 @param[in] PhysicalAddress Start physical address the 2M page
179 @param[in, out] PageEntry2M Pointer to 2M page entry.
180 @param[in] StackBase Stack base address.
181 @param[in] StackSize Stack size.
187 IN PHYSICAL_ADDRESS PhysicalAddress
,
188 IN OUT UINT64
*PageEntry2M
,
189 IN PHYSICAL_ADDRESS StackBase
,
193 PHYSICAL_ADDRESS PhysicalAddress4K
;
194 UINTN IndexOfPageTableEntries
;
195 PAGE_TABLE_4K_ENTRY
*PageTableEntry
;
196 PAGE_TABLE_4K_ENTRY
*PageTableEntry1
;
197 UINT64 AddressEncMask
;
199 PageTableEntry
= AllocatePageTableMemory(1);
201 PageTableEntry1
= PageTableEntry
;
203 AddressEncMask
= InternalGetMemEncryptionAddressMask ();
205 ASSERT (PageTableEntry
!= NULL
);
206 ASSERT (*PageEntry2M
& AddressEncMask
);
208 PhysicalAddress4K
= PhysicalAddress
;
209 for (IndexOfPageTableEntries
= 0;
210 IndexOfPageTableEntries
< 512;
211 (IndexOfPageTableEntries
++,
213 PhysicalAddress4K
+= SIZE_4KB
)) {
215 // Fill in the Page Table entries
217 PageTableEntry
->Uint64
= (UINT64
) PhysicalAddress4K
| AddressEncMask
;
218 PageTableEntry
->Bits
.ReadWrite
= 1;
219 PageTableEntry
->Bits
.Present
= 1;
220 if ((PhysicalAddress4K
>= StackBase
) &&
221 (PhysicalAddress4K
< StackBase
+ StackSize
)) {
223 // Set Nx bit for stack.
225 PageTableEntry
->Bits
.Nx
= 1;
230 // Fill in 2M page entry.
232 *PageEntry2M
= ((UINT64
)(UINTN
)PageTableEntry1
|
233 IA32_PG_P
| IA32_PG_RW
| AddressEncMask
);
237 Set one page of page table pool memory to be read-only.
239 @param[in] PageTableBase Base address of page table (CR3).
240 @param[in] Address Start address of a page to be set as read-only.
241 @param[in] Level4Paging Level 4 paging flag.
246 SetPageTablePoolReadOnly (
247 IN UINTN PageTableBase
,
248 IN EFI_PHYSICAL_ADDRESS Address
,
249 IN BOOLEAN Level4Paging
254 UINT64 AddressEncMask
;
255 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
257 UINT64
*NewPageTable
;
265 ASSERT (PageTableBase
!= 0);
268 // Since the page table is always from page table pool, which is always
269 // located at the boundary of PcdPageTablePoolAlignment, we just need to
270 // set the whole pool unit to be read-only.
272 Address
= Address
& PAGE_TABLE_POOL_ALIGN_MASK
;
274 LevelShift
[1] = PAGING_L1_ADDRESS_SHIFT
;
275 LevelShift
[2] = PAGING_L2_ADDRESS_SHIFT
;
276 LevelShift
[3] = PAGING_L3_ADDRESS_SHIFT
;
277 LevelShift
[4] = PAGING_L4_ADDRESS_SHIFT
;
279 LevelMask
[1] = PAGING_4K_ADDRESS_MASK_64
;
280 LevelMask
[2] = PAGING_2M_ADDRESS_MASK_64
;
281 LevelMask
[3] = PAGING_1G_ADDRESS_MASK_64
;
282 LevelMask
[4] = PAGING_1G_ADDRESS_MASK_64
;
284 LevelSize
[1] = SIZE_4KB
;
285 LevelSize
[2] = SIZE_2MB
;
286 LevelSize
[3] = SIZE_1GB
;
287 LevelSize
[4] = SIZE_512GB
;
289 AddressEncMask
= InternalGetMemEncryptionAddressMask();
290 PageTable
= (UINT64
*)(UINTN
)PageTableBase
;
291 PoolUnitSize
= PAGE_TABLE_POOL_UNIT_SIZE
;
293 for (Level
= (Level4Paging
) ? 4 : 3; Level
> 0; --Level
) {
294 Index
= ((UINTN
)RShiftU64 (Address
, LevelShift
[Level
]));
295 Index
&= PAGING_PAE_INDEX_MASK
;
297 PageAttr
= PageTable
[Index
];
298 if ((PageAttr
& IA32_PG_PS
) == 0) {
300 // Go to next level of table.
302 PageTable
= (UINT64
*)(UINTN
)(PageAttr
& ~AddressEncMask
&
303 PAGING_4K_ADDRESS_MASK_64
);
307 if (PoolUnitSize
>= LevelSize
[Level
]) {
309 // Clear R/W bit if current page granularity is not larger than pool unit
312 if ((PageAttr
& IA32_PG_RW
) != 0) {
313 while (PoolUnitSize
> 0) {
315 // PAGE_TABLE_POOL_UNIT_SIZE and PAGE_TABLE_POOL_ALIGNMENT are fit in
316 // one page (2MB). Then we don't need to update attributes for pages
317 // crossing page directory. ASSERT below is for that purpose.
319 ASSERT (Index
< EFI_PAGE_SIZE
/sizeof (UINT64
));
321 PageTable
[Index
] &= ~(UINT64
)IA32_PG_RW
;
322 PoolUnitSize
-= LevelSize
[Level
];
332 // The smaller granularity of page must be needed.
336 NewPageTable
= AllocatePageTableMemory (1);
337 ASSERT (NewPageTable
!= NULL
);
339 PhysicalAddress
= PageAttr
& LevelMask
[Level
];
341 EntryIndex
< EFI_PAGE_SIZE
/sizeof (UINT64
);
343 NewPageTable
[EntryIndex
] = PhysicalAddress
| AddressEncMask
|
344 IA32_PG_P
| IA32_PG_RW
;
346 NewPageTable
[EntryIndex
] |= IA32_PG_PS
;
348 PhysicalAddress
+= LevelSize
[Level
- 1];
351 PageTable
[Index
] = (UINT64
)(UINTN
)NewPageTable
| AddressEncMask
|
352 IA32_PG_P
| IA32_PG_RW
;
353 PageTable
= NewPageTable
;
359 Prevent the memory pages used for page table from been overwritten.
361 @param[in] PageTableBase Base address of page table (CR3).
362 @param[in] Level4Paging Level 4 paging flag.
367 EnablePageTableProtection (
368 IN UINTN PageTableBase
,
369 IN BOOLEAN Level4Paging
372 PAGE_TABLE_POOL
*HeadPool
;
373 PAGE_TABLE_POOL
*Pool
;
375 EFI_PHYSICAL_ADDRESS Address
;
377 if (mPageTablePool
== NULL
) {
382 // SetPageTablePoolReadOnly might update mPageTablePool. It's safer to
383 // remember original one in advance.
385 HeadPool
= mPageTablePool
;
388 Address
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)Pool
;
389 PoolSize
= Pool
->Offset
+ EFI_PAGES_TO_SIZE (Pool
->FreePages
);
392 // The size of one pool must be multiple of PAGE_TABLE_POOL_UNIT_SIZE,
393 // which is one of page size of the processor (2MB by default). Let's apply
394 // the protection to them one by one.
396 while (PoolSize
> 0) {
397 SetPageTablePoolReadOnly(PageTableBase
, Address
, Level4Paging
);
398 Address
+= PAGE_TABLE_POOL_UNIT_SIZE
;
399 PoolSize
-= PAGE_TABLE_POOL_UNIT_SIZE
;
402 Pool
= Pool
->NextPool
;
403 } while (Pool
!= HeadPool
);
411 @param[in] PhysicalAddress Start physical address the 1G page
413 @param[in, out] PageEntry1G Pointer to 1G page entry.
414 @param[in] StackBase Stack base address.
415 @param[in] StackSize Stack size.
421 IN PHYSICAL_ADDRESS PhysicalAddress
,
422 IN OUT UINT64
*PageEntry1G
,
423 IN PHYSICAL_ADDRESS StackBase
,
427 PHYSICAL_ADDRESS PhysicalAddress2M
;
428 UINTN IndexOfPageDirectoryEntries
;
429 PAGE_TABLE_ENTRY
*PageDirectoryEntry
;
430 UINT64 AddressEncMask
;
432 PageDirectoryEntry
= AllocatePageTableMemory(1);
434 AddressEncMask
= InternalGetMemEncryptionAddressMask ();
435 ASSERT (PageDirectoryEntry
!= NULL
);
436 ASSERT (*PageEntry1G
& AddressEncMask
);
438 // Fill in 1G page entry.
440 *PageEntry1G
= ((UINT64
)(UINTN
)PageDirectoryEntry
|
441 IA32_PG_P
| IA32_PG_RW
| AddressEncMask
);
443 PhysicalAddress2M
= PhysicalAddress
;
444 for (IndexOfPageDirectoryEntries
= 0;
445 IndexOfPageDirectoryEntries
< 512;
446 (IndexOfPageDirectoryEntries
++,
447 PageDirectoryEntry
++,
448 PhysicalAddress2M
+= SIZE_2MB
)) {
449 if ((PhysicalAddress2M
< StackBase
+ StackSize
) &&
450 ((PhysicalAddress2M
+ SIZE_2MB
) > StackBase
)) {
452 // Need to split this 2M page that covers stack range.
456 (UINT64
*)PageDirectoryEntry
,
462 // Fill in the Page Directory entries
464 PageDirectoryEntry
->Uint64
= (UINT64
) PhysicalAddress2M
| AddressEncMask
;
465 PageDirectoryEntry
->Bits
.ReadWrite
= 1;
466 PageDirectoryEntry
->Bits
.Present
= 1;
467 PageDirectoryEntry
->Bits
.MustBe1
= 1;
474 Set or Clear the memory encryption bit
476 @param[in, out] PageTablePointer Page table entry pointer (PTE).
477 @param[in] Mode Set or Clear encryption bit
482 IN OUT UINT64
* PageTablePointer
,
483 IN MAP_RANGE_MODE Mode
486 UINT64 AddressEncMask
;
488 AddressEncMask
= InternalGetMemEncryptionAddressMask ();
490 if (Mode
== SetCBit
) {
491 *PageTablePointer
|= AddressEncMask
;
493 *PageTablePointer
&= ~AddressEncMask
;
499 Check the WP status in CR0 register. This bit is used to lock or unlock write
500 access to pages marked as read-only.
502 @retval TRUE Write protection is enabled.
503 @retval FALSE Write protection is disabled.
507 IsReadOnlyPageWriteProtected (
511 return ((AsmReadCr0 () & BIT16
) != 0);
516 Disable Write Protect on pages marked as read-only.
520 DisableReadOnlyPageWriteProtect (
524 AsmWriteCr0 (AsmReadCr0() & ~BIT16
);
528 Enable Write Protect on pages marked as read-only.
532 EnableReadOnlyPageWriteProtect (
536 AsmWriteCr0 (AsmReadCr0() | BIT16
);
541 This function either sets or clears memory encryption bit for the memory
542 region specified by PhysicalAddress and Length from the current page table
545 The function iterates through the PhysicalAddress one page at a time, and set
546 or clears the memory encryption mask in the page table. If it encounters
547 that a given physical address range is part of large page then it attempts to
548 change the attribute at one go (based on size), otherwise it splits the
549 large pages into smaller (e.g 2M page into 4K pages) and then try to set or
550 clear the encryption bit on the smallest page size.
552 @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use
554 @param[in] PhysicalAddress The physical address that is the start
555 address of a memory region.
556 @param[in] Length The length of memory region
557 @param[in] Mode Set or Clear mode
558 @param[in] CacheFlush Flush the caches before applying the
561 @retval RETURN_SUCCESS The attributes were cleared for the
563 @retval RETURN_INVALID_PARAMETER Number of pages is zero.
564 @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute
571 IN PHYSICAL_ADDRESS Cr3BaseAddress
,
572 IN PHYSICAL_ADDRESS PhysicalAddress
,
574 IN MAP_RANGE_MODE Mode
,
575 IN BOOLEAN CacheFlush
578 PAGE_MAP_AND_DIRECTORY_POINTER
*PageMapLevel4Entry
;
579 PAGE_MAP_AND_DIRECTORY_POINTER
*PageUpperDirectoryPointerEntry
;
580 PAGE_MAP_AND_DIRECTORY_POINTER
*PageDirectoryPointerEntry
;
581 PAGE_TABLE_1G_ENTRY
*PageDirectory1GEntry
;
582 PAGE_TABLE_ENTRY
*PageDirectory2MEntry
;
583 PAGE_TABLE_4K_ENTRY
*PageTableEntry
;
585 UINT64 AddressEncMask
;
587 RETURN_STATUS Status
;
590 // Set PageMapLevel4Entry to suppress incorrect compiler/analyzer warnings.
592 PageMapLevel4Entry
= NULL
;
596 "%a:%a: Cr3Base=0x%Lx Physical=0x%Lx Length=0x%Lx Mode=%a CacheFlush=%u\n",
602 (Mode
== SetCBit
) ? "Encrypt" : "Decrypt",
607 // Check if we have a valid memory encryption mask
609 AddressEncMask
= InternalGetMemEncryptionAddressMask ();
610 if (!AddressEncMask
) {
611 return RETURN_ACCESS_DENIED
;
614 PgTableMask
= AddressEncMask
| EFI_PAGE_MASK
;
617 return RETURN_INVALID_PARAMETER
;
621 // We are going to change the memory encryption attribute from C=0 -> C=1 or
622 // vice versa Flush the caches to ensure that data is written into memory
623 // with correct C-bit
626 WriteBackInvalidateDataCacheRange((VOID
*) (UINTN
)PhysicalAddress
, Length
);
630 // Make sure that the page table is changeable.
632 IsWpEnabled
= IsReadOnlyPageWriteProtected ();
634 DisableReadOnlyPageWriteProtect ();
637 Status
= EFI_SUCCESS
;
642 // If Cr3BaseAddress is not specified then read the current CR3
644 if (Cr3BaseAddress
== 0) {
645 Cr3BaseAddress
= AsmReadCr3();
648 PageMapLevel4Entry
= (VOID
*) (Cr3BaseAddress
& ~PgTableMask
);
649 PageMapLevel4Entry
+= PML4_OFFSET(PhysicalAddress
);
650 if (!PageMapLevel4Entry
->Bits
.Present
) {
653 "%a:%a: bad PML4 for Physical=0x%Lx\n",
658 Status
= RETURN_NO_MAPPING
;
662 PageDirectory1GEntry
= (VOID
*)(
663 (PageMapLevel4Entry
->Bits
.PageTableBaseAddress
<<
666 PageDirectory1GEntry
+= PDP_OFFSET(PhysicalAddress
);
667 if (!PageDirectory1GEntry
->Bits
.Present
) {
670 "%a:%a: bad PDPE for Physical=0x%Lx\n",
675 Status
= RETURN_NO_MAPPING
;
680 // If the MustBe1 bit is not 1, it's not actually a 1GB entry
682 if (PageDirectory1GEntry
->Bits
.MustBe1
) {
685 // If we have at least 1GB to go, we can just update this entry
687 if ((PhysicalAddress
& (BIT30
- 1)) == 0 && Length
>= BIT30
) {
688 SetOrClearCBit(&PageDirectory1GEntry
->Uint64
, Mode
);
691 "%a:%a: updated 1GB entry for Physical=0x%Lx\n",
696 PhysicalAddress
+= BIT30
;
700 // We must split the page
704 "%a:%a: splitting 1GB page for Physical=0x%Lx\n",
710 (UINT64
)PageDirectory1GEntry
->Bits
.PageTableBaseAddress
<< 30,
711 (UINT64
*)PageDirectory1GEntry
,
721 PageUpperDirectoryPointerEntry
=
722 (PAGE_MAP_AND_DIRECTORY_POINTER
*)PageDirectory1GEntry
;
723 PageDirectory2MEntry
=
725 (PageUpperDirectoryPointerEntry
->Bits
.PageTableBaseAddress
<<
728 PageDirectory2MEntry
+= PDE_OFFSET(PhysicalAddress
);
729 if (!PageDirectory2MEntry
->Bits
.Present
) {
732 "%a:%a: bad PDE for Physical=0x%Lx\n",
737 Status
= RETURN_NO_MAPPING
;
741 // If the MustBe1 bit is not a 1, it's not a 2MB entry
743 if (PageDirectory2MEntry
->Bits
.MustBe1
) {
746 // If we have at least 2MB left to go, we can just update this entry
748 if ((PhysicalAddress
& (BIT21
-1)) == 0 && Length
>= BIT21
) {
749 SetOrClearCBit (&PageDirectory2MEntry
->Uint64
, Mode
);
750 PhysicalAddress
+= BIT21
;
754 // We must split up this page into 4K pages
758 "%a:%a: splitting 2MB page for Physical=0x%Lx\n",
764 (UINT64
)PageDirectory2MEntry
->Bits
.PageTableBaseAddress
<< 21,
765 (UINT64
*)PageDirectory2MEntry
,
772 PageDirectoryPointerEntry
=
773 (PAGE_MAP_AND_DIRECTORY_POINTER
*)PageDirectory2MEntry
;
776 (PageDirectoryPointerEntry
->Bits
.PageTableBaseAddress
<<
779 PageTableEntry
+= PTE_OFFSET(PhysicalAddress
);
780 if (!PageTableEntry
->Bits
.Present
) {
783 "%a:%a: bad PTE for Physical=0x%Lx\n",
788 Status
= RETURN_NO_MAPPING
;
791 SetOrClearCBit (&PageTableEntry
->Uint64
, Mode
);
792 PhysicalAddress
+= EFI_PAGE_SIZE
;
793 Length
-= EFI_PAGE_SIZE
;
799 // Protect the page table by marking the memory used for page table to be
803 EnablePageTableProtection ((UINTN
)PageMapLevel4Entry
, TRUE
);
813 // Restore page table write protection, if any.
816 EnableReadOnlyPageWriteProtect ();
823 This function clears memory encryption bit for the memory region specified by
824 PhysicalAddress and Length from the current page table context.
826 @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use
828 @param[in] PhysicalAddress The physical address that is the start
829 address of a memory region.
830 @param[in] Length The length of memory region
831 @param[in] Flush Flush the caches before applying the
834 @retval RETURN_SUCCESS The attributes were cleared for the
836 @retval RETURN_INVALID_PARAMETER Number of pages is zero.
837 @retval RETURN_UNSUPPORTED Clearing the memory encyrption attribute
842 InternalMemEncryptSevSetMemoryDecrypted (
843 IN PHYSICAL_ADDRESS Cr3BaseAddress
,
844 IN PHYSICAL_ADDRESS PhysicalAddress
,
850 return SetMemoryEncDec (
860 This function sets memory encryption bit for the memory region specified by
861 PhysicalAddress and Length from the current page table context.
863 @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use
865 @param[in] PhysicalAddress The physical address that is the start
866 address of a memory region.
867 @param[in] Length The length of memory region
868 @param[in] Flush Flush the caches before applying the
871 @retval RETURN_SUCCESS The attributes were set for the memory
873 @retval RETURN_INVALID_PARAMETER Number of pages is zero.
874 @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute
879 InternalMemEncryptSevSetMemoryEncrypted (
880 IN PHYSICAL_ADDRESS Cr3BaseAddress
,
881 IN PHYSICAL_ADDRESS PhysicalAddress
,
886 return SetMemoryEncDec (
896 This function clears memory encryption bit for the MMIO region specified by
897 PhysicalAddress and Length.
899 @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use
901 @param[in] PhysicalAddress The physical address that is the start
902 address of a MMIO region.
903 @param[in] Length The length of memory region
905 @retval RETURN_SUCCESS The attributes were cleared for the
907 @retval RETURN_INVALID_PARAMETER Length is zero.
908 @retval RETURN_UNSUPPORTED Clearing the memory encyrption attribute
913 InternalMemEncryptSevClearMmioPageEncMask (
914 IN PHYSICAL_ADDRESS Cr3BaseAddress
,
915 IN PHYSICAL_ADDRESS PhysicalAddress
,
919 return SetMemoryEncDec (