2 PCI Library functions that use
3 (a) I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles, layering
4 on top of one PCI CF8 Library instance; or
5 (b) PCI Library functions that use the 256 MB PCI Express MMIO window to
6 perform PCI Configuration cycles, layering on PCI Express Library.
8 The decision is made in the entry point function, based on the OVMF platform
9 type, and then adhered to during the lifetime of the client module.
11 Copyright (C) 2016, Red Hat, Inc.
13 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
14 SPDX-License-Identifier: BSD-2-Clause-Patent
21 #include <IndustryStandard/Q35MchIch9.h>
23 #include <Library/PciLib.h>
24 #include <Library/PciCf8Lib.h>
25 #include <Library/PciExpressLib.h>
26 #include <Library/PcdLib.h>
28 STATIC BOOLEAN mRunningOnQ35
;
32 InitializeConfigAccessMethod (
36 mRunningOnQ35
= (PcdGet16 (PcdOvmfHostBridgePciDevId
) ==
37 INTEL_Q35_MCH_DEVICE_ID
);
38 return RETURN_SUCCESS
;
42 Registers a PCI device so PCI configuration registers may be accessed after
43 SetVirtualAddressMap().
45 Registers the PCI device specified by Address so all the PCI configuration registers
46 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
48 If Address > 0x0FFFFFFF, then ASSERT().
50 @param Address The address that encodes the PCI Bus, Device, Function and
53 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
54 @retval RETURN_UNSUPPORTED An attempt was made to call this function
55 after ExitBootServices().
56 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
57 at runtime could not be mapped.
58 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
59 complete the registration.
64 PciRegisterForRuntimeAccess (
68 return mRunningOnQ35
?
69 PciExpressRegisterForRuntimeAccess (Address
) :
70 PciCf8RegisterForRuntimeAccess (Address
);
74 Reads an 8-bit PCI configuration register.
76 Reads and returns the 8-bit PCI configuration register specified by Address.
77 This function must guarantee that all PCI read and write operations are
80 If Address > 0x0FFFFFFF, then ASSERT().
82 @param Address The address that encodes the PCI Bus, Device, Function and
85 @return The read value from the PCI configuration register.
94 return mRunningOnQ35
?
95 PciExpressRead8 (Address
) :
96 PciCf8Read8 (Address
);
100 Writes an 8-bit PCI configuration register.
102 Writes the 8-bit PCI configuration register specified by Address with the
103 value specified by Value. Value is returned. This function must guarantee
104 that all PCI read and write operations are serialized.
106 If Address > 0x0FFFFFFF, then ASSERT().
108 @param Address The address that encodes the PCI Bus, Device, Function and
110 @param Value The value to write.
112 @return The value written to the PCI configuration register.
122 return mRunningOnQ35
?
123 PciExpressWrite8 (Address
, Value
) :
124 PciCf8Write8 (Address
, Value
);
128 Performs a bitwise OR of an 8-bit PCI configuration register with
131 Reads the 8-bit PCI configuration register specified by Address, performs a
132 bitwise OR between the read result and the value specified by
133 OrData, and writes the result to the 8-bit PCI configuration register
134 specified by Address. The value written to the PCI configuration register is
135 returned. This function must guarantee that all PCI read and write operations
138 If Address > 0x0FFFFFFF, then ASSERT().
140 @param Address The address that encodes the PCI Bus, Device, Function and
142 @param OrData The value to OR with the PCI configuration register.
144 @return The value written back to the PCI configuration register.
154 return mRunningOnQ35
?
155 PciExpressOr8 (Address
, OrData
) :
156 PciCf8Or8 (Address
, OrData
);
160 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
163 Reads the 8-bit PCI configuration register specified by Address, performs a
164 bitwise AND between the read result and the value specified by AndData, and
165 writes the result to the 8-bit PCI configuration register specified by
166 Address. The value written to the PCI configuration register is returned.
167 This function must guarantee that all PCI read and write operations are
170 If Address > 0x0FFFFFFF, then ASSERT().
172 @param Address The address that encodes the PCI Bus, Device, Function and
174 @param AndData The value to AND with the PCI configuration register.
176 @return The value written back to the PCI configuration register.
186 return mRunningOnQ35
?
187 PciExpressAnd8 (Address
, AndData
) :
188 PciCf8And8 (Address
, AndData
);
192 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
193 value, followed a bitwise OR with another 8-bit value.
195 Reads the 8-bit PCI configuration register specified by Address, performs a
196 bitwise AND between the read result and the value specified by AndData,
197 performs a bitwise OR between the result of the AND operation and
198 the value specified by OrData, and writes the result to the 8-bit PCI
199 configuration register specified by Address. The value written to the PCI
200 configuration register is returned. This function must guarantee that all PCI
201 read and write operations are serialized.
203 If Address > 0x0FFFFFFF, then ASSERT().
205 @param Address The address that encodes the PCI Bus, Device, Function and
207 @param AndData The value to AND with the PCI configuration register.
208 @param OrData The value to OR with the result of the AND operation.
210 @return The value written back to the PCI configuration register.
221 return mRunningOnQ35
?
222 PciExpressAndThenOr8 (Address
, AndData
, OrData
) :
223 PciCf8AndThenOr8 (Address
, AndData
, OrData
);
227 Reads a bit field of a PCI configuration register.
229 Reads the bit field in an 8-bit PCI configuration register. The bit field is
230 specified by the StartBit and the EndBit. The value of the bit field is
233 If Address > 0x0FFFFFFF, then ASSERT().
234 If StartBit is greater than 7, then ASSERT().
235 If EndBit is greater than 7, then ASSERT().
236 If EndBit is less than StartBit, then ASSERT().
238 @param Address The PCI configuration register to read.
239 @param StartBit The ordinal of the least significant bit in the bit field.
241 @param EndBit The ordinal of the most significant bit in the bit field.
244 @return The value of the bit field read from the PCI configuration register.
255 return mRunningOnQ35
?
256 PciExpressBitFieldRead8 (Address
, StartBit
, EndBit
) :
257 PciCf8BitFieldRead8 (Address
, StartBit
, EndBit
);
261 Writes a bit field to a PCI configuration register.
263 Writes Value to the bit field of the PCI configuration register. The bit
264 field is specified by the StartBit and the EndBit. All other bits in the
265 destination PCI configuration register are preserved. The new value of the
266 8-bit register is returned.
268 If Address > 0x0FFFFFFF, then ASSERT().
269 If StartBit is greater than 7, then ASSERT().
270 If EndBit is greater than 7, then ASSERT().
271 If EndBit is less than StartBit, then ASSERT().
272 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
274 @param Address The PCI configuration register to write.
275 @param StartBit The ordinal of the least significant bit in the bit field.
277 @param EndBit The ordinal of the most significant bit in the bit field.
279 @param Value The new value of the bit field.
281 @return The value written back to the PCI configuration register.
293 return mRunningOnQ35
?
294 PciExpressBitFieldWrite8 (Address
, StartBit
, EndBit
, Value
) :
295 PciCf8BitFieldWrite8 (Address
, StartBit
, EndBit
, Value
);
299 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
300 writes the result back to the bit field in the 8-bit port.
302 Reads the 8-bit PCI configuration register specified by Address, performs a
303 bitwise OR between the read result and the value specified by
304 OrData, and writes the result to the 8-bit PCI configuration register
305 specified by Address. The value written to the PCI configuration register is
306 returned. This function must guarantee that all PCI read and write operations
307 are serialized. Extra left bits in OrData are stripped.
309 If Address > 0x0FFFFFFF, then ASSERT().
310 If StartBit is greater than 7, then ASSERT().
311 If EndBit is greater than 7, then ASSERT().
312 If EndBit is less than StartBit, then ASSERT().
313 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
315 @param Address The PCI configuration register to write.
316 @param StartBit The ordinal of the least significant bit in the bit field.
318 @param EndBit The ordinal of the most significant bit in the bit field.
320 @param OrData The value to OR with the PCI configuration register.
322 @return The value written back to the PCI configuration register.
334 return mRunningOnQ35
?
335 PciExpressBitFieldOr8 (Address
, StartBit
, EndBit
, OrData
) :
336 PciCf8BitFieldOr8 (Address
, StartBit
, EndBit
, OrData
);
340 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
341 AND, and writes the result back to the bit field in the 8-bit register.
343 Reads the 8-bit PCI configuration register specified by Address, performs a
344 bitwise AND between the read result and the value specified by AndData, and
345 writes the result to the 8-bit PCI configuration register specified by
346 Address. The value written to the PCI configuration register is returned.
347 This function must guarantee that all PCI read and write operations are
348 serialized. Extra left bits in AndData are stripped.
350 If Address > 0x0FFFFFFF, then ASSERT().
351 If StartBit is greater than 7, then ASSERT().
352 If EndBit is greater than 7, then ASSERT().
353 If EndBit is less than StartBit, then ASSERT().
354 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
356 @param Address The PCI configuration register to write.
357 @param StartBit The ordinal of the least significant bit in the bit field.
359 @param EndBit The ordinal of the most significant bit in the bit field.
361 @param AndData The value to AND with the PCI configuration register.
363 @return The value written back to the PCI configuration register.
375 return mRunningOnQ35
?
376 PciExpressBitFieldAnd8 (Address
, StartBit
, EndBit
, AndData
) :
377 PciCf8BitFieldAnd8 (Address
, StartBit
, EndBit
, AndData
);
381 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
382 bitwise OR, and writes the result back to the bit field in the
385 Reads the 8-bit PCI configuration register specified by Address, performs a
386 bitwise AND followed by a bitwise OR between the read result and
387 the value specified by AndData, and writes the result to the 8-bit PCI
388 configuration register specified by Address. The value written to the PCI
389 configuration register is returned. This function must guarantee that all PCI
390 read and write operations are serialized. Extra left bits in both AndData and
393 If Address > 0x0FFFFFFF, then ASSERT().
394 If StartBit is greater than 7, then ASSERT().
395 If EndBit is greater than 7, then ASSERT().
396 If EndBit is less than StartBit, then ASSERT().
397 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
398 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
400 @param Address The PCI configuration register to write.
401 @param StartBit The ordinal of the least significant bit in the bit field.
403 @param EndBit The ordinal of the most significant bit in the bit field.
405 @param AndData The value to AND with the PCI configuration register.
406 @param OrData The value to OR with the result of the AND operation.
408 @return The value written back to the PCI configuration register.
413 PciBitFieldAndThenOr8 (
421 return mRunningOnQ35
?
422 PciExpressBitFieldAndThenOr8 (Address
, StartBit
, EndBit
, AndData
, OrData
) :
423 PciCf8BitFieldAndThenOr8 (Address
, StartBit
, EndBit
, AndData
, OrData
);
427 Reads a 16-bit PCI configuration register.
429 Reads and returns the 16-bit PCI configuration register specified by Address.
430 This function must guarantee that all PCI read and write operations are
433 If Address > 0x0FFFFFFF, then ASSERT().
434 If Address is not aligned on a 16-bit boundary, then ASSERT().
436 @param Address The address that encodes the PCI Bus, Device, Function and
439 @return The read value from the PCI configuration register.
448 return mRunningOnQ35
?
449 PciExpressRead16 (Address
) :
450 PciCf8Read16 (Address
);
454 Writes a 16-bit PCI configuration register.
456 Writes the 16-bit PCI configuration register specified by Address with the
457 value specified by Value. Value is returned. This function must guarantee
458 that all PCI read and write operations are serialized.
460 If Address > 0x0FFFFFFF, then ASSERT().
461 If Address is not aligned on a 16-bit boundary, then ASSERT().
463 @param Address The address that encodes the PCI Bus, Device, Function and
465 @param Value The value to write.
467 @return The value written to the PCI configuration register.
477 return mRunningOnQ35
?
478 PciExpressWrite16 (Address
, Value
) :
479 PciCf8Write16 (Address
, Value
);
483 Performs a bitwise OR of a 16-bit PCI configuration register with
486 Reads the 16-bit PCI configuration register specified by Address, performs a
487 bitwise OR between the read result and the value specified by
488 OrData, and writes the result to the 16-bit PCI configuration register
489 specified by Address. The value written to the PCI configuration register is
490 returned. This function must guarantee that all PCI read and write operations
493 If Address > 0x0FFFFFFF, then ASSERT().
494 If Address is not aligned on a 16-bit boundary, then ASSERT().
496 @param Address The address that encodes the PCI Bus, Device, Function and
498 @param OrData The value to OR with the PCI configuration register.
500 @return The value written back to the PCI configuration register.
510 return mRunningOnQ35
?
511 PciExpressOr16 (Address
, OrData
) :
512 PciCf8Or16 (Address
, OrData
);
516 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
519 Reads the 16-bit PCI configuration register specified by Address, performs a
520 bitwise AND between the read result and the value specified by AndData, and
521 writes the result to the 16-bit PCI configuration register specified by
522 Address. The value written to the PCI configuration register is returned.
523 This function must guarantee that all PCI read and write operations are
526 If Address > 0x0FFFFFFF, then ASSERT().
527 If Address is not aligned on a 16-bit boundary, then ASSERT().
529 @param Address The address that encodes the PCI Bus, Device, Function and
531 @param AndData The value to AND with the PCI configuration register.
533 @return The value written back to the PCI configuration register.
543 return mRunningOnQ35
?
544 PciExpressAnd16 (Address
, AndData
) :
545 PciCf8And16 (Address
, AndData
);
549 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
550 value, followed a bitwise OR with another 16-bit value.
552 Reads the 16-bit PCI configuration register specified by Address, performs a
553 bitwise AND between the read result and the value specified by AndData,
554 performs a bitwise OR between the result of the AND operation and
555 the value specified by OrData, and writes the result to the 16-bit PCI
556 configuration register specified by Address. The value written to the PCI
557 configuration register is returned. This function must guarantee that all PCI
558 read and write operations are serialized.
560 If Address > 0x0FFFFFFF, then ASSERT().
561 If Address is not aligned on a 16-bit boundary, then ASSERT().
563 @param Address The address that encodes the PCI Bus, Device, Function and
565 @param AndData The value to AND with the PCI configuration register.
566 @param OrData The value to OR with the result of the AND operation.
568 @return The value written back to the PCI configuration register.
579 return mRunningOnQ35
?
580 PciExpressAndThenOr16 (Address
, AndData
, OrData
) :
581 PciCf8AndThenOr16 (Address
, AndData
, OrData
);
585 Reads a bit field of a PCI configuration register.
587 Reads the bit field in a 16-bit PCI configuration register. The bit field is
588 specified by the StartBit and the EndBit. The value of the bit field is
591 If Address > 0x0FFFFFFF, then ASSERT().
592 If Address is not aligned on a 16-bit boundary, then ASSERT().
593 If StartBit is greater than 15, then ASSERT().
594 If EndBit is greater than 15, then ASSERT().
595 If EndBit is less than StartBit, then ASSERT().
597 @param Address The PCI configuration register to read.
598 @param StartBit The ordinal of the least significant bit in the bit field.
600 @param EndBit The ordinal of the most significant bit in the bit field.
603 @return The value of the bit field read from the PCI configuration register.
614 return mRunningOnQ35
?
615 PciExpressBitFieldRead16 (Address
, StartBit
, EndBit
) :
616 PciCf8BitFieldRead16 (Address
, StartBit
, EndBit
);
620 Writes a bit field to a PCI configuration register.
622 Writes Value to the bit field of the PCI configuration register. The bit
623 field is specified by the StartBit and the EndBit. All other bits in the
624 destination PCI configuration register are preserved. The new value of the
625 16-bit register is returned.
627 If Address > 0x0FFFFFFF, then ASSERT().
628 If Address is not aligned on a 16-bit boundary, then ASSERT().
629 If StartBit is greater than 15, then ASSERT().
630 If EndBit is greater than 15, then ASSERT().
631 If EndBit is less than StartBit, then ASSERT().
632 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
634 @param Address The PCI configuration register to write.
635 @param StartBit The ordinal of the least significant bit in the bit field.
637 @param EndBit The ordinal of the most significant bit in the bit field.
639 @param Value The new value of the bit field.
641 @return The value written back to the PCI configuration register.
653 return mRunningOnQ35
?
654 PciExpressBitFieldWrite16 (Address
, StartBit
, EndBit
, Value
) :
655 PciCf8BitFieldWrite16 (Address
, StartBit
, EndBit
, Value
);
659 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
660 writes the result back to the bit field in the 16-bit port.
662 Reads the 16-bit PCI configuration register specified by Address, performs a
663 bitwise OR between the read result and the value specified by
664 OrData, and writes the result to the 16-bit PCI configuration register
665 specified by Address. The value written to the PCI configuration register is
666 returned. This function must guarantee that all PCI read and write operations
667 are serialized. Extra left bits in OrData are stripped.
669 If Address > 0x0FFFFFFF, then ASSERT().
670 If Address is not aligned on a 16-bit boundary, then ASSERT().
671 If StartBit is greater than 15, then ASSERT().
672 If EndBit is greater than 15, then ASSERT().
673 If EndBit is less than StartBit, then ASSERT().
674 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
676 @param Address The PCI configuration register to write.
677 @param StartBit The ordinal of the least significant bit in the bit field.
679 @param EndBit The ordinal of the most significant bit in the bit field.
681 @param OrData The value to OR with the PCI configuration register.
683 @return The value written back to the PCI configuration register.
695 return mRunningOnQ35
?
696 PciExpressBitFieldOr16 (Address
, StartBit
, EndBit
, OrData
) :
697 PciCf8BitFieldOr16 (Address
, StartBit
, EndBit
, OrData
);
701 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
702 AND, and writes the result back to the bit field in the 16-bit register.
704 Reads the 16-bit PCI configuration register specified by Address, performs a
705 bitwise AND between the read result and the value specified by AndData, and
706 writes the result to the 16-bit PCI configuration register specified by
707 Address. The value written to the PCI configuration register is returned.
708 This function must guarantee that all PCI read and write operations are
709 serialized. Extra left bits in AndData are stripped.
711 If Address > 0x0FFFFFFF, then ASSERT().
712 If Address is not aligned on a 16-bit boundary, then ASSERT().
713 If StartBit is greater than 15, then ASSERT().
714 If EndBit is greater than 15, then ASSERT().
715 If EndBit is less than StartBit, then ASSERT().
716 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
718 @param Address The PCI configuration register to write.
719 @param StartBit The ordinal of the least significant bit in the bit field.
721 @param EndBit The ordinal of the most significant bit in the bit field.
723 @param AndData The value to AND with the PCI configuration register.
725 @return The value written back to the PCI configuration register.
737 return mRunningOnQ35
?
738 PciExpressBitFieldAnd16 (Address
, StartBit
, EndBit
, AndData
) :
739 PciCf8BitFieldAnd16 (Address
, StartBit
, EndBit
, AndData
);
743 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
744 bitwise OR, and writes the result back to the bit field in the
747 Reads the 16-bit PCI configuration register specified by Address, performs a
748 bitwise AND followed by a bitwise OR between the read result and
749 the value specified by AndData, and writes the result to the 16-bit PCI
750 configuration register specified by Address. The value written to the PCI
751 configuration register is returned. This function must guarantee that all PCI
752 read and write operations are serialized. Extra left bits in both AndData and
755 If Address > 0x0FFFFFFF, then ASSERT().
756 If Address is not aligned on a 16-bit boundary, then ASSERT().
757 If StartBit is greater than 15, then ASSERT().
758 If EndBit is greater than 15, then ASSERT().
759 If EndBit is less than StartBit, then ASSERT().
760 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
761 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
763 @param Address The PCI configuration register to write.
764 @param StartBit The ordinal of the least significant bit in the bit field.
766 @param EndBit The ordinal of the most significant bit in the bit field.
768 @param AndData The value to AND with the PCI configuration register.
769 @param OrData The value to OR with the result of the AND operation.
771 @return The value written back to the PCI configuration register.
776 PciBitFieldAndThenOr16 (
784 return mRunningOnQ35
?
785 PciExpressBitFieldAndThenOr16 (Address
, StartBit
, EndBit
, AndData
, OrData
) :
786 PciCf8BitFieldAndThenOr16 (Address
, StartBit
, EndBit
, AndData
, OrData
);
790 Reads a 32-bit PCI configuration register.
792 Reads and returns the 32-bit PCI configuration register specified by Address.
793 This function must guarantee that all PCI read and write operations are
796 If Address > 0x0FFFFFFF, then ASSERT().
797 If Address is not aligned on a 32-bit boundary, then ASSERT().
799 @param Address The address that encodes the PCI Bus, Device, Function and
802 @return The read value from the PCI configuration register.
811 return mRunningOnQ35
?
812 PciExpressRead32 (Address
) :
813 PciCf8Read32 (Address
);
817 Writes a 32-bit PCI configuration register.
819 Writes the 32-bit PCI configuration register specified by Address with the
820 value specified by Value. Value is returned. This function must guarantee
821 that all PCI read and write operations are serialized.
823 If Address > 0x0FFFFFFF, then ASSERT().
824 If Address is not aligned on a 32-bit boundary, then ASSERT().
826 @param Address The address that encodes the PCI Bus, Device, Function and
828 @param Value The value to write.
830 @return The value written to the PCI configuration register.
840 return mRunningOnQ35
?
841 PciExpressWrite32 (Address
, Value
) :
842 PciCf8Write32 (Address
, Value
);
846 Performs a bitwise OR of a 32-bit PCI configuration register with
849 Reads the 32-bit PCI configuration register specified by Address, performs a
850 bitwise OR between the read result and the value specified by
851 OrData, and writes the result to the 32-bit PCI configuration register
852 specified by Address. The value written to the PCI configuration register is
853 returned. This function must guarantee that all PCI read and write operations
856 If Address > 0x0FFFFFFF, then ASSERT().
857 If Address is not aligned on a 32-bit boundary, then ASSERT().
859 @param Address The address that encodes the PCI Bus, Device, Function and
861 @param OrData The value to OR with the PCI configuration register.
863 @return The value written back to the PCI configuration register.
873 return mRunningOnQ35
?
874 PciExpressOr32 (Address
, OrData
) :
875 PciCf8Or32 (Address
, OrData
);
879 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
882 Reads the 32-bit PCI configuration register specified by Address, performs a
883 bitwise AND between the read result and the value specified by AndData, and
884 writes the result to the 32-bit PCI configuration register specified by
885 Address. The value written to the PCI configuration register is returned.
886 This function must guarantee that all PCI read and write operations are
889 If Address > 0x0FFFFFFF, then ASSERT().
890 If Address is not aligned on a 32-bit boundary, then ASSERT().
892 @param Address The address that encodes the PCI Bus, Device, Function and
894 @param AndData The value to AND with the PCI configuration register.
896 @return The value written back to the PCI configuration register.
906 return mRunningOnQ35
?
907 PciExpressAnd32 (Address
, AndData
) :
908 PciCf8And32 (Address
, AndData
);
912 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
913 value, followed a bitwise OR with another 32-bit value.
915 Reads the 32-bit PCI configuration register specified by Address, performs a
916 bitwise AND between the read result and the value specified by AndData,
917 performs a bitwise OR between the result of the AND operation and
918 the value specified by OrData, and writes the result to the 32-bit PCI
919 configuration register specified by Address. The value written to the PCI
920 configuration register is returned. This function must guarantee that all PCI
921 read and write operations are serialized.
923 If Address > 0x0FFFFFFF, then ASSERT().
924 If Address is not aligned on a 32-bit boundary, then ASSERT().
926 @param Address The address that encodes the PCI Bus, Device, Function and
928 @param AndData The value to AND with the PCI configuration register.
929 @param OrData The value to OR with the result of the AND operation.
931 @return The value written back to the PCI configuration register.
942 return mRunningOnQ35
?
943 PciExpressAndThenOr32 (Address
, AndData
, OrData
) :
944 PciCf8AndThenOr32 (Address
, AndData
, OrData
);
948 Reads a bit field of a PCI configuration register.
950 Reads the bit field in a 32-bit PCI configuration register. The bit field is
951 specified by the StartBit and the EndBit. The value of the bit field is
954 If Address > 0x0FFFFFFF, then ASSERT().
955 If Address is not aligned on a 32-bit boundary, then ASSERT().
956 If StartBit is greater than 31, then ASSERT().
957 If EndBit is greater than 31, then ASSERT().
958 If EndBit is less than StartBit, then ASSERT().
960 @param Address The PCI configuration register to read.
961 @param StartBit The ordinal of the least significant bit in the bit field.
963 @param EndBit The ordinal of the most significant bit in the bit field.
966 @return The value of the bit field read from the PCI configuration register.
977 return mRunningOnQ35
?
978 PciExpressBitFieldRead32 (Address
, StartBit
, EndBit
) :
979 PciCf8BitFieldRead32 (Address
, StartBit
, EndBit
);
983 Writes a bit field to a PCI configuration register.
985 Writes Value to the bit field of the PCI configuration register. The bit
986 field is specified by the StartBit and the EndBit. All other bits in the
987 destination PCI configuration register are preserved. The new value of the
988 32-bit register is returned.
990 If Address > 0x0FFFFFFF, then ASSERT().
991 If Address is not aligned on a 32-bit boundary, then ASSERT().
992 If StartBit is greater than 31, then ASSERT().
993 If EndBit is greater than 31, then ASSERT().
994 If EndBit is less than StartBit, then ASSERT().
995 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
997 @param Address The PCI configuration register to write.
998 @param StartBit The ordinal of the least significant bit in the bit field.
1000 @param EndBit The ordinal of the most significant bit in the bit field.
1002 @param Value The new value of the bit field.
1004 @return The value written back to the PCI configuration register.
1009 PciBitFieldWrite32 (
1016 return mRunningOnQ35
?
1017 PciExpressBitFieldWrite32 (Address
, StartBit
, EndBit
, Value
) :
1018 PciCf8BitFieldWrite32 (Address
, StartBit
, EndBit
, Value
);
1022 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1023 writes the result back to the bit field in the 32-bit port.
1025 Reads the 32-bit PCI configuration register specified by Address, performs a
1026 bitwise OR between the read result and the value specified by
1027 OrData, and writes the result to the 32-bit PCI configuration register
1028 specified by Address. The value written to the PCI configuration register is
1029 returned. This function must guarantee that all PCI read and write operations
1030 are serialized. Extra left bits in OrData are stripped.
1032 If Address > 0x0FFFFFFF, then ASSERT().
1033 If Address is not aligned on a 32-bit boundary, then ASSERT().
1034 If StartBit is greater than 31, then ASSERT().
1035 If EndBit is greater than 31, then ASSERT().
1036 If EndBit is less than StartBit, then ASSERT().
1037 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1039 @param Address The PCI configuration register to write.
1040 @param StartBit The ordinal of the least significant bit in the bit field.
1042 @param EndBit The ordinal of the most significant bit in the bit field.
1044 @param OrData The value to OR with the PCI configuration register.
1046 @return The value written back to the PCI configuration register.
1058 return mRunningOnQ35
?
1059 PciExpressBitFieldOr32 (Address
, StartBit
, EndBit
, OrData
) :
1060 PciCf8BitFieldOr32 (Address
, StartBit
, EndBit
, OrData
);
1064 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1065 AND, and writes the result back to the bit field in the 32-bit register.
1067 Reads the 32-bit PCI configuration register specified by Address, performs a
1068 bitwise AND between the read result and the value specified by AndData, and
1069 writes the result to the 32-bit PCI configuration register specified by
1070 Address. The value written to the PCI configuration register is returned.
1071 This function must guarantee that all PCI read and write operations are
1072 serialized. Extra left bits in AndData are stripped.
1074 If Address > 0x0FFFFFFF, then ASSERT().
1075 If Address is not aligned on a 32-bit boundary, then ASSERT().
1076 If StartBit is greater than 31, then ASSERT().
1077 If EndBit is greater than 31, then ASSERT().
1078 If EndBit is less than StartBit, then ASSERT().
1079 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1081 @param Address The PCI configuration register to write.
1082 @param StartBit The ordinal of the least significant bit in the bit field.
1084 @param EndBit The ordinal of the most significant bit in the bit field.
1086 @param AndData The value to AND with the PCI configuration register.
1088 @return The value written back to the PCI configuration register.
1100 return mRunningOnQ35
?
1101 PciExpressBitFieldAnd32 (Address
, StartBit
, EndBit
, AndData
) :
1102 PciCf8BitFieldAnd32 (Address
, StartBit
, EndBit
, AndData
);
1106 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1107 bitwise OR, and writes the result back to the bit field in the
1110 Reads the 32-bit PCI configuration register specified by Address, performs a
1111 bitwise AND followed by a bitwise OR between the read result and
1112 the value specified by AndData, and writes the result to the 32-bit PCI
1113 configuration register specified by Address. The value written to the PCI
1114 configuration register is returned. This function must guarantee that all PCI
1115 read and write operations are serialized. Extra left bits in both AndData and
1116 OrData are stripped.
1118 If Address > 0x0FFFFFFF, then ASSERT().
1119 If Address is not aligned on a 32-bit boundary, then ASSERT().
1120 If StartBit is greater than 31, then ASSERT().
1121 If EndBit is greater than 31, then ASSERT().
1122 If EndBit is less than StartBit, then ASSERT().
1123 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1124 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1126 @param Address The PCI configuration register to write.
1127 @param StartBit The ordinal of the least significant bit in the bit field.
1129 @param EndBit The ordinal of the most significant bit in the bit field.
1131 @param AndData The value to AND with the PCI configuration register.
1132 @param OrData The value to OR with the result of the AND operation.
1134 @return The value written back to the PCI configuration register.
1139 PciBitFieldAndThenOr32 (
1147 return mRunningOnQ35
?
1148 PciExpressBitFieldAndThenOr32 (Address
, StartBit
, EndBit
, AndData
, OrData
) :
1149 PciCf8BitFieldAndThenOr32 (Address
, StartBit
, EndBit
, AndData
, OrData
);
1153 Reads a range of PCI configuration registers into a caller supplied buffer.
1155 Reads the range of PCI configuration registers specified by StartAddress and
1156 Size into the buffer specified by Buffer. This function only allows the PCI
1157 configuration registers from a single PCI function to be read. Size is
1158 returned. When possible 32-bit PCI configuration read cycles are used to read
1159 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1160 and 16-bit PCI configuration read cycles may be used at the beginning and the
1163 If StartAddress > 0x0FFFFFFF, then ASSERT().
1164 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1165 If Size > 0 and Buffer is NULL, then ASSERT().
1167 @param StartAddress The starting address that encodes the PCI Bus, Device,
1168 Function and Register.
1169 @param Size The size in bytes of the transfer.
1170 @param Buffer The pointer to a buffer receiving the data read.
1178 IN UINTN StartAddress
,
1183 return mRunningOnQ35
?
1184 PciExpressReadBuffer (StartAddress
, Size
, Buffer
) :
1185 PciCf8ReadBuffer (StartAddress
, Size
, Buffer
);
1189 Copies the data in a caller supplied buffer to a specified range of PCI
1190 configuration space.
1192 Writes the range of PCI configuration registers specified by StartAddress and
1193 Size from the buffer specified by Buffer. This function only allows the PCI
1194 configuration registers from a single PCI function to be written. Size is
1195 returned. When possible 32-bit PCI configuration write cycles are used to
1196 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1197 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1198 and the end of the range.
1200 If StartAddress > 0x0FFFFFFF, then ASSERT().
1201 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1202 If Size > 0 and Buffer is NULL, then ASSERT().
1204 @param StartAddress The starting address that encodes the PCI Bus, Device,
1205 Function and Register.
1206 @param Size The size in bytes of the transfer.
1207 @param Buffer The pointer to a buffer containing the data to write.
1209 @return Size written to StartAddress.
1215 IN UINTN StartAddress
,
1220 return mRunningOnQ35
?
1221 PciExpressWriteBuffer (StartAddress
, Size
, Buffer
) :
1222 PciCf8WriteBuffer (StartAddress
, Size
, Buffer
);