OvmfPkg/Library/PciHostBridgeLib/XenSupport.c

   1 /** @file
   2   Scan the entire PCI bus for root bridges to support OVMF above Xen.
   3
   4   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
   5
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9 #include <PiDxe.h>
  10
  11 #include <IndustryStandard/Pci.h>
  12 #include <IndustryStandard/Q35MchIch9.h>
  13
  14 #include <Protocol/PciHostBridgeResourceAllocation.h>
  15 #include <Protocol/PciRootBridgeIo.h>
  16
  17 #include <Library/BaseMemoryLib.h>
  18 #include <Library/DebugLib.h>
  19 #include <Library/MemoryAllocationLib.h>
  20 #include <Library/PciHostBridgeLib.h>
  21 #include <Library/PciLib.h>
  22 #include "PciHostBridge.h"
  23
  24 STATIC
  25 VOID
  26 PcatPciRootBridgeBarExisted (
  27   IN  UINTN                          Address,
  28   OUT UINT32                         *OriginalValue,
  29   OUT UINT32                         *Value
  30   )
  31 {
  32   //
  33   // Preserve the original value
  34   //
  35   *OriginalValue = PciRead32 (Address);
  36
  37   //
  38   // Disable timer interrupt while the BAR is probed
  39   //
  40   DisableInterrupts ();
  41
  42   PciWrite32 (Address, 0xFFFFFFFF);
  43   *Value = PciRead32 (Address);
  44   PciWrite32 (Address, *OriginalValue);
  45
  46   //
  47   // Enable interrupt
  48   //
  49   EnableInterrupts ();
  50 }
  51
  52 STATIC
  53 VOID
  54 PcatPciRootBridgeParseBars (
  55   IN UINT16                         Command,
  56   IN UINTN                          Bus,
  57   IN UINTN                          Device,
  58   IN UINTN                          Function,
  59   IN UINTN                          BarOffsetBase,
  60   IN UINTN                          BarOffsetEnd,
  61   IN PCI_ROOT_BRIDGE_APERTURE       *Io,
  62   IN PCI_ROOT_BRIDGE_APERTURE       *Mem,
  63   IN PCI_ROOT_BRIDGE_APERTURE       *MemAbove4G,
  64   IN PCI_ROOT_BRIDGE_APERTURE       *PMem,
  65   IN PCI_ROOT_BRIDGE_APERTURE       *PMemAbove4G
  66
  67 )
  68 {
  69   UINT32                            OriginalValue;
  70   UINT32                            Value;
  71   UINT32                            OriginalUpperValue;
  72   UINT32                            UpperValue;
  73   UINT64                            Mask;
  74   UINTN                             Offset;
  75   UINT64                            Base;
  76   UINT64                            Length;
  77   UINT64                            Limit;
  78   PCI_ROOT_BRIDGE_APERTURE          *MemAperture;
  79
  80   for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {
  81     PcatPciRootBridgeBarExisted (
  82       PCI_LIB_ADDRESS (Bus, Device, Function, Offset),
  83       &OriginalValue, &Value
  84     );
  85     if (Value == 0) {
  86       continue;
  87     }
  88     if ((Value & BIT0) == BIT0) {
  89       //
  90       // IO Bar
  91       //
  92       if (Command & EFI_PCI_COMMAND_IO_SPACE) {
  93         Mask = 0xfffffffc;
  94         Base = OriginalValue & Mask;
  95         Length = ((~(Value & Mask)) & Mask) + 0x04;
  96         if (!(Value & 0xFFFF0000)) {
  97           Length &= 0x0000FFFF;
  98         }
  99         Limit = Base + Length - 1;
 100
 101         if (Base < Limit) {
 102           if (Io->Base > Base) {
 103             Io->Base = Base;
 104           }
 105           if (Io->Limit < Limit) {
 106             Io->Limit = Limit;
 107           }
 108         }
 109       }
 110     } else {
 111       //
 112       // Mem Bar
 113       //
 114       if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {
 115
 116         Mask = 0xfffffff0;
 117         Base = OriginalValue & Mask;
 118         Length = Value & Mask;
 119
 120         if ((Value & (BIT1 | BIT2)) == 0) {
 121           //
 122           // 32bit
 123           //
 124           Length = ((~Length) + 1) & 0xffffffff;
 125
 126           if ((Value & BIT3) == BIT3) {
 127             MemAperture = PMem;
 128           } else {
 129             MemAperture = Mem;
 130           }
 131         } else {
 132           //
 133           // 64bit
 134           //
 135           Offset += 4;
 136           PcatPciRootBridgeBarExisted (
 137             PCI_LIB_ADDRESS (Bus, Device, Function, Offset),
 138             &OriginalUpperValue,
 139             &UpperValue
 140           );
 141
 142           Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);
 143           Length = Length | LShiftU64 ((UINT64) UpperValue, 32);
 144           Length = (~Length) + 1;
 145
 146           if ((Value & BIT3) == BIT3) {
 147             MemAperture = PMemAbove4G;
 148           } else {
 149             MemAperture = MemAbove4G;
 150           }
 151         }
 152
 153         Limit = Base + Length - 1;
 154         if (Base < Limit) {
 155           if (MemAperture->Base > Base) {
 156             MemAperture->Base = Base;
 157           }
 158           if (MemAperture->Limit < Limit) {
 159             MemAperture->Limit = Limit;
 160           }
 161         }
 162       }
 163     }
 164   }
 165 }
 166
 167 PCI_ROOT_BRIDGE *
 168 ScanForRootBridges (
 169   UINTN      *NumberOfRootBridges
 170   )
 171 {
 172   UINTN      PrimaryBus;
 173   UINTN      SubBus;
 174   UINT8      Device;
 175   UINT8      Function;
 176   UINTN      NumberOfDevices;
 177   UINTN      Address;
 178   PCI_TYPE01 Pci;
 179   UINT64     Attributes;
 180   UINT64     Base;
 181   UINT64     Limit;
 182   UINT64     Value;
 183   PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture;
 184   PCI_ROOT_BRIDGE *RootBridges;
 185   UINTN      BarOffsetEnd;
 186
 187
 188   *NumberOfRootBridges = 0;
 189   RootBridges = NULL;
 190
 191   //
 192   // After scanning all the PCI devices on the PCI root bridge's primary bus,
 193   // update the Primary Bus Number for the next PCI root bridge to be this PCI
 194   // root bridge's subordinate bus number + 1.
 195   //
 196   for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {
 197     SubBus = PrimaryBus;
 198     Attributes = 0;
 199
 200     ZeroMem (&Io, sizeof (Io));
 201     ZeroMem (&Mem, sizeof (Mem));
 202     ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
 203     ZeroMem (&PMem, sizeof (PMem));
 204     ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));
 205     Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;
 206     //
 207     // Scan all the PCI devices on the primary bus of the PCI root bridge
 208     //
 209     for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {
 210
 211       for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {
 212
 213         //
 214         // Compute the PCI configuration address of the PCI device to probe
 215         //
 216         Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0);
 217
 218         //
 219         // Read the Vendor ID from the PCI Configuration Header
 220         //
 221         if (PciRead16 (Address) == MAX_UINT16) {
 222           if (Function == 0) {
 223             //
 224             // If the PCI Configuration Read fails, or a PCI device does not
 225             // exist, then skip this entire PCI device
 226             //
 227             break;
 228           } else {
 229             //
 230             // If PCI function != 0, VendorId == 0xFFFF, we continue to search
 231             // PCI function.
 232             //
 233             continue;
 234           }
 235         }
 236
 237         //
 238         // Read the entire PCI Configuration Header
 239         //
 240         PciReadBuffer (Address, sizeof (Pci), &Pci);
 241
 242         //
 243         // Increment the number of PCI device found on the primary bus of the
 244         // PCI root bridge
 245         //
 246         NumberOfDevices++;
 247
 248         //
 249         // Look for devices with the VGA Palette Snoop enabled in the COMMAND
 250         // register of the PCI Config Header
 251         //
 252         if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {
 253           Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
 254           Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
 255         }
 256
 257         BarOffsetEnd = 0;
 258
 259         //
 260         // PCI-PCI Bridge
 261         //
 262         if (IS_PCI_BRIDGE (&Pci)) {
 263           //
 264           // Get the Bus range that the PPB is decoding
 265           //
 266           if (Pci.Bridge.SubordinateBus > SubBus) {
 267             //
 268             // If the suborinate bus number of the PCI-PCI bridge is greater
 269             // than the PCI root bridge's current subordinate bus number,
 270             // then update the PCI root bridge's subordinate bus number
 271             //
 272             SubBus = Pci.Bridge.SubordinateBus;
 273           }
 274
 275           //
 276           // Get the I/O range that the PPB is decoding
 277           //
 278           Value = Pci.Bridge.IoBase & 0x0f;
 279           Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;
 280           Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;
 281           if (Value == BIT0) {
 282             Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);
 283             Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);
 284           }
 285           if (Base < Limit) {
 286             if (Io.Base > Base) {
 287               Io.Base = Base;
 288             }
 289             if (Io.Limit < Limit) {
 290               Io.Limit = Limit;
 291             }
 292           }
 293
 294           //
 295           // Get the Memory range that the PPB is decoding
 296           //
 297           Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;
 298           Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;
 299           if (Base < Limit) {
 300             if (Mem.Base > Base) {
 301               Mem.Base = Base;
 302             }
 303             if (Mem.Limit < Limit) {
 304               Mem.Limit = Limit;
 305             }
 306           }
 307
 308           //
 309           // Get the Prefetchable Memory range that the PPB is decoding
 310           //
 311           Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;
 312           Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;
 313           Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)
 314                    << 16) | 0xfffff;
 315           MemAperture = &PMem;
 316           if (Value == BIT0) {
 317             Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);
 318             Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);
 319             MemAperture = &PMemAbove4G;
 320           }
 321           if (Base < Limit) {
 322             if (MemAperture->Base > Base) {
 323               MemAperture->Base = Base;
 324             }
 325             if (MemAperture->Limit < Limit) {
 326               MemAperture->Limit = Limit;
 327             }
 328           }
 329
 330           //
 331           // Look at the PPB Configuration for legacy decoding attributes
 332           //
 333           if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)
 334               == EFI_PCI_BRIDGE_CONTROL_ISA) {
 335             Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
 336             Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;
 337             Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
 338           }
 339           if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)
 340               == EFI_PCI_BRIDGE_CONTROL_VGA) {
 341             Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
 342             Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
 343             Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
 344             if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)
 345                 != 0) {
 346               Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
 347               Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;
 348             }
 349           }
 350
 351           BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]);
 352         } else {
 353           //
 354           // Parse the BARs of the PCI device to get what I/O Ranges, Memory
 355           // Ranges, and Prefetchable Memory Ranges the device is decoding
 356           //
 357           if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {
 358             BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]);
 359           }
 360         }
 361
 362         PcatPciRootBridgeParseBars (
 363           Pci.Hdr.Command,
 364           PrimaryBus,
 365           Device,
 366           Function,
 367           OFFSET_OF (PCI_TYPE00, Device.Bar),
 368           BarOffsetEnd,
 369           &Io,
 370           &Mem, &MemAbove4G,
 371           &PMem, &PMemAbove4G
 372         );
 373
 374         //
 375         // See if the PCI device is an IDE controller
 376         //
 377         if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,
 378                        PCI_CLASS_MASS_STORAGE_IDE)) {
 379           if (Pci.Hdr.ClassCode[0] & 0x80) {
 380             Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
 381             Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
 382           }
 383           if (Pci.Hdr.ClassCode[0] & 0x01) {
 384             Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
 385           }
 386           if (Pci.Hdr.ClassCode[0] & 0x04) {
 387             Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
 388           }
 389         }
 390
 391         //
 392         // See if the PCI device is a legacy VGA controller or
 393         // a standard VGA controller
 394         //
 395         if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||
 396             IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)
 397             ) {
 398           Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
 399           Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
 400           Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
 401           Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
 402           Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;
 403         }
 404
 405         //
 406         // See if the PCI Device is a PCI - ISA or PCI - EISA
 407         // or ISA_POSITIVIE_DECODE Bridge device
 408         //
 409         if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {
 410           if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||
 411               Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||
 412               Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {
 413             Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
 414             Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;
 415             Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
 416           }
 417         }
 418
 419         //
 420         // If this device is not a multi function device, then skip the rest
 421         // of this PCI device
 422         //
 423         if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
 424           break;
 425         }
 426       }
 427     }
 428
 429     //
 430     // If at least one PCI device was found on the primary bus of this PCI
 431     // root bridge, then the PCI root bridge exists.
 432     //
 433     if (NumberOfDevices > 0) {
 434       RootBridges = ReallocatePool (
 435         (*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),
 436         (*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),
 437         RootBridges
 438       );
 439       ASSERT (RootBridges != NULL);
 440       InitRootBridge (
 441         Attributes, Attributes, 0,
 442         (UINT8) PrimaryBus, (UINT8) SubBus,
 443         &Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G,
 444         &RootBridges[*NumberOfRootBridges]
 445       );
 446       RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;
 447       //
 448       // Increment the index for the next PCI Root Bridge
 449       //
 450       (*NumberOfRootBridges)++;
 451     }
 452   }
 453
 454   return RootBridges;
 455 }