3 Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
10 #include <Library/BaseLib.h>
11 #include <Library/BaseMemoryLib.h>
12 #include <Library/MemoryAllocationLib.h>
13 #include <Library/DebugLib.h>
14 #include <Protocol/DebugSupport.h>
15 #include <Library/TdxLib.h>
16 #include <IndustryStandard/Tdx.h>
17 #include <Library/PrePiLib.h>
18 #include <Library/PeilessStartupLib.h>
19 #include <Library/PlatformInitLib.h>
20 #include <Library/TdxHelperLib.h>
21 #include <ConfidentialComputingGuestAttr.h>
22 #include <Guid/MemoryTypeInformation.h>
23 #include <OvmfPlatforms.h>
24 #include "PeilessStartupInternal.h"
26 #define GET_GPAW_INIT_STATE(INFO) ((UINT8) ((INFO) & 0x3f))
28 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation
[] = {
29 { EfiACPIMemoryNVS
, 0x004 },
30 { EfiACPIReclaimMemory
, 0x008 },
31 { EfiReservedMemoryType
, 0x004 },
32 { EfiRuntimeServicesData
, 0x024 },
33 { EfiRuntimeServicesCode
, 0x030 },
34 { EfiBootServicesCode
, 0x180 },
35 { EfiBootServicesData
, 0xF00 },
36 { EfiMaxMemoryType
, 0x000 }
42 EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
47 DEBUG ((DEBUG_INFO
, "InitializePlatform in Pei-less boot\n"));
48 PlatformDebugDumpCmos ();
50 PlatformInfoHob
->DefaultMaxCpuNumber
= 64;
51 PlatformInfoHob
->PcdPciMmio64Size
= 0x800000000;
53 PlatformInfoHob
->HostBridgeDevId
= PciRead16 (OVMF_HOSTBRIDGE_DID
);
54 DEBUG ((DEBUG_INFO
, "HostBridgeDeviceId = 0x%x\n", PlatformInfoHob
->HostBridgeDevId
));
56 PlatformAddressWidthInitialization (PlatformInfoHob
);
59 "PhysMemAddressWidth=0x%x, Pci64Base=0x%llx, Pci64Size=0x%llx\n",
60 PlatformInfoHob
->PhysMemAddressWidth
,
61 PlatformInfoHob
->PcdPciMmio64Base
,
62 PlatformInfoHob
->PcdPciMmio64Size
65 PlatformMaxCpuCountInitialization (PlatformInfoHob
);
68 "MaxCpuCount=%d, BootCpuCount=%d\n",
69 PlatformInfoHob
->PcdCpuMaxLogicalProcessorNumber
,
70 PlatformInfoHob
->PcdCpuBootLogicalProcessorNumber
73 PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
);
74 PlatformQemuUc32BaseInitialization (PlatformInfoHob
);
77 "Uc32Base = 0x%x, Uc32Size = 0x%x, LowerMemorySize = 0x%x\n",
78 PlatformInfoHob
->Uc32Base
,
79 PlatformInfoHob
->Uc32Size
,
80 PlatformInfoHob
->LowMemory
83 VariableStore
= PlatformReserveEmuVariableNvStore ();
84 PlatformInfoHob
->PcdEmuVariableNvStoreReserved
= (UINT64
)(UINTN
)VariableStore
;
85 #ifdef SECURE_BOOT_FEATURE_ENABLED
86 PlatformInitEmuVariableNvStore (VariableStore
);
90 PlatformTdxPublishRamRegions ();
92 PlatformQemuInitializeRam (PlatformInfoHob
);
93 PlatformQemuInitializeRamForS3 (PlatformInfoHob
);
97 // Create Memory Type Information HOB
100 &gEfiMemoryTypeInformationGuid
,
101 mDefaultMemoryTypeInformation
,
102 sizeof (mDefaultMemoryTypeInformation
)
105 PlatformMemMapInitialization (PlatformInfoHob
);
107 PlatformNoexecDxeInitialization (PlatformInfoHob
);
109 if (TdIsEnabled ()) {
110 PlatformInfoHob
->PcdConfidentialComputingGuestAttr
= CCAttrIntelTdx
;
111 PlatformInfoHob
->PcdTdxSharedBitMask
= TdSharedPageMask ();
112 PlatformInfoHob
->PcdSetNxForStack
= TRUE
;
115 PlatformMiscInitialization (PlatformInfoHob
);
121 * This function brings up the Tdx guest from SEC phase to DXE phase.
122 * PEI phase is skipped because most of the components in PEI phase
123 * is not needed for Tdx guest, for example, MP Services, TPM etc.
124 * In this way, the attack surfaces are reduced as much as possible.
126 * @param Context The pointer to the SecCoreData
127 * @return VOID This function never returns
135 EFI_SEC_PEI_HAND_OFF
*SecCoreData
;
136 EFI_FIRMWARE_VOLUME_HEADER
*BootFv
;
138 EFI_HOB_PLATFORM_INFO PlatformInfoHob
;
141 TD_RETURN_DATA TdReturnData
;
144 Status
= EFI_SUCCESS
;
147 SecCoreData
= (EFI_SEC_PEI_HAND_OFF
*)Context
;
149 ZeroMem (&PlatformInfoHob
, sizeof (PlatformInfoHob
));
151 if (TdIsEnabled ()) {
152 VmmHobList
= (VOID
*)(UINTN
)FixedPcdGet32 (PcdOvmfSecGhcbBase
);
153 Status
= TdCall (TDCALL_TDINFO
, 0, 0, 0, &TdReturnData
);
154 ASSERT (Status
== EFI_SUCCESS
);
158 "Tdx started with(Hob: 0x%x, Gpaw: 0x%x, Cpus: %d)\n",
159 (UINT32
)(UINTN
)VmmHobList
,
160 GET_GPAW_INIT_STATE (TdReturnData
.TdInfo
.Gpaw
),
161 TdReturnData
.TdInfo
.NumVcpus
164 Status
= ConstructFwHobList (VmmHobList
);
166 DEBUG ((DEBUG_INFO
, "Ovmf started\n"));
167 Status
= ConstructSecHobList ();
170 if (EFI_ERROR (Status
)) {
175 DEBUG ((DEBUG_INFO
, "HobList: %p\n", GetHobList ()));
177 if (TdIsEnabled ()) {
181 Status
= TdxHelperMeasureTdHob ();
182 if (EFI_ERROR (Status
)) {
190 Status
= TdxHelperMeasureCfvImage ();
191 if (EFI_ERROR (Status
)) {
197 // Build GuidHob for tdx measurement
199 Status
= TdxHelperBuildGuidHobForTdxMeasurement ();
200 if (EFI_ERROR (Status
)) {
207 // Initialize the Platform
209 Status
= InitializePlatform (&PlatformInfoHob
);
210 if (EFI_ERROR (Status
)) {
215 BuildGuidDataHob (&gUefiOvmfPkgPlatformInfoGuid
, &PlatformInfoHob
, sizeof (EFI_HOB_PLATFORM_INFO
));
220 BootFv
= (EFI_FIRMWARE_VOLUME_HEADER
*)SecCoreData
->BootFirmwareVolumeBase
;
221 BuildFvHob ((UINTN
)BootFv
, BootFv
->FvLength
);
226 DxeCodeBase
= PcdGet32 (PcdBfvBase
);
227 DxeCodeSize
= PcdGet32 (PcdBfvRawDataSize
) - (UINT32
)BootFv
->FvLength
;
228 BuildFvHob (DxeCodeBase
, DxeCodeSize
);
230 DEBUG ((DEBUG_INFO
, "SecFv : %p, 0x%x\n", BootFv
, BootFv
->FvLength
));
231 DEBUG ((DEBUG_INFO
, "DxeFv : %x, 0x%x\n", DxeCodeBase
, DxeCodeSize
));
233 BuildStackHob ((UINTN
)SecCoreData
->StackBase
, SecCoreData
->StackSize
<<= 1);
235 BuildResourceDescriptorHob (
236 EFI_RESOURCE_SYSTEM_MEMORY
,
237 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
238 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
239 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
240 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
241 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
242 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
|
243 EFI_RESOURCE_ATTRIBUTE_TESTED
,
244 (UINT64
)SecCoreData
->TemporaryRamBase
,
245 (UINT64
)SecCoreData
->TemporaryRamSize
249 // Load the DXE Core and transfer control to it.
250 // Only DxeFV is in the compressed section.
252 Status
= DxeLoadCore (1);
255 // Never arrive here.