2 Memory Detection for Virtual Machines.
4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
14 // The package level header files this module uses
16 #include <IndustryStandard/E820.h>
17 #include <IndustryStandard/I440FxPiix4.h>
18 #include <IndustryStandard/Q35MchIch9.h>
19 #include <IndustryStandard/CloudHv.h>
20 #include <IndustryStandard/Xen/arch-x86/hvm/start_info.h>
22 #include <Register/Intel/SmramSaveStateMap.h>
25 // The Library classes this module consumes
27 #include <Library/BaseLib.h>
28 #include <Library/BaseMemoryLib.h>
29 #include <Library/CcProbeLib.h>
30 #include <Library/DebugLib.h>
31 #include <Library/HardwareInfoLib.h>
32 #include <Library/HobLib.h>
33 #include <Library/IoLib.h>
34 #include <Library/MemEncryptSevLib.h>
35 #include <Library/PcdLib.h>
36 #include <Library/PciLib.h>
37 #include <Library/PeimEntryPoint.h>
38 #include <Library/ResourcePublicationLib.h>
39 #include <Library/MtrrLib.h>
40 #include <Library/QemuFwCfgLib.h>
41 #include <Library/QemuFwCfgSimpleParserLib.h>
42 #include <Library/TdxLib.h>
44 #include <Library/PlatformInitLib.h>
46 #define MEGABYTE_SHIFT 20
50 PlatformQemuUc32BaseInitialization (
51 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
54 UINT32 LowerMemorySize
;
56 if (PlatformInfoHob
->HostBridgeDevId
== 0xffff /* microvm */) {
60 if (PlatformInfoHob
->HostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
61 LowerMemorySize
= PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
);
62 ASSERT (PcdGet64 (PcdPciExpressBaseAddress
) <= MAX_UINT32
);
63 ASSERT (PcdGet64 (PcdPciExpressBaseAddress
) >= LowerMemorySize
);
65 if (LowerMemorySize
<= BASE_2GB
) {
66 // Newer qemu with gigabyte aligned memory,
67 // 32-bit pci mmio window is 2G -> 4G then.
68 PlatformInfoHob
->Uc32Base
= BASE_2GB
;
71 // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
72 // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for
73 // setting PcdPciExpressBaseAddress such that describing the
74 // [PcdPciExpressBaseAddress, 4GB) range require a very small number of
75 // variable MTRRs (preferably 1 or 2).
77 PlatformInfoHob
->Uc32Base
= (UINT32
)PcdGet64 (PcdPciExpressBaseAddress
);
83 if (PlatformInfoHob
->HostBridgeDevId
== CLOUDHV_DEVICE_ID
) {
84 PlatformInfoHob
->Uc32Size
= CLOUDHV_MMIO_HOLE_SIZE
;
85 PlatformInfoHob
->Uc32Base
= CLOUDHV_MMIO_HOLE_ADDRESS
;
89 ASSERT (PlatformInfoHob
->HostBridgeDevId
== INTEL_82441_DEVICE_ID
);
91 // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one
92 // variable MTRR suffices by truncating the size to a whole power of two,
93 // while keeping the end affixed to 4GB. This will round the base up.
95 LowerMemorySize
= PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
);
96 PlatformInfoHob
->Uc32Size
= GetPowerOfTwo32 ((UINT32
)(SIZE_4GB
- LowerMemorySize
));
97 PlatformInfoHob
->Uc32Base
= (UINT32
)(SIZE_4GB
- PlatformInfoHob
->Uc32Size
);
99 // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.
100 // Therefore Uc32Base is at least 2GB.
102 ASSERT (PlatformInfoHob
->Uc32Base
>= BASE_2GB
);
104 if (PlatformInfoHob
->Uc32Base
!= LowerMemorySize
) {
107 "%a: rounded UC32 base from 0x%x up to 0x%x, for "
108 "an UC32 size of 0x%x\n",
111 PlatformInfoHob
->Uc32Base
,
112 PlatformInfoHob
->Uc32Size
118 Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside
119 of the 32-bit address range.
121 Find the highest exclusive >=4GB RAM address, or produce memory resource
122 descriptor HOBs for RAM entries that start at or above 4GB.
124 @param[out] MaxAddress If MaxAddress is NULL, then PlatformScanOrAdd64BitE820Ram()
125 produces memory resource descriptor HOBs for RAM
126 entries that start at or above 4GB.
128 Otherwise, MaxAddress holds the highest exclusive
129 >=4GB RAM address on output. If QEMU's fw_cfg E820
130 RAM map contains no RAM entry that starts outside of
131 the 32-bit address range, then MaxAddress is exactly
134 @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and processed.
136 @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a
137 whole multiple of sizeof(EFI_E820_ENTRY64). No
138 RAM entry was processed.
140 @return Error codes from QemuFwCfgFindFile(). No RAM
145 PlatformScanOrAdd64BitE820Ram (
146 IN BOOLEAN AddHighHob
,
147 OUT UINT64
*LowMemory OPTIONAL
,
148 OUT UINT64
*MaxAddress OPTIONAL
152 FIRMWARE_CONFIG_ITEM FwCfgItem
;
154 EFI_E820_ENTRY64 E820Entry
;
157 Status
= QemuFwCfgFindFile ("etc/e820", &FwCfgItem
, &FwCfgSize
);
158 if (EFI_ERROR (Status
)) {
162 if (FwCfgSize
% sizeof E820Entry
!= 0) {
163 return EFI_PROTOCOL_ERROR
;
166 if (LowMemory
!= NULL
) {
170 if (MaxAddress
!= NULL
) {
171 *MaxAddress
= BASE_4GB
;
174 QemuFwCfgSelectItem (FwCfgItem
);
175 for (Processed
= 0; Processed
< FwCfgSize
; Processed
+= sizeof E820Entry
) {
176 QemuFwCfgReadBytes (sizeof E820Entry
, &E820Entry
);
179 "%a: Base=0x%Lx Length=0x%Lx Type=%u\n",
185 if (E820Entry
.Type
== EfiAcpiAddressRangeMemory
) {
186 if (AddHighHob
&& (E820Entry
.BaseAddr
>= BASE_4GB
)) {
191 // Round up the start address, and round down the end address.
193 Base
= ALIGN_VALUE (E820Entry
.BaseAddr
, (UINT64
)EFI_PAGE_SIZE
);
194 End
= (E820Entry
.BaseAddr
+ E820Entry
.Length
) &
195 ~(UINT64
)EFI_PAGE_MASK
;
197 PlatformAddMemoryRangeHob (Base
, End
);
200 "%a: PlatformAddMemoryRangeHob [0x%Lx, 0x%Lx)\n",
208 if (MaxAddress
|| LowMemory
) {
211 Candidate
= E820Entry
.BaseAddr
+ E820Entry
.Length
;
212 if (MaxAddress
&& (Candidate
> *MaxAddress
)) {
213 *MaxAddress
= Candidate
;
216 "%a: MaxAddress=0x%Lx\n",
222 if (LowMemory
&& (Candidate
> *LowMemory
) && (Candidate
< BASE_4GB
)) {
223 *LowMemory
= Candidate
;
226 "%a: LowMemory=0x%Lx\n",
232 } else if (E820Entry
.Type
== EfiAcpiAddressRangeReserved
) {
236 "%a: Reserved: Base=0x%Lx Length=0x%Lx\n",
241 BuildResourceDescriptorHob (
242 EFI_RESOURCE_MEMORY_RESERVED
,
257 @param Entries Pointer to PVH memmap
258 @param Count Number of entries
263 GetPvhMemmapEntries (
264 struct hvm_memmap_table_entry
**Entries
,
268 UINT32
*PVHResetVectorData
;
269 struct hvm_start_info
*pvh_start_info
;
271 PVHResetVectorData
= (VOID
*)(UINTN
)PcdGet32 (PcdXenPvhStartOfDayStructPtr
);
272 if (PVHResetVectorData
== 0) {
273 return EFI_NOT_FOUND
;
276 pvh_start_info
= (struct hvm_start_info
*)(UINTN
)PVHResetVectorData
[0];
278 *Entries
= (struct hvm_memmap_table_entry
*)(UINTN
)pvh_start_info
->memmap_paddr
;
279 *Count
= pvh_start_info
->memmap_entries
;
286 GetHighestSystemMemoryAddressFromPvhMemmap (
290 struct hvm_memmap_table_entry
*Memmap
;
291 UINT32 MemmapEntriesCount
;
292 struct hvm_memmap_table_entry
*Entry
;
295 UINT64 HighestAddress
;
300 Status
= GetPvhMemmapEntries (&Memmap
, &MemmapEntriesCount
);
301 ASSERT_EFI_ERROR (Status
);
303 for (Loop
= 0; Loop
< MemmapEntriesCount
; Loop
++) {
304 Entry
= Memmap
+ Loop
;
305 EntryEnd
= Entry
->addr
+ Entry
->size
;
307 if ((Entry
->type
== XEN_HVM_MEMMAP_TYPE_RAM
) &&
308 (EntryEnd
> HighestAddress
))
310 if (Below4gb
&& (EntryEnd
<= BASE_4GB
)) {
311 HighestAddress
= EntryEnd
;
312 } else if (!Below4gb
&& (EntryEnd
>= BASE_4GB
)) {
313 HighestAddress
= EntryEnd
;
318 return HighestAddress
;
323 PlatformGetSystemMemorySizeBelow4gb (
324 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
328 UINT64 LowerMemorySize
= 0;
332 if ((PlatformInfoHob
->HostBridgeDevId
== CLOUDHV_DEVICE_ID
) &&
333 (CcProbe () != CcGuestTypeIntelTdx
))
335 // Get the information from PVH memmap
336 return (UINT32
)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE
);
339 Status
= PlatformScanOrAdd64BitE820Ram (FALSE
, &LowerMemorySize
, NULL
);
340 if ((Status
== EFI_SUCCESS
) && (LowerMemorySize
> 0)) {
341 return (UINT32
)LowerMemorySize
;
345 // CMOS 0x34/0x35 specifies the system memory above 16 MB.
346 // * CMOS(0x35) is the high byte
347 // * CMOS(0x34) is the low byte
348 // * The size is specified in 64kb chunks
349 // * Since this is memory above 16MB, the 16MB must be added
350 // into the calculation to get the total memory size.
353 Cmos0x34
= (UINT8
)PlatformCmosRead8 (0x34);
354 Cmos0x35
= (UINT8
)PlatformCmosRead8 (0x35);
356 return (UINT32
)(((UINTN
)((Cmos0x35
<< 8) + Cmos0x34
) << 16) + SIZE_16MB
);
361 PlatformGetSystemMemorySizeAbove4gb (
368 // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
369 // * CMOS(0x5d) is the most significant size byte
370 // * CMOS(0x5c) is the middle size byte
371 // * CMOS(0x5b) is the least significant size byte
372 // * The size is specified in 64kb chunks
376 for (CmosIndex
= 0x5d; CmosIndex
>= 0x5b; CmosIndex
--) {
377 Size
= (UINT32
)(Size
<< 8) + (UINT32
)PlatformCmosRead8 (CmosIndex
);
380 return LShiftU64 (Size
, 16);
384 Return the highest address that DXE could possibly use, plus one.
388 PlatformGetFirstNonAddress (
389 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
392 UINT64 FirstNonAddress
;
393 UINT32 FwCfgPciMmio64Mb
;
395 FIRMWARE_CONFIG_ITEM FwCfgItem
;
397 UINT64 HotPlugMemoryEnd
;
400 // set FirstNonAddress to suppress incorrect compiler/analyzer warnings
405 // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM
406 // address from it. This can express an address >= 4GB+1TB.
408 // Otherwise, get the flat size of the memory above 4GB from the CMOS (which
409 // can only express a size smaller than 1TB), and add it to 4GB.
411 Status
= PlatformScanOrAdd64BitE820Ram (FALSE
, NULL
, &FirstNonAddress
);
412 if (EFI_ERROR (Status
)) {
413 FirstNonAddress
= BASE_4GB
+ PlatformGetSystemMemorySizeAbove4gb ();
417 // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO
418 // resources to 32-bit anyway. See DegradeResource() in
419 // "PciResourceSupport.c".
422 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode
)) {
423 return FirstNonAddress
;
429 // See if the user specified the number of megabytes for the 64-bit PCI host
430 // aperture. Accept an aperture size up to 16TB.
432 // As signaled by the "X-" prefix, this knob is experimental, and might go
435 Status
= QemuFwCfgParseUint32 (
436 "opt/ovmf/X-PciMmio64Mb",
441 case EFI_UNSUPPORTED
:
445 if (FwCfgPciMmio64Mb
<= 0x1000000) {
446 PlatformInfoHob
->PcdPciMmio64Size
= LShiftU64 (FwCfgPciMmio64Mb
, 20);
456 "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",
462 if (PlatformInfoHob
->PcdPciMmio64Size
== 0) {
463 if (PlatformInfoHob
->BootMode
!= BOOT_ON_S3_RESUME
) {
466 "%a: disabling 64-bit PCI host aperture\n",
472 // There's nothing more to do; the amount of memory above 4GB fully
473 // determines the highest address plus one. The memory hotplug area (see
474 // below) plays no role for the firmware in this case.
476 return FirstNonAddress
;
480 // The "etc/reserved-memory-end" fw_cfg file, when present, contains an
481 // absolute, exclusive end address for the memory hotplug area. This area
482 // starts right at the end of the memory above 4GB. The 64-bit PCI host
483 // aperture must be placed above it.
485 Status
= QemuFwCfgFindFile (
486 "etc/reserved-memory-end",
490 if (!EFI_ERROR (Status
) && (FwCfgSize
== sizeof HotPlugMemoryEnd
)) {
491 QemuFwCfgSelectItem (FwCfgItem
);
492 QemuFwCfgReadBytes (FwCfgSize
, &HotPlugMemoryEnd
);
495 "%a: HotPlugMemoryEnd=0x%Lx\n",
500 ASSERT (HotPlugMemoryEnd
>= FirstNonAddress
);
501 FirstNonAddress
= HotPlugMemoryEnd
;
505 // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so
506 // that the host can map it with 1GB hugepages. Follow suit.
508 PlatformInfoHob
->PcdPciMmio64Base
= ALIGN_VALUE (FirstNonAddress
, (UINT64
)SIZE_1GB
);
509 PlatformInfoHob
->PcdPciMmio64Size
= ALIGN_VALUE (PlatformInfoHob
->PcdPciMmio64Size
, (UINT64
)SIZE_1GB
);
512 // The 64-bit PCI host aperture should also be "naturally" aligned. The
513 // alignment is determined by rounding the size of the aperture down to the
514 // next smaller or equal power of two. That is, align the aperture by the
515 // largest BAR size that can fit into it.
517 PlatformInfoHob
->PcdPciMmio64Base
= ALIGN_VALUE (PlatformInfoHob
->PcdPciMmio64Base
, GetPowerOfTwo64 (PlatformInfoHob
->PcdPciMmio64Size
));
520 // The useful address space ends with the 64-bit PCI host aperture.
522 FirstNonAddress
= PlatformInfoHob
->PcdPciMmio64Base
+ PlatformInfoHob
->PcdPciMmio64Size
;
523 return FirstNonAddress
;
527 * Use CPUID to figure physical address width.
529 * Does *not* work reliable on qemu. For historical reasons qemu
530 * returns phys-bits=40 by default even in case the host machine
531 * supports less than that.
533 * So we apply the following rules (which can be enabled/disabled
534 * using the QemuQuirk parameter) to figure whenever we can work with
535 * the returned physical address width or not:
537 * (1) If it is 41 or higher consider it valid.
538 * (2) If it is 40 or lower consider it valid in case it matches a
539 * known-good value for the CPU vendor, which is:
540 * -> 36 or 39 for Intel
542 * (3) Otherwise consider it invalid.
544 * Recommendation: Run qemu with host-phys-bits=on. That will make
545 * sure guest phys-bits is not larger than host phys-bits. Some
546 * distro builds do that by default.
550 PlatformAddressWidthFromCpuid (
551 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
,
555 UINT32 RegEax
, RegEbx
, RegEcx
, RegEdx
, Max
;
557 CHAR8 Signature
[13] = { 0 };
558 BOOLEAN Valid
= FALSE
;
559 BOOLEAN Page1GSupport
= FALSE
;
561 AsmCpuid (0x80000000, &RegEax
, &RegEbx
, &RegEcx
, &RegEdx
);
562 *(UINT32
*)(Signature
+ 0) = RegEbx
;
563 *(UINT32
*)(Signature
+ 4) = RegEdx
;
564 *(UINT32
*)(Signature
+ 8) = RegEcx
;
567 if (Max
>= 0x80000001) {
568 AsmCpuid (0x80000001, NULL
, NULL
, NULL
, &RegEdx
);
569 if ((RegEdx
& BIT26
) != 0) {
570 Page1GSupport
= TRUE
;
574 if (Max
>= 0x80000008) {
575 AsmCpuid (0x80000008, &RegEax
, NULL
, NULL
, NULL
);
576 PhysBits
= (UINT8
)RegEax
;
583 } else if (PhysBits
>= 41) {
585 } else if (AsciiStrCmp (Signature
, "GenuineIntel") == 0) {
586 if ((PhysBits
== 36) || (PhysBits
== 39)) {
589 } else if (AsciiStrCmp (Signature
, "AuthenticAMD") == 0) {
590 if (PhysBits
== 40) {
597 "%a: Signature: '%a', PhysBits: %d, QemuQuirk: %a, Valid: %a\n",
601 QemuQuirk
? "On" : "Off",
608 * Avoid 5-level paging altogether for now, which limits
609 * PhysBits to 48. Also avoid using address bit 48, due to sign
610 * extension we can't identity-map these addresses (and lots of
611 * places in edk2 assume we have everything identity-mapped).
612 * So the actual limit is 47.
614 DEBUG ((DEBUG_INFO
, "%a: limit PhysBits to 47 (avoid 5-level paging)\n", __func__
));
618 if (!Page1GSupport
&& (PhysBits
> 40)) {
619 DEBUG ((DEBUG_INFO
, "%a: limit PhysBits to 40 (no 1G pages available)\n", __func__
));
623 PlatformInfoHob
->PhysMemAddressWidth
= PhysBits
;
624 PlatformInfoHob
->FirstNonAddress
= LShiftU64 (1, PlatformInfoHob
->PhysMemAddressWidth
);
630 PlatformDynamicMmioWindow (
631 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
634 UINT64 AddrSpace
, MmioSpace
;
636 AddrSpace
= LShiftU64 (1, PlatformInfoHob
->PhysMemAddressWidth
);
637 MmioSpace
= LShiftU64 (1, PlatformInfoHob
->PhysMemAddressWidth
- 3);
639 if ((PlatformInfoHob
->PcdPciMmio64Size
< MmioSpace
) &&
640 (PlatformInfoHob
->PcdPciMmio64Base
+ MmioSpace
< AddrSpace
))
642 DEBUG ((DEBUG_INFO
, "%a: using dynamic mmio window\n", __func__
));
643 DEBUG ((DEBUG_INFO
, "%a: Addr Space 0x%Lx (%Ld GB)\n", __func__
, AddrSpace
, RShiftU64 (AddrSpace
, 30)));
644 DEBUG ((DEBUG_INFO
, "%a: MMIO Space 0x%Lx (%Ld GB)\n", __func__
, MmioSpace
, RShiftU64 (MmioSpace
, 30)));
645 PlatformInfoHob
->PcdPciMmio64Size
= MmioSpace
;
646 PlatformInfoHob
->PcdPciMmio64Base
= AddrSpace
- MmioSpace
;
648 DEBUG ((DEBUG_INFO
, "%a: using classic mmio window\n", __func__
));
651 DEBUG ((DEBUG_INFO
, "%a: Pci64 Base 0x%Lx\n", __func__
, PlatformInfoHob
->PcdPciMmio64Base
));
652 DEBUG ((DEBUG_INFO
, "%a: Pci64 Size 0x%Lx\n", __func__
, PlatformInfoHob
->PcdPciMmio64Size
));
656 Iterate over the PCI host bridges resources information optionally provided
657 in fw-cfg and find the highest address contained in the PCI MMIO windows. If
658 the information is found, return the exclusive end; one past the last usable
661 @param[out] PciMmioAddressEnd Pointer to one-after End Address updated with
662 information extracted from host-provided data
663 or zero if no information available or an
666 @retval EFI_SUCCESS PCI information was read and the output
667 parameter updated with the last valid
668 address in the 64-bit MMIO range.
669 @retval EFI_INVALID_PARAMETER Pointer parameter is invalid
670 @retval EFI_INCOMPATIBLE_VERSION Hardware information found in fw-cfg
671 has an incompatible format
672 @retval EFI_UNSUPPORTED Fw-cfg is not supported, thus host
673 provided information, if any, cannot be
675 @retval EFI_NOT_FOUND No PCI host bridge information provided
680 PlatformScanHostProvided64BitPciMmioEnd (
681 OUT UINT64
*PciMmioAddressEnd
685 HOST_BRIDGE_INFO HostBridge
;
686 FIRMWARE_CONFIG_ITEM FwCfgItem
;
688 UINTN FwCfgReadIndex
;
690 UINT64 Above4GMmioEnd
;
692 if (PciMmioAddressEnd
== NULL
) {
693 return EFI_INVALID_PARAMETER
;
696 *PciMmioAddressEnd
= 0;
699 Status
= QemuFwCfgFindFile ("etc/hardware-info", &FwCfgItem
, &FwCfgSize
);
700 if (EFI_ERROR (Status
)) {
704 QemuFwCfgSelectItem (FwCfgItem
);
707 while (FwCfgReadIndex
< FwCfgSize
) {
708 Status
= QemuFwCfgReadNextHardwareInfoByType (
709 HardwareInfoTypeHostBridge
,
717 if (Status
!= EFI_SUCCESS
) {
719 // No more data available to read in the file, break
720 // loop and finish process
725 Status
= HardwareInfoPciHostBridgeLastMmioAddress (
732 if (Status
!= EFI_SUCCESS
) {
734 // Error parsing MMIO apertures and extracting last MMIO
735 // address, reset PciMmioAddressEnd as if no information was
736 // found, to avoid moving forward with incomplete data, and
741 "%a: ignoring malformed hardware information from fw_cfg\n",
744 *PciMmioAddressEnd
= 0;
748 if (Above4GMmioEnd
> *PciMmioAddressEnd
) {
749 *PciMmioAddressEnd
= Above4GMmioEnd
;
753 if (*PciMmioAddressEnd
> 0) {
755 // Host-provided PCI information was found and a MMIO window end
757 // Increase the End address by one to have the output pointing to
758 // one after the address in use (exclusive end).
760 *PciMmioAddressEnd
+= 1;
764 "%a: Pci64End=0x%Lx\n",
772 return EFI_NOT_FOUND
;
776 Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest RAM size.
780 PlatformAddressWidthInitialization (
781 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
784 UINT64 FirstNonAddress
;
785 UINT8 PhysMemAddressWidth
;
788 if (PlatformInfoHob
->HostBridgeDevId
== 0xffff /* microvm */) {
789 PlatformAddressWidthFromCpuid (PlatformInfoHob
, FALSE
);
794 // First scan host-provided hardware information to assess if the address
795 // space is already known. If so, guest must use those values.
797 Status
= PlatformScanHostProvided64BitPciMmioEnd (&FirstNonAddress
);
799 if (EFI_ERROR (Status
)) {
801 // If the host did not provide valid hardware information leading to a
802 // hard-defined 64-bit MMIO end, fold back to calculating the minimum range
804 // As guest-physical memory size grows, the permanent PEI RAM requirements
805 // are dominated by the identity-mapping page tables built by the DXE IPL.
806 // The DXL IPL keys off of the physical address bits advertized in the CPU
807 // HOB. To conserve memory, we calculate the minimum address width here.
809 FirstNonAddress
= PlatformGetFirstNonAddress (PlatformInfoHob
);
812 PlatformAddressWidthFromCpuid (PlatformInfoHob
, TRUE
);
813 if (PlatformInfoHob
->PhysMemAddressWidth
!= 0) {
814 // physical address width is known
815 PlatformInfoHob
->FirstNonAddress
= FirstNonAddress
;
816 PlatformDynamicMmioWindow (PlatformInfoHob
);
821 // physical address width is NOT known
822 // -> do some guess work, mostly based on installed memory
823 // -> try be conservstibe to stay below the guaranteed minimum of
824 // 36 phys bits (aka 64 GB).
826 PhysMemAddressWidth
= (UINT8
)HighBitSet64 (FirstNonAddress
);
829 // If FirstNonAddress is not an integral power of two, then we need an
832 if ((FirstNonAddress
& (FirstNonAddress
- 1)) != 0) {
833 ++PhysMemAddressWidth
;
837 // The minimum address width is 36 (covers up to and excluding 64 GB, which
838 // is the maximum for Ia32 + PAE). The theoretical architecture maximum for
839 // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
840 // can simply assert that here, since 48 bits are good enough for 256 TB.
842 if (PhysMemAddressWidth
<= 36) {
843 PhysMemAddressWidth
= 36;
846 #if defined (MDE_CPU_X64)
847 if (TdIsEnabled ()) {
848 if (TdSharedPageMask () == (1ULL << 47)) {
849 PhysMemAddressWidth
= 48;
851 PhysMemAddressWidth
= 52;
855 ASSERT (PhysMemAddressWidth
<= 52);
857 ASSERT (PhysMemAddressWidth
<= 48);
860 PlatformInfoHob
->FirstNonAddress
= FirstNonAddress
;
861 PlatformInfoHob
->PhysMemAddressWidth
= PhysMemAddressWidth
;
866 QemuInitializeRamBelow1gb (
867 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
870 if (PlatformInfoHob
->SmmSmramRequire
&& PlatformInfoHob
->Q35SmramAtDefaultSmbase
) {
871 PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE
);
872 PlatformAddReservedMemoryBaseSizeHob (
874 MCH_DEFAULT_SMBASE_SIZE
,
878 SMM_DEFAULT_SMBASE
+ MCH_DEFAULT_SMBASE_SIZE
< BASE_512KB
+ BASE_128KB
,
879 "end of SMRAM at default SMBASE ends at, or exceeds, 640KB"
881 PlatformAddMemoryRangeHob (
882 SMM_DEFAULT_SMBASE
+ MCH_DEFAULT_SMBASE_SIZE
,
883 BASE_512KB
+ BASE_128KB
886 PlatformAddMemoryRangeHob (0, BASE_512KB
+ BASE_128KB
);
891 Peform Memory Detection for QEMU / KVM
896 PlatformQemuInitializeRam (
897 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
900 UINT64 LowerMemorySize
;
901 UINT64 UpperMemorySize
;
902 MTRR_SETTINGS MtrrSettings
;
905 DEBUG ((DEBUG_INFO
, "%a called\n", __FUNCTION__
));
908 // Determine total memory size available
910 LowerMemorySize
= PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
);
912 if (PlatformInfoHob
->BootMode
== BOOT_ON_S3_RESUME
) {
914 // Create the following memory HOB as an exception on the S3 boot path.
916 // Normally we'd create memory HOBs only on the normal boot path. However,
917 // CpuMpPei specifically needs such a low-memory HOB on the S3 path as
918 // well, for "borrowing" a subset of it temporarily, for the AP startup
921 // CpuMpPei saves the original contents of the borrowed area in permanent
922 // PEI RAM, in a backup buffer allocated with the normal PEI services.
923 // CpuMpPei restores the original contents ("returns" the borrowed area) at
924 // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before
925 // transferring control to the OS's wakeup vector in the FACS.
927 // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to
928 // restore the original contents. Furthermore, we expect all such PEIMs
929 // (CpuMpPei included) to claim the borrowed areas by producing memory
930 // allocation HOBs, and to honor preexistent memory allocation HOBs when
931 // looking for an area to borrow.
933 QemuInitializeRamBelow1gb (PlatformInfoHob
);
936 // Create memory HOBs
938 QemuInitializeRamBelow1gb (PlatformInfoHob
);
940 if (PlatformInfoHob
->SmmSmramRequire
) {
943 TsegSize
= PlatformInfoHob
->Q35TsegMbytes
* SIZE_1MB
;
944 PlatformAddMemoryRangeHob (BASE_1MB
, LowerMemorySize
- TsegSize
);
945 PlatformAddReservedMemoryBaseSizeHob (
946 LowerMemorySize
- TsegSize
,
951 PlatformAddMemoryRangeHob (BASE_1MB
, LowerMemorySize
);
955 // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM
956 // entries. Otherwise, create a single memory HOB with the flat >=4GB
957 // memory size read from the CMOS.
959 Status
= PlatformScanOrAdd64BitE820Ram (TRUE
, NULL
, NULL
);
960 if (EFI_ERROR (Status
)) {
961 UpperMemorySize
= PlatformGetSystemMemorySizeAbove4gb ();
962 if (UpperMemorySize
!= 0) {
963 PlatformAddMemoryBaseSizeHob (BASE_4GB
, UpperMemorySize
);
969 // We'd like to keep the following ranges uncached:
971 // - [Uc32Base, 4 GB)
973 // Everything else should be WB. Unfortunately, programming the inverse (ie.
974 // keeping the default UC, and configuring the complement set of the above as
975 // WB) is not reliable in general, because the end of the upper RAM can have
976 // practically any alignment, and we may not have enough variable MTRRs to
979 if (IsMtrrSupported () && (PlatformInfoHob
->HostBridgeDevId
!= CLOUDHV_DEVICE_ID
)) {
980 MtrrGetAllMtrrs (&MtrrSettings
);
983 // MTRRs disabled, fixed MTRRs disabled, default type is uncached
985 ASSERT ((MtrrSettings
.MtrrDefType
& BIT11
) == 0);
986 ASSERT ((MtrrSettings
.MtrrDefType
& BIT10
) == 0);
987 ASSERT ((MtrrSettings
.MtrrDefType
& 0xFF) == 0);
990 // flip default type to writeback
992 SetMem (&MtrrSettings
.Fixed
, sizeof MtrrSettings
.Fixed
, 0x06);
993 ZeroMem (&MtrrSettings
.Variables
, sizeof MtrrSettings
.Variables
);
994 MtrrSettings
.MtrrDefType
|= BIT11
| BIT10
| 6;
995 MtrrSetAllMtrrs (&MtrrSettings
);
998 // Set memory range from 640KB to 1MB to uncacheable
1000 Status
= MtrrSetMemoryAttribute (
1001 BASE_512KB
+ BASE_128KB
,
1002 BASE_1MB
- (BASE_512KB
+ BASE_128KB
),
1005 ASSERT_EFI_ERROR (Status
);
1008 // Set the memory range from the start of the 32-bit MMIO area (32-bit PCI
1009 // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.
1011 Status
= MtrrSetMemoryAttribute (
1012 PlatformInfoHob
->Uc32Base
,
1013 SIZE_4GB
- PlatformInfoHob
->Uc32Base
,
1016 ASSERT_EFI_ERROR (Status
);
1022 PlatformQemuInitializeRamForS3 (
1023 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
1026 if (PlatformInfoHob
->S3Supported
&& (PlatformInfoHob
->BootMode
!= BOOT_ON_S3_RESUME
)) {
1028 // This is the memory range that will be used for PEI on S3 resume
1030 BuildMemoryAllocationHob (
1031 PlatformInfoHob
->S3AcpiReservedMemoryBase
,
1032 PlatformInfoHob
->S3AcpiReservedMemorySize
,
1037 // Cover the initial RAM area used as stack and temporary PEI heap.
1039 // This is reserved as ACPI NVS so it can be used on S3 resume.
1041 BuildMemoryAllocationHob (
1042 PcdGet32 (PcdOvmfSecPeiTempRamBase
),
1043 PcdGet32 (PcdOvmfSecPeiTempRamSize
),
1048 // SEC stores its table of GUIDed section handlers here.
1050 BuildMemoryAllocationHob (
1051 PcdGet64 (PcdGuidedExtractHandlerTableAddress
),
1052 PcdGet32 (PcdGuidedExtractHandlerTableSize
),
1058 // Reserve the initial page tables built by the reset vector code.
1060 // Since this memory range will be used by the Reset Vector on S3
1061 // resume, it must be reserved as ACPI NVS.
1063 BuildMemoryAllocationHob (
1064 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfSecPageTablesBase
),
1065 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfSecPageTablesSize
),
1069 if (PlatformInfoHob
->SevEsIsEnabled
) {
1071 // If SEV-ES is enabled, reserve the GHCB-related memory area. This
1072 // includes the extra page table used to break down the 2MB page
1073 // mapping into 4KB page entries where the GHCB resides and the
1074 // GHCB area itself.
1076 // Since this memory range will be used by the Reset Vector on S3
1077 // resume, it must be reserved as ACPI NVS.
1079 BuildMemoryAllocationHob (
1080 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbPageTableBase
),
1081 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbPageTableSize
),
1084 BuildMemoryAllocationHob (
1085 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbBase
),
1086 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbSize
),
1089 BuildMemoryAllocationHob (
1090 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbBackupBase
),
1091 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbBackupSize
),
1099 if (PlatformInfoHob
->BootMode
!= BOOT_ON_S3_RESUME
) {
1100 if (!PlatformInfoHob
->SmmSmramRequire
) {
1102 // Reserve the lock box storage area
1104 // Since this memory range will be used on S3 resume, it must be
1105 // reserved as ACPI NVS.
1107 // If S3 is unsupported, then various drivers might still write to the
1108 // LockBox area. We ought to prevent DXE from serving allocation requests
1109 // such that they would overlap the LockBox storage.
1112 (VOID
*)(UINTN
)PcdGet32 (PcdOvmfLockBoxStorageBase
),
1113 (UINTN
)PcdGet32 (PcdOvmfLockBoxStorageSize
)
1115 BuildMemoryAllocationHob (
1116 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfLockBoxStorageBase
),
1117 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfLockBoxStorageSize
),
1118 PlatformInfoHob
->S3Supported
? EfiACPIMemoryNVS
: EfiBootServicesData
1122 if (PlatformInfoHob
->SmmSmramRequire
) {
1126 // Make sure the TSEG area that we reported as a reserved memory resource
1127 // cannot be used for reserved memory allocations.
1129 TsegSize
= PlatformInfoHob
->Q35TsegMbytes
* SIZE_1MB
;
1130 BuildMemoryAllocationHob (
1131 PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
) - TsegSize
,
1133 EfiReservedMemoryType
1136 // Similarly, allocate away the (already reserved) SMRAM at the default
1137 // SMBASE, if it exists.
1139 if (PlatformInfoHob
->Q35SmramAtDefaultSmbase
) {
1140 BuildMemoryAllocationHob (
1142 MCH_DEFAULT_SMBASE_SIZE
,
1143 EfiReservedMemoryType
1149 if (FixedPcdGet32 (PcdOvmfWorkAreaSize
) != 0) {
1151 // Reserve the work area.
1153 // Since this memory range will be used by the Reset Vector on S3
1154 // resume, it must be reserved as ACPI NVS.
1156 // If S3 is unsupported, then various drivers might still write to the
1157 // work area. We ought to prevent DXE from serving allocation requests
1158 // such that they would overlap the work area.
1160 BuildMemoryAllocationHob (
1161 (EFI_PHYSICAL_ADDRESS
)(UINTN
)FixedPcdGet32 (PcdOvmfWorkAreaBase
),
1162 (UINT64
)(UINTN
)FixedPcdGet32 (PcdOvmfWorkAreaSize
),
1163 PlatformInfoHob
->S3Supported
? EfiACPIMemoryNVS
: EfiBootServicesData