2 Memory Detection for Virtual Machines.
4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
14 // The package level header files this module uses
16 #include <IndustryStandard/E820.h>
17 #include <IndustryStandard/I440FxPiix4.h>
18 #include <IndustryStandard/Q35MchIch9.h>
19 #include <IndustryStandard/CloudHv.h>
20 #include <IndustryStandard/Xen/arch-x86/hvm/start_info.h>
22 #include <Register/Intel/SmramSaveStateMap.h>
25 // The Library classes this module consumes
27 #include <Library/BaseLib.h>
28 #include <Library/BaseMemoryLib.h>
29 #include <Library/DebugLib.h>
30 #include <Library/HobLib.h>
31 #include <Library/IoLib.h>
32 #include <Library/MemEncryptSevLib.h>
33 #include <Library/PcdLib.h>
34 #include <Library/PciLib.h>
35 #include <Library/PeimEntryPoint.h>
36 #include <Library/ResourcePublicationLib.h>
37 #include <Library/MtrrLib.h>
38 #include <Library/QemuFwCfgLib.h>
39 #include <Library/QemuFwCfgSimpleParserLib.h>
40 #include <Library/TdxLib.h>
42 #include <Library/PlatformInitLib.h>
46 PlatformQemuUc32BaseInitialization (
47 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
50 UINT32 LowerMemorySize
;
52 if (PlatformInfoHob
->HostBridgeDevId
== 0xffff /* microvm */) {
56 if (PlatformInfoHob
->HostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
58 // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
59 // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for
60 // setting PcdPciExpressBaseAddress such that describing the
61 // [PcdPciExpressBaseAddress, 4GB) range require a very small number of
62 // variable MTRRs (preferably 1 or 2).
64 ASSERT (PcdGet64 (PcdPciExpressBaseAddress
) <= MAX_UINT32
);
65 PlatformInfoHob
->Uc32Base
= (UINT32
)PcdGet64 (PcdPciExpressBaseAddress
);
69 if (PlatformInfoHob
->HostBridgeDevId
== CLOUDHV_DEVICE_ID
) {
70 PlatformInfoHob
->Uc32Size
= CLOUDHV_MMIO_HOLE_SIZE
;
71 PlatformInfoHob
->Uc32Base
= CLOUDHV_MMIO_HOLE_ADDRESS
;
75 ASSERT (PlatformInfoHob
->HostBridgeDevId
== INTEL_82441_DEVICE_ID
);
77 // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one
78 // variable MTRR suffices by truncating the size to a whole power of two,
79 // while keeping the end affixed to 4GB. This will round the base up.
81 LowerMemorySize
= PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
);
82 PlatformInfoHob
->Uc32Size
= GetPowerOfTwo32 ((UINT32
)(SIZE_4GB
- LowerMemorySize
));
83 PlatformInfoHob
->Uc32Base
= (UINT32
)(SIZE_4GB
- PlatformInfoHob
->Uc32Size
);
85 // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.
86 // Therefore Uc32Base is at least 2GB.
88 ASSERT (PlatformInfoHob
->Uc32Base
>= BASE_2GB
);
90 if (PlatformInfoHob
->Uc32Base
!= LowerMemorySize
) {
93 "%a: rounded UC32 base from 0x%x up to 0x%x, for "
94 "an UC32 size of 0x%x\n",
97 PlatformInfoHob
->Uc32Base
,
98 PlatformInfoHob
->Uc32Size
104 Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside
105 of the 32-bit address range.
107 Find the highest exclusive >=4GB RAM address, or produce memory resource
108 descriptor HOBs for RAM entries that start at or above 4GB.
110 @param[out] MaxAddress If MaxAddress is NULL, then PlatformScanOrAdd64BitE820Ram()
111 produces memory resource descriptor HOBs for RAM
112 entries that start at or above 4GB.
114 Otherwise, MaxAddress holds the highest exclusive
115 >=4GB RAM address on output. If QEMU's fw_cfg E820
116 RAM map contains no RAM entry that starts outside of
117 the 32-bit address range, then MaxAddress is exactly
120 @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and processed.
122 @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a
123 whole multiple of sizeof(EFI_E820_ENTRY64). No
124 RAM entry was processed.
126 @return Error codes from QemuFwCfgFindFile(). No RAM
131 PlatformScanOrAdd64BitE820Ram (
132 IN BOOLEAN AddHighHob
,
133 OUT UINT64
*LowMemory OPTIONAL
,
134 OUT UINT64
*MaxAddress OPTIONAL
138 FIRMWARE_CONFIG_ITEM FwCfgItem
;
140 EFI_E820_ENTRY64 E820Entry
;
143 Status
= QemuFwCfgFindFile ("etc/e820", &FwCfgItem
, &FwCfgSize
);
144 if (EFI_ERROR (Status
)) {
148 if (FwCfgSize
% sizeof E820Entry
!= 0) {
149 return EFI_PROTOCOL_ERROR
;
152 if (LowMemory
!= NULL
) {
156 if (MaxAddress
!= NULL
) {
157 *MaxAddress
= BASE_4GB
;
160 QemuFwCfgSelectItem (FwCfgItem
);
161 for (Processed
= 0; Processed
< FwCfgSize
; Processed
+= sizeof E820Entry
) {
162 QemuFwCfgReadBytes (sizeof E820Entry
, &E820Entry
);
165 "%a: Base=0x%Lx Length=0x%Lx Type=%u\n",
171 if (E820Entry
.Type
== EfiAcpiAddressRangeMemory
) {
172 if (AddHighHob
&& (E820Entry
.BaseAddr
>= BASE_4GB
)) {
177 // Round up the start address, and round down the end address.
179 Base
= ALIGN_VALUE (E820Entry
.BaseAddr
, (UINT64
)EFI_PAGE_SIZE
);
180 End
= (E820Entry
.BaseAddr
+ E820Entry
.Length
) &
181 ~(UINT64
)EFI_PAGE_MASK
;
183 PlatformAddMemoryRangeHob (Base
, End
);
186 "%a: PlatformAddMemoryRangeHob [0x%Lx, 0x%Lx)\n",
194 if (MaxAddress
|| LowMemory
) {
197 Candidate
= E820Entry
.BaseAddr
+ E820Entry
.Length
;
198 if (MaxAddress
&& (Candidate
> *MaxAddress
)) {
199 *MaxAddress
= Candidate
;
202 "%a: MaxAddress=0x%Lx\n",
208 if (LowMemory
&& (Candidate
> *LowMemory
) && (Candidate
< BASE_4GB
)) {
209 *LowMemory
= Candidate
;
212 "%a: LowMemory=0x%Lx\n",
227 @param Entries Pointer to PVH memmap
228 @param Count Number of entries
233 GetPvhMemmapEntries (
234 struct hvm_memmap_table_entry
**Entries
,
238 UINT32
*PVHResetVectorData
;
239 struct hvm_start_info
*pvh_start_info
;
241 PVHResetVectorData
= (VOID
*)(UINTN
)PcdGet32 (PcdXenPvhStartOfDayStructPtr
);
242 if (PVHResetVectorData
== 0) {
243 return EFI_NOT_FOUND
;
246 pvh_start_info
= (struct hvm_start_info
*)(UINTN
)PVHResetVectorData
[0];
248 *Entries
= (struct hvm_memmap_table_entry
*)(UINTN
)pvh_start_info
->memmap_paddr
;
249 *Count
= pvh_start_info
->memmap_entries
;
256 GetHighestSystemMemoryAddressFromPvhMemmap (
260 struct hvm_memmap_table_entry
*Memmap
;
261 UINT32 MemmapEntriesCount
;
262 struct hvm_memmap_table_entry
*Entry
;
265 UINT64 HighestAddress
;
270 Status
= GetPvhMemmapEntries (&Memmap
, &MemmapEntriesCount
);
271 ASSERT_EFI_ERROR (Status
);
273 for (Loop
= 0; Loop
< MemmapEntriesCount
; Loop
++) {
274 Entry
= Memmap
+ Loop
;
275 EntryEnd
= Entry
->addr
+ Entry
->size
;
277 if ((Entry
->type
== XEN_HVM_MEMMAP_TYPE_RAM
) &&
278 (EntryEnd
> HighestAddress
))
280 if (Below4gb
&& (EntryEnd
<= BASE_4GB
)) {
281 HighestAddress
= EntryEnd
;
282 } else if (!Below4gb
&& (EntryEnd
>= BASE_4GB
)) {
283 HighestAddress
= EntryEnd
;
288 return HighestAddress
;
293 PlatformGetSystemMemorySizeBelow4gb (
294 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
298 UINT64 LowerMemorySize
= 0;
302 if (PlatformInfoHob
->HostBridgeDevId
== CLOUDHV_DEVICE_ID
) {
303 // Get the information from PVH memmap
304 return (UINT32
)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE
);
307 Status
= PlatformScanOrAdd64BitE820Ram (FALSE
, &LowerMemorySize
, NULL
);
308 if ((Status
== EFI_SUCCESS
) && (LowerMemorySize
> 0)) {
309 return (UINT32
)LowerMemorySize
;
313 // CMOS 0x34/0x35 specifies the system memory above 16 MB.
314 // * CMOS(0x35) is the high byte
315 // * CMOS(0x34) is the low byte
316 // * The size is specified in 64kb chunks
317 // * Since this is memory above 16MB, the 16MB must be added
318 // into the calculation to get the total memory size.
321 Cmos0x34
= (UINT8
)PlatformCmosRead8 (0x34);
322 Cmos0x35
= (UINT8
)PlatformCmosRead8 (0x35);
324 return (UINT32
)(((UINTN
)((Cmos0x35
<< 8) + Cmos0x34
) << 16) + SIZE_16MB
);
329 PlatformGetSystemMemorySizeAbove4gb (
336 // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
337 // * CMOS(0x5d) is the most significant size byte
338 // * CMOS(0x5c) is the middle size byte
339 // * CMOS(0x5b) is the least significant size byte
340 // * The size is specified in 64kb chunks
344 for (CmosIndex
= 0x5d; CmosIndex
>= 0x5b; CmosIndex
--) {
345 Size
= (UINT32
)(Size
<< 8) + (UINT32
)PlatformCmosRead8 (CmosIndex
);
348 return LShiftU64 (Size
, 16);
352 Return the highest address that DXE could possibly use, plus one.
356 PlatformGetFirstNonAddress (
357 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
360 UINT64 FirstNonAddress
;
361 UINT32 FwCfgPciMmio64Mb
;
363 FIRMWARE_CONFIG_ITEM FwCfgItem
;
365 UINT64 HotPlugMemoryEnd
;
368 // set FirstNonAddress to suppress incorrect compiler/analyzer warnings
373 // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM
374 // address from it. This can express an address >= 4GB+1TB.
376 // Otherwise, get the flat size of the memory above 4GB from the CMOS (which
377 // can only express a size smaller than 1TB), and add it to 4GB.
379 Status
= PlatformScanOrAdd64BitE820Ram (FALSE
, NULL
, &FirstNonAddress
);
380 if (EFI_ERROR (Status
)) {
381 FirstNonAddress
= BASE_4GB
+ PlatformGetSystemMemorySizeAbove4gb ();
385 // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO
386 // resources to 32-bit anyway. See DegradeResource() in
387 // "PciResourceSupport.c".
390 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode
)) {
391 return FirstNonAddress
;
397 // See if the user specified the number of megabytes for the 64-bit PCI host
398 // aperture. Accept an aperture size up to 16TB.
400 // As signaled by the "X-" prefix, this knob is experimental, and might go
403 Status
= QemuFwCfgParseUint32 (
404 "opt/ovmf/X-PciMmio64Mb",
409 case EFI_UNSUPPORTED
:
413 if (FwCfgPciMmio64Mb
<= 0x1000000) {
414 PlatformInfoHob
->PcdPciMmio64Size
= LShiftU64 (FwCfgPciMmio64Mb
, 20);
424 "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",
430 if (PlatformInfoHob
->PcdPciMmio64Size
== 0) {
431 if (PlatformInfoHob
->BootMode
!= BOOT_ON_S3_RESUME
) {
434 "%a: disabling 64-bit PCI host aperture\n",
440 // There's nothing more to do; the amount of memory above 4GB fully
441 // determines the highest address plus one. The memory hotplug area (see
442 // below) plays no role for the firmware in this case.
444 return FirstNonAddress
;
448 // The "etc/reserved-memory-end" fw_cfg file, when present, contains an
449 // absolute, exclusive end address for the memory hotplug area. This area
450 // starts right at the end of the memory above 4GB. The 64-bit PCI host
451 // aperture must be placed above it.
453 Status
= QemuFwCfgFindFile (
454 "etc/reserved-memory-end",
458 if (!EFI_ERROR (Status
) && (FwCfgSize
== sizeof HotPlugMemoryEnd
)) {
459 QemuFwCfgSelectItem (FwCfgItem
);
460 QemuFwCfgReadBytes (FwCfgSize
, &HotPlugMemoryEnd
);
463 "%a: HotPlugMemoryEnd=0x%Lx\n",
468 ASSERT (HotPlugMemoryEnd
>= FirstNonAddress
);
469 FirstNonAddress
= HotPlugMemoryEnd
;
473 // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so
474 // that the host can map it with 1GB hugepages. Follow suit.
476 PlatformInfoHob
->PcdPciMmio64Base
= ALIGN_VALUE (FirstNonAddress
, (UINT64
)SIZE_1GB
);
477 PlatformInfoHob
->PcdPciMmio64Size
= ALIGN_VALUE (PlatformInfoHob
->PcdPciMmio64Size
, (UINT64
)SIZE_1GB
);
480 // The 64-bit PCI host aperture should also be "naturally" aligned. The
481 // alignment is determined by rounding the size of the aperture down to the
482 // next smaller or equal power of two. That is, align the aperture by the
483 // largest BAR size that can fit into it.
485 PlatformInfoHob
->PcdPciMmio64Base
= ALIGN_VALUE (PlatformInfoHob
->PcdPciMmio64Base
, GetPowerOfTwo64 (PlatformInfoHob
->PcdPciMmio64Size
));
488 // The useful address space ends with the 64-bit PCI host aperture.
490 FirstNonAddress
= PlatformInfoHob
->PcdPciMmio64Base
+ PlatformInfoHob
->PcdPciMmio64Size
;
491 return FirstNonAddress
;
495 * Use CPUID to figure physical address width. Does *not* work
496 * reliable on qemu. For historical reasons qemu returns phys-bits=40
497 * even in case the host machine supports less than that.
499 * qemu has a cpu property (host-phys-bits={on,off}) to change that
500 * and make sure guest phys-bits are not larger than host phys-bits.,
501 * but it is off by default. Exception: microvm machine type
502 * hard-wires that property to on.
506 PlatformAddressWidthFromCpuid (
507 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
512 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
513 if (RegEax
>= 0x80000008) {
514 AsmCpuid (0x80000008, &RegEax
, NULL
, NULL
, NULL
);
515 PlatformInfoHob
->PhysMemAddressWidth
= (UINT8
)RegEax
;
517 PlatformInfoHob
->PhysMemAddressWidth
= 36;
520 PlatformInfoHob
->FirstNonAddress
= LShiftU64 (1, PlatformInfoHob
->PhysMemAddressWidth
);
524 "%a: cpuid: phys-bits is %d\n",
526 PlatformInfoHob
->PhysMemAddressWidth
531 Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest RAM size.
535 PlatformAddressWidthInitialization (
536 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
539 UINT64 FirstNonAddress
;
540 UINT8 PhysMemAddressWidth
;
542 if (PlatformInfoHob
->HostBridgeDevId
== 0xffff /* microvm */) {
543 PlatformAddressWidthFromCpuid (PlatformInfoHob
);
548 // As guest-physical memory size grows, the permanent PEI RAM requirements
549 // are dominated by the identity-mapping page tables built by the DXE IPL.
550 // The DXL IPL keys off of the physical address bits advertized in the CPU
551 // HOB. To conserve memory, we calculate the minimum address width here.
553 FirstNonAddress
= PlatformGetFirstNonAddress (PlatformInfoHob
);
554 PhysMemAddressWidth
= (UINT8
)HighBitSet64 (FirstNonAddress
);
557 // If FirstNonAddress is not an integral power of two, then we need an
560 if ((FirstNonAddress
& (FirstNonAddress
- 1)) != 0) {
561 ++PhysMemAddressWidth
;
565 // The minimum address width is 36 (covers up to and excluding 64 GB, which
566 // is the maximum for Ia32 + PAE). The theoretical architecture maximum for
567 // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
568 // can simply assert that here, since 48 bits are good enough for 256 TB.
570 if (PhysMemAddressWidth
<= 36) {
571 PhysMemAddressWidth
= 36;
574 #if defined (MDE_CPU_X64)
575 if (TdIsEnabled ()) {
576 if (TdSharedPageMask () == (1ULL << 47)) {
577 PhysMemAddressWidth
= 48;
579 PhysMemAddressWidth
= 52;
583 ASSERT (PhysMemAddressWidth
<= 52);
585 ASSERT (PhysMemAddressWidth
<= 48);
588 PlatformInfoHob
->FirstNonAddress
= FirstNonAddress
;
589 PlatformInfoHob
->PhysMemAddressWidth
= PhysMemAddressWidth
;
594 QemuInitializeRamBelow1gb (
595 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
598 if (PlatformInfoHob
->SmmSmramRequire
&& PlatformInfoHob
->Q35SmramAtDefaultSmbase
) {
599 PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE
);
600 PlatformAddReservedMemoryBaseSizeHob (
602 MCH_DEFAULT_SMBASE_SIZE
,
606 SMM_DEFAULT_SMBASE
+ MCH_DEFAULT_SMBASE_SIZE
< BASE_512KB
+ BASE_128KB
,
607 "end of SMRAM at default SMBASE ends at, or exceeds, 640KB"
609 PlatformAddMemoryRangeHob (
610 SMM_DEFAULT_SMBASE
+ MCH_DEFAULT_SMBASE_SIZE
,
611 BASE_512KB
+ BASE_128KB
614 PlatformAddMemoryRangeHob (0, BASE_512KB
+ BASE_128KB
);
619 Peform Memory Detection for QEMU / KVM
624 PlatformQemuInitializeRam (
625 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
628 UINT64 LowerMemorySize
;
629 UINT64 UpperMemorySize
;
630 MTRR_SETTINGS MtrrSettings
;
633 DEBUG ((DEBUG_INFO
, "%a called\n", __FUNCTION__
));
636 // Determine total memory size available
638 LowerMemorySize
= PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
);
640 if (PlatformInfoHob
->BootMode
== BOOT_ON_S3_RESUME
) {
642 // Create the following memory HOB as an exception on the S3 boot path.
644 // Normally we'd create memory HOBs only on the normal boot path. However,
645 // CpuMpPei specifically needs such a low-memory HOB on the S3 path as
646 // well, for "borrowing" a subset of it temporarily, for the AP startup
649 // CpuMpPei saves the original contents of the borrowed area in permanent
650 // PEI RAM, in a backup buffer allocated with the normal PEI services.
651 // CpuMpPei restores the original contents ("returns" the borrowed area) at
652 // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before
653 // transferring control to the OS's wakeup vector in the FACS.
655 // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to
656 // restore the original contents. Furthermore, we expect all such PEIMs
657 // (CpuMpPei included) to claim the borrowed areas by producing memory
658 // allocation HOBs, and to honor preexistent memory allocation HOBs when
659 // looking for an area to borrow.
661 QemuInitializeRamBelow1gb (PlatformInfoHob
);
664 // Create memory HOBs
666 QemuInitializeRamBelow1gb (PlatformInfoHob
);
668 if (PlatformInfoHob
->SmmSmramRequire
) {
671 TsegSize
= PlatformInfoHob
->Q35TsegMbytes
* SIZE_1MB
;
672 PlatformAddMemoryRangeHob (BASE_1MB
, LowerMemorySize
- TsegSize
);
673 PlatformAddReservedMemoryBaseSizeHob (
674 LowerMemorySize
- TsegSize
,
679 PlatformAddMemoryRangeHob (BASE_1MB
, LowerMemorySize
);
683 // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM
684 // entries. Otherwise, create a single memory HOB with the flat >=4GB
685 // memory size read from the CMOS.
687 Status
= PlatformScanOrAdd64BitE820Ram (TRUE
, NULL
, NULL
);
688 if (EFI_ERROR (Status
)) {
689 UpperMemorySize
= PlatformGetSystemMemorySizeAbove4gb ();
690 if (UpperMemorySize
!= 0) {
691 PlatformAddMemoryBaseSizeHob (BASE_4GB
, UpperMemorySize
);
697 // We'd like to keep the following ranges uncached:
699 // - [LowerMemorySize, 4 GB)
701 // Everything else should be WB. Unfortunately, programming the inverse (ie.
702 // keeping the default UC, and configuring the complement set of the above as
703 // WB) is not reliable in general, because the end of the upper RAM can have
704 // practically any alignment, and we may not have enough variable MTRRs to
707 if (IsMtrrSupported () && (PlatformInfoHob
->HostBridgeDevId
!= CLOUDHV_DEVICE_ID
)) {
708 MtrrGetAllMtrrs (&MtrrSettings
);
711 // MTRRs disabled, fixed MTRRs disabled, default type is uncached
713 ASSERT ((MtrrSettings
.MtrrDefType
& BIT11
) == 0);
714 ASSERT ((MtrrSettings
.MtrrDefType
& BIT10
) == 0);
715 ASSERT ((MtrrSettings
.MtrrDefType
& 0xFF) == 0);
718 // flip default type to writeback
720 SetMem (&MtrrSettings
.Fixed
, sizeof MtrrSettings
.Fixed
, 0x06);
721 ZeroMem (&MtrrSettings
.Variables
, sizeof MtrrSettings
.Variables
);
722 MtrrSettings
.MtrrDefType
|= BIT11
| BIT10
| 6;
723 MtrrSetAllMtrrs (&MtrrSettings
);
726 // Set memory range from 640KB to 1MB to uncacheable
728 Status
= MtrrSetMemoryAttribute (
729 BASE_512KB
+ BASE_128KB
,
730 BASE_1MB
- (BASE_512KB
+ BASE_128KB
),
733 ASSERT_EFI_ERROR (Status
);
736 // Set the memory range from the start of the 32-bit MMIO area (32-bit PCI
737 // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.
739 Status
= MtrrSetMemoryAttribute (
740 PlatformInfoHob
->Uc32Base
,
741 SIZE_4GB
- PlatformInfoHob
->Uc32Base
,
744 ASSERT_EFI_ERROR (Status
);
750 PlatformQemuInitializeRamForS3 (
751 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
754 if (PlatformInfoHob
->S3Supported
&& (PlatformInfoHob
->BootMode
!= BOOT_ON_S3_RESUME
)) {
756 // This is the memory range that will be used for PEI on S3 resume
758 BuildMemoryAllocationHob (
759 PlatformInfoHob
->S3AcpiReservedMemoryBase
,
760 PlatformInfoHob
->S3AcpiReservedMemorySize
,
765 // Cover the initial RAM area used as stack and temporary PEI heap.
767 // This is reserved as ACPI NVS so it can be used on S3 resume.
769 BuildMemoryAllocationHob (
770 PcdGet32 (PcdOvmfSecPeiTempRamBase
),
771 PcdGet32 (PcdOvmfSecPeiTempRamSize
),
776 // SEC stores its table of GUIDed section handlers here.
778 BuildMemoryAllocationHob (
779 PcdGet64 (PcdGuidedExtractHandlerTableAddress
),
780 PcdGet32 (PcdGuidedExtractHandlerTableSize
),
786 // Reserve the initial page tables built by the reset vector code.
788 // Since this memory range will be used by the Reset Vector on S3
789 // resume, it must be reserved as ACPI NVS.
791 BuildMemoryAllocationHob (
792 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfSecPageTablesBase
),
793 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfSecPageTablesSize
),
797 if (PlatformInfoHob
->SevEsIsEnabled
) {
799 // If SEV-ES is enabled, reserve the GHCB-related memory area. This
800 // includes the extra page table used to break down the 2MB page
801 // mapping into 4KB page entries where the GHCB resides and the
804 // Since this memory range will be used by the Reset Vector on S3
805 // resume, it must be reserved as ACPI NVS.
807 BuildMemoryAllocationHob (
808 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbPageTableBase
),
809 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbPageTableSize
),
812 BuildMemoryAllocationHob (
813 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbBase
),
814 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbSize
),
817 BuildMemoryAllocationHob (
818 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbBackupBase
),
819 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfSecGhcbBackupSize
),
827 if (PlatformInfoHob
->BootMode
!= BOOT_ON_S3_RESUME
) {
828 if (!PlatformInfoHob
->SmmSmramRequire
) {
830 // Reserve the lock box storage area
832 // Since this memory range will be used on S3 resume, it must be
833 // reserved as ACPI NVS.
835 // If S3 is unsupported, then various drivers might still write to the
836 // LockBox area. We ought to prevent DXE from serving allocation requests
837 // such that they would overlap the LockBox storage.
840 (VOID
*)(UINTN
)PcdGet32 (PcdOvmfLockBoxStorageBase
),
841 (UINTN
)PcdGet32 (PcdOvmfLockBoxStorageSize
)
843 BuildMemoryAllocationHob (
844 (EFI_PHYSICAL_ADDRESS
)(UINTN
)PcdGet32 (PcdOvmfLockBoxStorageBase
),
845 (UINT64
)(UINTN
)PcdGet32 (PcdOvmfLockBoxStorageSize
),
846 PlatformInfoHob
->S3Supported
? EfiACPIMemoryNVS
: EfiBootServicesData
850 if (PlatformInfoHob
->SmmSmramRequire
) {
854 // Make sure the TSEG area that we reported as a reserved memory resource
855 // cannot be used for reserved memory allocations.
857 TsegSize
= PlatformInfoHob
->Q35TsegMbytes
* SIZE_1MB
;
858 BuildMemoryAllocationHob (
859 PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
) - TsegSize
,
861 EfiReservedMemoryType
864 // Similarly, allocate away the (already reserved) SMRAM at the default
865 // SMBASE, if it exists.
867 if (PlatformInfoHob
->Q35SmramAtDefaultSmbase
) {
868 BuildMemoryAllocationHob (
870 MCH_DEFAULT_SMBASE_SIZE
,
871 EfiReservedMemoryType
877 if (FixedPcdGet32 (PcdOvmfWorkAreaSize
) != 0) {
879 // Reserve the work area.
881 // Since this memory range will be used by the Reset Vector on S3
882 // resume, it must be reserved as ACPI NVS.
884 // If S3 is unsupported, then various drivers might still write to the
885 // work area. We ought to prevent DXE from serving allocation requests
886 // such that they would overlap the work area.
888 BuildMemoryAllocationHob (
889 (EFI_PHYSICAL_ADDRESS
)(UINTN
)FixedPcdGet32 (PcdOvmfWorkAreaBase
),
890 (UINT64
)(UINTN
)FixedPcdGet32 (PcdOvmfWorkAreaSize
),
891 PlatformInfoHob
->S3Supported
? EfiACPIMemoryNVS
: EfiBootServicesData