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OvmfPkg/PlatformInitLib: Add check to NvVarStoreFV HeaderLength
[mirror_edk2.git] / OvmfPkg / Library / PlatformInitLib / Platform.c
1 /**@file
2
3 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
4 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
5
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 **/
9
10 //
11 // The package level header files this module uses
12 //
13 #include <PiPei.h>
14
15 //
16 // The Library classes this module consumes
17 //
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/BaseLib.h>
20 #include <Library/DebugLib.h>
21 #include <Library/HobLib.h>
22 #include <Library/IoLib.h>
23 #include <IndustryStandard/I440FxPiix4.h>
24 #include <IndustryStandard/Microvm.h>
25 #include <IndustryStandard/Pci22.h>
26 #include <IndustryStandard/Q35MchIch9.h>
27 #include <IndustryStandard/QemuCpuHotplug.h>
28 #include <Library/MemoryAllocationLib.h>
29 #include <Library/QemuFwCfgLib.h>
30 #include <Library/QemuFwCfgS3Lib.h>
31 #include <Library/QemuFwCfgSimpleParserLib.h>
32 #include <Library/PciLib.h>
33 #include <Guid/SystemNvDataGuid.h>
34 #include <Guid/VariableFormat.h>
35 #include <OvmfPlatforms.h>
36
37 #include <Library/PlatformInitLib.h>
38
39 VOID
40 EFIAPI
41 PlatformAddIoMemoryBaseSizeHob (
42 IN EFI_PHYSICAL_ADDRESS MemoryBase,
43 IN UINT64 MemorySize
44 )
45 {
46 BuildResourceDescriptorHob (
47 EFI_RESOURCE_MEMORY_MAPPED_IO,
48 EFI_RESOURCE_ATTRIBUTE_PRESENT |
49 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
50 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
51 EFI_RESOURCE_ATTRIBUTE_TESTED,
52 MemoryBase,
53 MemorySize
54 );
55 }
56
57 VOID
58 EFIAPI
59 PlatformAddReservedMemoryBaseSizeHob (
60 IN EFI_PHYSICAL_ADDRESS MemoryBase,
61 IN UINT64 MemorySize,
62 IN BOOLEAN Cacheable
63 )
64 {
65 BuildResourceDescriptorHob (
66 EFI_RESOURCE_MEMORY_RESERVED,
67 EFI_RESOURCE_ATTRIBUTE_PRESENT |
68 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
69 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
70 (Cacheable ?
71 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
72 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
73 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
74 0
75 ) |
76 EFI_RESOURCE_ATTRIBUTE_TESTED,
77 MemoryBase,
78 MemorySize
79 );
80 }
81
82 VOID
83 EFIAPI
84 PlatformAddIoMemoryRangeHob (
85 IN EFI_PHYSICAL_ADDRESS MemoryBase,
86 IN EFI_PHYSICAL_ADDRESS MemoryLimit
87 )
88 {
89 PlatformAddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
90 }
91
92 VOID
93 EFIAPI
94 PlatformAddMemoryBaseSizeHob (
95 IN EFI_PHYSICAL_ADDRESS MemoryBase,
96 IN UINT64 MemorySize
97 )
98 {
99 BuildResourceDescriptorHob (
100 EFI_RESOURCE_SYSTEM_MEMORY,
101 EFI_RESOURCE_ATTRIBUTE_PRESENT |
102 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
103 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
104 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
105 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
106 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
107 EFI_RESOURCE_ATTRIBUTE_TESTED,
108 MemoryBase,
109 MemorySize
110 );
111 }
112
113 VOID
114 EFIAPI
115 PlatformAddMemoryRangeHob (
116 IN EFI_PHYSICAL_ADDRESS MemoryBase,
117 IN EFI_PHYSICAL_ADDRESS MemoryLimit
118 )
119 {
120 PlatformAddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
121 }
122
123 VOID
124 EFIAPI
125 PlatformMemMapInitialization (
126 IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
127 )
128 {
129 UINT64 PciIoBase;
130 UINT64 PciIoSize;
131 UINT32 TopOfLowRam;
132 UINT64 PciExBarBase;
133 UINT32 PciBase;
134 UINT32 PciSize;
135
136 PciIoBase = 0xC000;
137 PciIoSize = 0x4000;
138
139 //
140 // Video memory + Legacy BIOS region
141 //
142 if (!TdIsEnabled ()) {
143 PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB);
144 }
145
146 if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) {
147 PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);
148 PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */
149 PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */
150 return;
151 }
152
153 TopOfLowRam = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);
154 PciExBarBase = 0;
155 if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
156 //
157 // The MMCONFIG area is expected to fall between the top of low RAM and
158 // the base of the 32-bit PCI host aperture.
159 //
160 PciExBarBase = PcdGet64 (PcdPciExpressBaseAddress);
161 ASSERT (TopOfLowRam <= PciExBarBase);
162 ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
163 PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
164 } else {
165 ASSERT (TopOfLowRam <= PlatformInfoHob->Uc32Base);
166 PciBase = PlatformInfoHob->Uc32Base;
167 }
168
169 //
170 // address purpose size
171 // ------------ -------- -------------------------
172 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
173 // 0xFC000000 gap 44 MB
174 // 0xFEC00000 IO-APIC 4 KB
175 // 0xFEC01000 gap 1020 KB
176 // 0xFED00000 HPET 1 KB
177 // 0xFED00400 gap 111 KB
178 // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
179 // 0xFED20000 gap 896 KB
180 // 0xFEE00000 LAPIC 1 MB
181 //
182 PciSize = 0xFC000000 - PciBase;
183 PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize);
184
185 PlatformInfoHob->PcdPciMmio32Base = PciBase;
186 PlatformInfoHob->PcdPciMmio32Size = PciSize;
187
188 PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
189 PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
190 if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
191 PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
192 //
193 // Note: there should be an
194 //
195 // PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
196 //
197 // call below, just like the one above for RCBA. However, Linux insists
198 // that the MMCONFIG area be marked in the E820 or UEFI memory map as
199 // "reserved memory" -- Linux does not content itself with a simple gap
200 // in the memory map wherever the MCFG ACPI table points to.
201 //
202 // This appears to be a safety measure. The PCI Firmware Specification
203 // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
204 // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
205 // [...]". (Emphasis added here.)
206 //
207 // Normally we add memory resource descriptor HOBs in
208 // QemuInitializeRam(), and pre-allocate from those with memory
209 // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
210 // is most definitely not RAM; so, as an exception, cover it with
211 // uncacheable reserved memory right here.
212 //
213 PlatformAddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
214 BuildMemoryAllocationHob (
215 PciExBarBase,
216 SIZE_256MB,
217 EfiReservedMemoryType
218 );
219 }
220
221 PlatformAddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);
222
223 //
224 // On Q35, the IO Port space is available for PCI resource allocations from
225 // 0x6000 up.
226 //
227 if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
228 PciIoBase = 0x6000;
229 PciIoSize = 0xA000;
230 ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
231 }
232
233 //
234 // Add PCI IO Port space available for PCI resource allocations.
235 //
236 BuildResourceDescriptorHob (
237 EFI_RESOURCE_IO,
238 EFI_RESOURCE_ATTRIBUTE_PRESENT |
239 EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
240 PciIoBase,
241 PciIoSize
242 );
243
244 PlatformInfoHob->PcdPciIoBase = PciIoBase;
245 PlatformInfoHob->PcdPciIoSize = PciIoSize;
246 }
247
248 /**
249 * Fetch "opt/ovmf/PcdSetNxForStack" from QEMU
250 *
251 * @param Setting The pointer to the setting of "/opt/ovmf/PcdSetNxForStack".
252 * @return EFI_SUCCESS Successfully fetch the settings.
253 */
254 EFI_STATUS
255 EFIAPI
256 PlatformNoexecDxeInitialization (
257 IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
258 )
259 {
260 return QemuFwCfgParseBool ("opt/ovmf/PcdSetNxForStack", &PlatformInfoHob->PcdSetNxForStack);
261 }
262
263 VOID
264 PciExBarInitialization (
265 VOID
266 )
267 {
268 union {
269 UINT64 Uint64;
270 UINT32 Uint32[2];
271 } PciExBarBase;
272
273 //
274 // We only support the 256MB size for the MMCONFIG area:
275 // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
276 //
277 // The masks used below enforce the Q35 requirements that the MMCONFIG area
278 // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
279 //
280 // Note that (b) also ensures that the minimum address width we have
281 // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
282 // for DXE's page tables to cover the MMCONFIG area.
283 //
284 PciExBarBase.Uint64 = PcdGet64 (PcdPciExpressBaseAddress);
285 ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
286 ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
287
288 //
289 // Clear the PCIEXBAREN bit first, before programming the high register.
290 //
291 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
292
293 //
294 // Program the high register. Then program the low register, setting the
295 // MMCONFIG area size and enabling decoding at once.
296 //
297 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
298 PciWrite32 (
299 DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
300 PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
301 );
302 }
303
304 VOID
305 EFIAPI
306 PlatformMiscInitialization (
307 IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
308 )
309 {
310 UINTN PmCmd;
311 UINTN Pmba;
312 UINT32 PmbaAndVal;
313 UINT32 PmbaOrVal;
314 UINTN AcpiCtlReg;
315 UINT8 AcpiEnBit;
316
317 //
318 // Disable A20 Mask
319 //
320 if (PlatformInfoHob->HostBridgeDevId != CLOUDHV_DEVICE_ID) {
321 IoOr8 (0x92, BIT1);
322 }
323
324 //
325 // Build the CPU HOB with guest RAM size dependent address width and 16-bits
326 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
327 // S3 resume as well, so we build it unconditionally.)
328 //
329 BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16);
330
331 //
332 // Determine platform type and save Host Bridge DID to PCD
333 //
334 switch (PlatformInfoHob->HostBridgeDevId) {
335 case INTEL_82441_DEVICE_ID:
336 PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
337 Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
338 PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
339 PmbaOrVal = PIIX4_PMBA_VALUE;
340 AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
341 AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
342 break;
343 case INTEL_Q35_MCH_DEVICE_ID:
344 PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
345 Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
346 PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
347 PmbaOrVal = ICH9_PMBASE_VALUE;
348 AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
349 AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
350 break;
351 case CLOUDHV_DEVICE_ID:
352 break;
353 default:
354 DEBUG ((
355 DEBUG_ERROR,
356 "%a: Unknown Host Bridge Device ID: 0x%04x\n",
357 __FUNCTION__,
358 PlatformInfoHob->HostBridgeDevId
359 ));
360 ASSERT (FALSE);
361 return;
362 }
363
364 if (PlatformInfoHob->HostBridgeDevId == CLOUDHV_DEVICE_ID) {
365 DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor is done.\n", __FUNCTION__));
366 return;
367 }
368
369 //
370 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has
371 // been configured and skip the setup here. This matches the logic in
372 // AcpiTimerLibConstructor ().
373 //
374 if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
375 //
376 // The PEI phase should be exited with fully accessibe ACPI PM IO space:
377 // 1. set PMBA
378 //
379 PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
380
381 //
382 // 2. set PCICMD/IOSE
383 //
384 PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
385
386 //
387 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
388 //
389 PciOr8 (AcpiCtlReg, AcpiEnBit);
390 }
391
392 if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
393 //
394 // Set Root Complex Register Block BAR
395 //
396 PciWrite32 (
397 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
398 ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
399 );
400
401 //
402 // Set PCI Express Register Range Base Address
403 //
404 PciExBarInitialization ();
405 }
406 }
407
408 /**
409 Fetch the boot CPU count and the possible CPU count from QEMU, and expose
410 them to UefiCpuPkg modules.
411 **/
412 VOID
413 EFIAPI
414 PlatformMaxCpuCountInitialization (
415 IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
416 )
417 {
418 UINT16 BootCpuCount = 0;
419 UINT32 MaxCpuCount;
420
421 //
422 // Try to fetch the boot CPU count.
423 //
424 if (QemuFwCfgIsAvailable ()) {
425 QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);
426 BootCpuCount = QemuFwCfgRead16 ();
427 }
428
429 if (BootCpuCount == 0) {
430 //
431 // QEMU doesn't report the boot CPU count. (BootCpuCount == 0) will let
432 // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or
433 // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reached
434 // first).
435 //
436 DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__));
437 MaxCpuCount = PlatformInfoHob->DefaultMaxCpuNumber;
438 } else {
439 //
440 // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs up to
441 // (BootCpuCount - 1) precisely, regardless of timeout.
442 //
443 // Now try to fetch the possible CPU count.
444 //
445 UINTN CpuHpBase;
446 UINT32 CmdData2;
447
448 CpuHpBase = ((PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?
449 ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);
450
451 //
452 // If only legacy mode is available in the CPU hotplug register block, or
453 // the register block is completely missing, then the writes below are
454 // no-ops.
455 //
456 // 1. Switch the hotplug register block to modern mode.
457 //
458 IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);
459 //
460 // 2. Select a valid CPU for deterministic reading of
461 // QEMU_CPUHP_R_CMD_DATA2.
462 //
463 // CPU#0 is always valid; it is the always present and non-removable
464 // BSP.
465 //
466 IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);
467 //
468 // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to
469 // read as zero, and which does not invalidate the selector. (The
470 // selector may change, but it must not become invalid.)
471 //
472 // Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later.
473 //
474 IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING);
475 //
476 // 4. Read QEMU_CPUHP_R_CMD_DATA2.
477 //
478 // If the register block is entirely missing, then this is an unassigned
479 // IO read, returning all-bits-one.
480 //
481 // If only legacy mode is available, then bit#0 stands for CPU#0 in the
482 // "CPU present bitmap". CPU#0 is always present.
483 //
484 // Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (returning
485 // all-bits-zero), or it is specified to read as zero after the above
486 // steps. Both cases confirm modern mode.
487 //
488 CmdData2 = IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2);
489 DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=0x%x\n", __FUNCTION__, CmdData2));
490 if (CmdData2 != 0) {
491 //
492 // QEMU doesn't support the modern CPU hotplug interface. Assume that the
493 // possible CPU count equals the boot CPU count (precluding hotplug).
494 //
495 DEBUG ((
496 DEBUG_WARN,
497 "%a: modern CPU hotplug interface unavailable\n",
498 __FUNCTION__
499 ));
500 MaxCpuCount = BootCpuCount;
501 } else {
502 //
503 // Grab the possible CPU count from the modern CPU hotplug interface.
504 //
505 UINT32 Present, Possible, Selected;
506
507 Present = 0;
508 Possible = 0;
509
510 //
511 // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures
512 // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However,
513 // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pending
514 // hotplug events; therefore, select CPU#0 forcibly.
515 //
516 IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);
517
518 do {
519 UINT8 CpuStatus;
520
521 //
522 // Read the status of the currently selected CPU. This will help with a
523 // sanity check against "BootCpuCount".
524 //
525 CpuStatus = IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT);
526 if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) != 0) {
527 ++Present;
528 }
529
530 //
531 // Attempt to select the next CPU.
532 //
533 ++Possible;
534 IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);
535 //
536 // If the selection is successful, then the following read will return
537 // the selector (which we know is positive at this point). Otherwise,
538 // the read will return 0.
539 //
540 Selected = IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA);
541 ASSERT (Selected == Possible || Selected == 0);
542 } while (Selected > 0);
543
544 //
545 // Sanity check: fw_cfg and the modern CPU hotplug interface should
546 // return the same boot CPU count.
547 //
548 if (BootCpuCount != Present) {
549 DEBUG ((
550 DEBUG_WARN,
551 "%a: QEMU v2.7 reset bug: BootCpuCount=%d "
552 "Present=%u\n",
553 __FUNCTION__,
554 BootCpuCount,
555 Present
556 ));
557 //
558 // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug plus
559 // platform reset (including S3), was corrected in QEMU commit
560 // e3cadac073a9 ("pc: fix FW_CFG_NB_CPUS to account for -device added
561 // CPUs", 2016-11-16), part of release v2.8.0.
562 //
563 BootCpuCount = (UINT16)Present;
564 }
565
566 MaxCpuCount = Possible;
567 }
568 }
569
570 DEBUG ((
571 DEBUG_INFO,
572 "%a: BootCpuCount=%d MaxCpuCount=%u\n",
573 __FUNCTION__,
574 BootCpuCount,
575 MaxCpuCount
576 ));
577 ASSERT (BootCpuCount <= MaxCpuCount);
578
579 PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber = MaxCpuCount;
580 PlatformInfoHob->PcdCpuBootLogicalProcessorNumber = BootCpuCount;
581 }
582
583 /**
584 Check padding data all bit should be 1.
585
586 @param[in] Buffer - A pointer to buffer header
587 @param[in] BufferSize - Buffer size
588
589 @retval TRUE - The padding data is valid.
590 @retval TRUE - The padding data is invalid.
591
592 **/
593 BOOLEAN
594 CheckPaddingData (
595 IN UINT8 *Buffer,
596 IN UINT32 BufferSize
597 )
598 {
599 UINT32 index;
600
601 for (index = 0; index < BufferSize; index++) {
602 if (Buffer[index] != 0xFF) {
603 return FALSE;
604 }
605 }
606
607 return TRUE;
608 }
609
610 /**
611 Check the integrity of NvVarStore.
612
613 @param[in] NvVarStoreBase - A pointer to NvVarStore header
614 @param[in] NvVarStoreSize - NvVarStore size
615
616 @retval TRUE - The NvVarStore is valid.
617 @retval FALSE - The NvVarStore is invalid.
618
619 **/
620 BOOLEAN
621 EFIAPI
622 PlatformValidateNvVarStore (
623 IN UINT8 *NvVarStoreBase,
624 IN UINT32 NvVarStoreSize
625 )
626 {
627 UINT16 Checksum;
628 UINTN VariableBase;
629 UINT32 VariableOffset;
630 UINT32 VariableOffsetBeforeAlign;
631 EFI_FIRMWARE_VOLUME_HEADER *NvVarStoreFvHeader;
632 VARIABLE_STORE_HEADER *NvVarStoreHeader;
633 AUTHENTICATED_VARIABLE_HEADER *VariableHeader;
634
635 static EFI_GUID FvHdrGUID = EFI_SYSTEM_NV_DATA_FV_GUID;
636 static EFI_GUID VarStoreHdrGUID = EFI_AUTHENTICATED_VARIABLE_GUID;
637
638 VariableOffset = 0;
639
640 if (NvVarStoreBase == NULL) {
641 DEBUG ((DEBUG_ERROR, "NvVarStore pointer is NULL.\n"));
642 return FALSE;
643 }
644
645 //
646 // Verify the header zerovetor, filesystemguid,
647 // revision, signature, attributes, fvlength, checksum
648 // HeaderLength cannot be an odd number
649 //
650 NvVarStoreFvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)NvVarStoreBase;
651
652 if ((!IsZeroBuffer (NvVarStoreFvHeader->ZeroVector, 16)) ||
653 (!CompareGuid (&FvHdrGUID, &NvVarStoreFvHeader->FileSystemGuid)) ||
654 (NvVarStoreFvHeader->Signature != EFI_FVH_SIGNATURE) ||
655 (NvVarStoreFvHeader->Attributes != 0x4feff) ||
656 ((NvVarStoreFvHeader->HeaderLength & 0x01) != 0) ||
657 (NvVarStoreFvHeader->Revision != EFI_FVH_REVISION) ||
658 (NvVarStoreFvHeader->FvLength != NvVarStoreSize)
659 )
660 {
661 DEBUG ((DEBUG_ERROR, "NvVarStore FV headers were invalid.\n"));
662 return FALSE;
663 }
664
665 //
666 // Verify the header checksum
667 //
668 Checksum = CalculateSum16 ((VOID *)NvVarStoreFvHeader, NvVarStoreFvHeader->HeaderLength);
669
670 if (Checksum != 0) {
671 DEBUG ((DEBUG_ERROR, "NvVarStore FV checksum was invalid.\n"));
672 return FALSE;
673 }
674
675 //
676 // Verify the header signature, size, format, state
677 //
678 NvVarStoreHeader = (VARIABLE_STORE_HEADER *)(NvVarStoreBase + NvVarStoreFvHeader->HeaderLength);
679 if ((!CompareGuid (&VarStoreHdrGUID, &NvVarStoreHeader->Signature)) ||
680 (NvVarStoreHeader->Format != VARIABLE_STORE_FORMATTED) ||
681 (NvVarStoreHeader->State != VARIABLE_STORE_HEALTHY) ||
682 (NvVarStoreHeader->Size > (NvVarStoreFvHeader->FvLength - NvVarStoreFvHeader->HeaderLength)) ||
683 (NvVarStoreHeader->Size < sizeof (VARIABLE_STORE_HEADER))
684 )
685 {
686 DEBUG ((DEBUG_ERROR, "NvVarStore header signature/size/format/state were invalid.\n"));
687 return FALSE;
688 }
689
690 //
691 // Verify the header startId, state
692 // Verify data to the end
693 //
694 VariableBase = (UINTN)NvVarStoreBase + NvVarStoreFvHeader->HeaderLength + sizeof (VARIABLE_STORE_HEADER);
695 while (VariableOffset < (NvVarStoreHeader->Size - sizeof (VARIABLE_STORE_HEADER))) {
696 VariableHeader = (AUTHENTICATED_VARIABLE_HEADER *)(VariableBase + VariableOffset);
697 if (VariableHeader->StartId != VARIABLE_DATA) {
698 if (!CheckPaddingData ((UINT8 *)VariableHeader, NvVarStoreHeader->Size - sizeof (VARIABLE_STORE_HEADER) - VariableOffset)) {
699 DEBUG ((DEBUG_ERROR, "NvVarStore variable header StartId was invalid.\n"));
700 return FALSE;
701 }
702
703 VariableOffset = NvVarStoreHeader->Size - sizeof (VARIABLE_STORE_HEADER);
704 } else {
705 if (!((VariableHeader->State == VAR_IN_DELETED_TRANSITION) ||
706 (VariableHeader->State == VAR_DELETED) ||
707 (VariableHeader->State == VAR_HEADER_VALID_ONLY) ||
708 (VariableHeader->State == VAR_ADDED)))
709 {
710 DEBUG ((DEBUG_ERROR, "NvVarStore Variable header State was invalid.\n"));
711 return FALSE;
712 }
713
714 VariableOffset += sizeof (AUTHENTICATED_VARIABLE_HEADER) + VariableHeader->NameSize + VariableHeader->DataSize;
715 // Verify VariableOffset should be less than or equal NvVarStoreHeader->Size - sizeof(VARIABLE_STORE_HEADER)
716 if (VariableOffset > (NvVarStoreHeader->Size - sizeof (VARIABLE_STORE_HEADER))) {
717 DEBUG ((DEBUG_ERROR, "NvVarStore Variable header VariableOffset was invalid.\n"));
718 return FALSE;
719 }
720
721 VariableOffsetBeforeAlign = VariableOffset;
722 // 4 byte align
723 VariableOffset = (VariableOffset + 3) & (UINTN)(~3);
724
725 if (!CheckPaddingData ((UINT8 *)(VariableBase + VariableOffsetBeforeAlign), VariableOffset - VariableOffsetBeforeAlign)) {
726 DEBUG ((DEBUG_ERROR, "NvVarStore Variable header PaddingData was invalid.\n"));
727 return FALSE;
728 }
729 }
730 }
731
732 return TRUE;
733 }
734
735 /**
736 Allocate storage for NV variables early on so it will be
737 at a consistent address. Since VM memory is preserved
738 across reboots, this allows the NV variable storage to survive
739 a VM reboot.
740
741 *
742 * @retval VOID* The pointer to the storage for NV Variables
743 */
744 VOID *
745 EFIAPI
746 PlatformReserveEmuVariableNvStore (
747 VOID
748 )
749 {
750 VOID *VariableStore;
751 UINT32 VarStoreSize;
752
753 VarStoreSize = 2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize);
754 //
755 // Allocate storage for NV variables early on so it will be
756 // at a consistent address. Since VM memory is preserved
757 // across reboots, this allows the NV variable storage to survive
758 // a VM reboot.
759 //
760 VariableStore =
761 AllocateRuntimePages (
762 EFI_SIZE_TO_PAGES (VarStoreSize)
763 );
764 DEBUG ((
765 DEBUG_INFO,
766 "Reserved variable store memory: 0x%p; size: %dkb\n",
767 VariableStore,
768 VarStoreSize / 1024
769 ));
770
771 return VariableStore;
772 }
773
774 /**
775 When OVMF is lauched with -bios parameter, UEFI variables will be
776 partially emulated, and non-volatile variables may lose their contents
777 after a reboot. This makes the secure boot feature not working.
778
779 This function is used to initialize the EmuVariableNvStore
780 with the conent in PcdOvmfFlashNvStorageVariableBase.
781
782 @param[in] EmuVariableNvStore - A pointer to EmuVariableNvStore
783
784 @retval EFI_SUCCESS - Successfully init the EmuVariableNvStore
785 @retval Others - As the error code indicates
786 */
787 EFI_STATUS
788 EFIAPI
789 PlatformInitEmuVariableNvStore (
790 IN VOID *EmuVariableNvStore
791 )
792 {
793 UINT8 *Base;
794 UINT32 Size;
795 UINT32 EmuVariableNvStoreSize;
796
797 EmuVariableNvStoreSize = 2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize);
798 if ((EmuVariableNvStore == NULL) || (EmuVariableNvStoreSize == 0)) {
799 DEBUG ((DEBUG_ERROR, "Invalid EmuVariableNvStore parameter.\n"));
800 return EFI_INVALID_PARAMETER;
801 }
802
803 Base = (UINT8 *)(UINTN)PcdGet32 (PcdOvmfFlashNvStorageVariableBase);
804 Size = (UINT32)PcdGet32 (PcdFlashNvStorageVariableSize);
805 ASSERT (Size < EmuVariableNvStoreSize);
806
807 if (!PlatformValidateNvVarStore (Base, PcdGet32 (PcdCfvRawDataSize))) {
808 ASSERT (FALSE);
809 return EFI_INVALID_PARAMETER;
810 }
811
812 DEBUG ((DEBUG_INFO, "Init EmuVariableNvStore with the content in FlashNvStorage\n"));
813
814 CopyMem (EmuVariableNvStore, Base, Size);
815
816 return EFI_SUCCESS;
817 }
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