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1 /**@file
2
3 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
4 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
5
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 **/
9
10 //
11 // The package level header files this module uses
12 //
13 #include <PiPei.h>
14
15 //
16 // The Library classes this module consumes
17 //
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/BaseLib.h>
20 #include <Library/DebugLib.h>
21 #include <Library/HobLib.h>
22 #include <Library/IoLib.h>
23 #include <IndustryStandard/I440FxPiix4.h>
24 #include <IndustryStandard/Microvm.h>
25 #include <IndustryStandard/Pci22.h>
26 #include <IndustryStandard/Q35MchIch9.h>
27 #include <IndustryStandard/QemuCpuHotplug.h>
28 #include <Library/MemoryAllocationLib.h>
29 #include <Library/QemuFwCfgLib.h>
30 #include <Library/QemuFwCfgS3Lib.h>
31 #include <Library/QemuFwCfgSimpleParserLib.h>
32 #include <Library/PciLib.h>
33 #include <Guid/SystemNvDataGuid.h>
34 #include <Guid/VariableFormat.h>
35 #include <OvmfPlatforms.h>
36
37 #include <Library/PlatformInitLib.h>
38
39 VOID
40 EFIAPI
41 PlatformAddIoMemoryBaseSizeHob (
42 IN EFI_PHYSICAL_ADDRESS MemoryBase,
43 IN UINT64 MemorySize
44 )
45 {
46 BuildResourceDescriptorHob (
47 EFI_RESOURCE_MEMORY_MAPPED_IO,
48 EFI_RESOURCE_ATTRIBUTE_PRESENT |
49 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
50 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
51 EFI_RESOURCE_ATTRIBUTE_TESTED,
52 MemoryBase,
53 MemorySize
54 );
55 }
56
57 VOID
58 EFIAPI
59 PlatformAddReservedMemoryBaseSizeHob (
60 IN EFI_PHYSICAL_ADDRESS MemoryBase,
61 IN UINT64 MemorySize,
62 IN BOOLEAN Cacheable
63 )
64 {
65 BuildResourceDescriptorHob (
66 EFI_RESOURCE_MEMORY_RESERVED,
67 EFI_RESOURCE_ATTRIBUTE_PRESENT |
68 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
69 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
70 (Cacheable ?
71 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
72 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
73 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
74 0
75 ) |
76 EFI_RESOURCE_ATTRIBUTE_TESTED,
77 MemoryBase,
78 MemorySize
79 );
80 }
81
82 VOID
83 EFIAPI
84 PlatformAddIoMemoryRangeHob (
85 IN EFI_PHYSICAL_ADDRESS MemoryBase,
86 IN EFI_PHYSICAL_ADDRESS MemoryLimit
87 )
88 {
89 PlatformAddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
90 }
91
92 VOID
93 EFIAPI
94 PlatformAddMemoryBaseSizeHob (
95 IN EFI_PHYSICAL_ADDRESS MemoryBase,
96 IN UINT64 MemorySize
97 )
98 {
99 BuildResourceDescriptorHob (
100 EFI_RESOURCE_SYSTEM_MEMORY,
101 EFI_RESOURCE_ATTRIBUTE_PRESENT |
102 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
103 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
104 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
105 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
106 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
107 EFI_RESOURCE_ATTRIBUTE_TESTED,
108 MemoryBase,
109 MemorySize
110 );
111 }
112
113 VOID
114 EFIAPI
115 PlatformAddMemoryRangeHob (
116 IN EFI_PHYSICAL_ADDRESS MemoryBase,
117 IN EFI_PHYSICAL_ADDRESS MemoryLimit
118 )
119 {
120 PlatformAddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
121 }
122
123 VOID
124 EFIAPI
125 PlatformMemMapInitialization (
126 IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
127 )
128 {
129 UINT64 PciIoBase;
130 UINT64 PciIoSize;
131 UINT64 PciExBarBase;
132 UINT32 PciBase;
133 UINT32 PciSize;
134
135 PciIoBase = 0xC000;
136 PciIoSize = 0x4000;
137
138 //
139 // Video memory + Legacy BIOS region
140 //
141 if (!TdIsEnabled ()) {
142 PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB);
143 }
144
145 if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) {
146 PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);
147 PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */
148 PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */
149 return;
150 }
151
152 PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);
153 PciExBarBase = 0;
154 if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
155 //
156 // The MMCONFIG area is expected to fall between the top of low RAM and
157 // the base of the 32-bit PCI host aperture.
158 //
159 PciExBarBase = PcdGet64 (PcdPciExpressBaseAddress);
160 ASSERT (PlatformInfoHob->LowMemory <= PciExBarBase);
161 ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
162 PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
163 } else {
164 ASSERT (PlatformInfoHob->LowMemory <= PlatformInfoHob->Uc32Base);
165 PciBase = PlatformInfoHob->Uc32Base;
166 }
167
168 //
169 // address purpose size
170 // ------------ -------- -------------------------
171 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
172 // 0xFC000000 gap 44 MB
173 // 0xFEC00000 IO-APIC 4 KB
174 // 0xFEC01000 gap 1020 KB
175 // 0xFED00000 HPET 1 KB
176 // 0xFED00400 gap 111 KB
177 // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
178 // 0xFED20000 gap 896 KB
179 // 0xFEE00000 LAPIC 1 MB
180 //
181 PciSize = 0xFC000000 - PciBase;
182 PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize);
183
184 PlatformInfoHob->PcdPciMmio32Base = PciBase;
185 PlatformInfoHob->PcdPciMmio32Size = PciSize;
186
187 PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
188 PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
189 if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
190 PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
191 //
192 // Note: there should be an
193 //
194 // PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
195 //
196 // call below, just like the one above for RCBA. However, Linux insists
197 // that the MMCONFIG area be marked in the E820 or UEFI memory map as
198 // "reserved memory" -- Linux does not content itself with a simple gap
199 // in the memory map wherever the MCFG ACPI table points to.
200 //
201 // This appears to be a safety measure. The PCI Firmware Specification
202 // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
203 // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
204 // [...]". (Emphasis added here.)
205 //
206 // Normally we add memory resource descriptor HOBs in
207 // QemuInitializeRam(), and pre-allocate from those with memory
208 // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
209 // is most definitely not RAM; so, as an exception, cover it with
210 // uncacheable reserved memory right here.
211 //
212 PlatformAddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
213 BuildMemoryAllocationHob (
214 PciExBarBase,
215 SIZE_256MB,
216 EfiReservedMemoryType
217 );
218 }
219
220 PlatformAddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);
221
222 //
223 // On Q35, the IO Port space is available for PCI resource allocations from
224 // 0x6000 up.
225 //
226 if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
227 PciIoBase = 0x6000;
228 PciIoSize = 0xA000;
229 ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
230 }
231
232 //
233 // Add PCI IO Port space available for PCI resource allocations.
234 //
235 BuildResourceDescriptorHob (
236 EFI_RESOURCE_IO,
237 EFI_RESOURCE_ATTRIBUTE_PRESENT |
238 EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
239 PciIoBase,
240 PciIoSize
241 );
242
243 PlatformInfoHob->PcdPciIoBase = PciIoBase;
244 PlatformInfoHob->PcdPciIoSize = PciIoSize;
245 }
246
247 /**
248 * Fetch "opt/ovmf/PcdSetNxForStack" from QEMU
249 *
250 * @param Setting The pointer to the setting of "/opt/ovmf/PcdSetNxForStack".
251 * @return EFI_SUCCESS Successfully fetch the settings.
252 */
253 EFI_STATUS
254 EFIAPI
255 PlatformNoexecDxeInitialization (
256 IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
257 )
258 {
259 return QemuFwCfgParseBool ("opt/ovmf/PcdSetNxForStack", &PlatformInfoHob->PcdSetNxForStack);
260 }
261
262 VOID
263 PciExBarInitialization (
264 VOID
265 )
266 {
267 union {
268 UINT64 Uint64;
269 UINT32 Uint32[2];
270 } PciExBarBase;
271
272 //
273 // We only support the 256MB size for the MMCONFIG area:
274 // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
275 //
276 // The masks used below enforce the Q35 requirements that the MMCONFIG area
277 // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
278 //
279 // Note that (b) also ensures that the minimum address width we have
280 // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
281 // for DXE's page tables to cover the MMCONFIG area.
282 //
283 PciExBarBase.Uint64 = PcdGet64 (PcdPciExpressBaseAddress);
284 ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
285 ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
286
287 //
288 // Clear the PCIEXBAREN bit first, before programming the high register.
289 //
290 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
291
292 //
293 // Program the high register. Then program the low register, setting the
294 // MMCONFIG area size and enabling decoding at once.
295 //
296 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
297 PciWrite32 (
298 DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
299 PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
300 );
301 }
302
303 VOID
304 EFIAPI
305 PlatformMiscInitialization (
306 IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
307 )
308 {
309 UINTN PmCmd;
310 UINTN Pmba;
311 UINT32 PmbaAndVal;
312 UINT32 PmbaOrVal;
313 UINTN AcpiCtlReg;
314 UINT8 AcpiEnBit;
315
316 //
317 // Disable A20 Mask
318 //
319 if (PlatformInfoHob->HostBridgeDevId != CLOUDHV_DEVICE_ID) {
320 IoOr8 (0x92, BIT1);
321 }
322
323 //
324 // Build the CPU HOB with guest RAM size dependent address width and 16-bits
325 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
326 // S3 resume as well, so we build it unconditionally.)
327 //
328 BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16);
329
330 //
331 // Determine platform type and save Host Bridge DID to PCD
332 //
333 switch (PlatformInfoHob->HostBridgeDevId) {
334 case INTEL_82441_DEVICE_ID:
335 PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
336 Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
337 PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
338 PmbaOrVal = PIIX4_PMBA_VALUE;
339 AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
340 AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
341 break;
342 case INTEL_Q35_MCH_DEVICE_ID:
343 PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
344 Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
345 PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
346 PmbaOrVal = ICH9_PMBASE_VALUE;
347 AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
348 AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
349 break;
350 case CLOUDHV_DEVICE_ID:
351 break;
352 default:
353 DEBUG ((
354 DEBUG_ERROR,
355 "%a: Unknown Host Bridge Device ID: 0x%04x\n",
356 __FUNCTION__,
357 PlatformInfoHob->HostBridgeDevId
358 ));
359 ASSERT (FALSE);
360 return;
361 }
362
363 if (PlatformInfoHob->HostBridgeDevId == CLOUDHV_DEVICE_ID) {
364 DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor is done.\n", __FUNCTION__));
365 return;
366 }
367
368 //
369 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has
370 // been configured and skip the setup here. This matches the logic in
371 // AcpiTimerLibConstructor ().
372 //
373 if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
374 //
375 // The PEI phase should be exited with fully accessibe ACPI PM IO space:
376 // 1. set PMBA
377 //
378 PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
379
380 //
381 // 2. set PCICMD/IOSE
382 //
383 PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
384
385 //
386 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
387 //
388 PciOr8 (AcpiCtlReg, AcpiEnBit);
389 }
390
391 if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
392 //
393 // Set Root Complex Register Block BAR
394 //
395 PciWrite32 (
396 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
397 ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
398 );
399
400 //
401 // Set PCI Express Register Range Base Address
402 //
403 PciExBarInitialization ();
404 }
405 }
406
407 /**
408 Fetch the boot CPU count and the possible CPU count from QEMU, and expose
409 them to UefiCpuPkg modules.
410 **/
411 VOID
412 EFIAPI
413 PlatformMaxCpuCountInitialization (
414 IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
415 )
416 {
417 UINT16 BootCpuCount = 0;
418 UINT32 MaxCpuCount;
419
420 //
421 // Try to fetch the boot CPU count.
422 //
423 if (QemuFwCfgIsAvailable ()) {
424 QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);
425 BootCpuCount = QemuFwCfgRead16 ();
426 }
427
428 if (BootCpuCount == 0) {
429 //
430 // QEMU doesn't report the boot CPU count. (BootCpuCount == 0) will let
431 // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or
432 // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reached
433 // first).
434 //
435 DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__));
436 MaxCpuCount = PlatformInfoHob->DefaultMaxCpuNumber;
437 } else {
438 //
439 // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs up to
440 // (BootCpuCount - 1) precisely, regardless of timeout.
441 //
442 // Now try to fetch the possible CPU count.
443 //
444 UINTN CpuHpBase;
445 UINT32 CmdData2;
446
447 CpuHpBase = ((PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?
448 ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);
449
450 //
451 // If only legacy mode is available in the CPU hotplug register block, or
452 // the register block is completely missing, then the writes below are
453 // no-ops.
454 //
455 // 1. Switch the hotplug register block to modern mode.
456 //
457 IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);
458 //
459 // 2. Select a valid CPU for deterministic reading of
460 // QEMU_CPUHP_R_CMD_DATA2.
461 //
462 // CPU#0 is always valid; it is the always present and non-removable
463 // BSP.
464 //
465 IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);
466 //
467 // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to
468 // read as zero, and which does not invalidate the selector. (The
469 // selector may change, but it must not become invalid.)
470 //
471 // Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later.
472 //
473 IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING);
474 //
475 // 4. Read QEMU_CPUHP_R_CMD_DATA2.
476 //
477 // If the register block is entirely missing, then this is an unassigned
478 // IO read, returning all-bits-one.
479 //
480 // If only legacy mode is available, then bit#0 stands for CPU#0 in the
481 // "CPU present bitmap". CPU#0 is always present.
482 //
483 // Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (returning
484 // all-bits-zero), or it is specified to read as zero after the above
485 // steps. Both cases confirm modern mode.
486 //
487 CmdData2 = IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2);
488 DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=0x%x\n", __FUNCTION__, CmdData2));
489 if (CmdData2 != 0) {
490 //
491 // QEMU doesn't support the modern CPU hotplug interface. Assume that the
492 // possible CPU count equals the boot CPU count (precluding hotplug).
493 //
494 DEBUG ((
495 DEBUG_WARN,
496 "%a: modern CPU hotplug interface unavailable\n",
497 __FUNCTION__
498 ));
499 MaxCpuCount = BootCpuCount;
500 } else {
501 //
502 // Grab the possible CPU count from the modern CPU hotplug interface.
503 //
504 UINT32 Present, Possible, Selected;
505
506 Present = 0;
507 Possible = 0;
508
509 //
510 // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures
511 // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However,
512 // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pending
513 // hotplug events; therefore, select CPU#0 forcibly.
514 //
515 IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);
516
517 do {
518 UINT8 CpuStatus;
519
520 //
521 // Read the status of the currently selected CPU. This will help with a
522 // sanity check against "BootCpuCount".
523 //
524 CpuStatus = IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT);
525 if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) != 0) {
526 ++Present;
527 }
528
529 //
530 // Attempt to select the next CPU.
531 //
532 ++Possible;
533 IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);
534 //
535 // If the selection is successful, then the following read will return
536 // the selector (which we know is positive at this point). Otherwise,
537 // the read will return 0.
538 //
539 Selected = IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA);
540 ASSERT (Selected == Possible || Selected == 0);
541 } while (Selected > 0);
542
543 //
544 // Sanity check: fw_cfg and the modern CPU hotplug interface should
545 // return the same boot CPU count.
546 //
547 if (BootCpuCount != Present) {
548 DEBUG ((
549 DEBUG_WARN,
550 "%a: QEMU v2.7 reset bug: BootCpuCount=%d "
551 "Present=%u\n",
552 __FUNCTION__,
553 BootCpuCount,
554 Present
555 ));
556 //
557 // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug plus
558 // platform reset (including S3), was corrected in QEMU commit
559 // e3cadac073a9 ("pc: fix FW_CFG_NB_CPUS to account for -device added
560 // CPUs", 2016-11-16), part of release v2.8.0.
561 //
562 BootCpuCount = (UINT16)Present;
563 }
564
565 MaxCpuCount = Possible;
566 }
567 }
568
569 DEBUG ((
570 DEBUG_INFO,
571 "%a: BootCpuCount=%d MaxCpuCount=%u\n",
572 __FUNCTION__,
573 BootCpuCount,
574 MaxCpuCount
575 ));
576 ASSERT (BootCpuCount <= MaxCpuCount);
577
578 PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber = MaxCpuCount;
579 PlatformInfoHob->PcdCpuBootLogicalProcessorNumber = BootCpuCount;
580 }
581
582 /**
583 Check padding data all bit should be 1.
584
585 @param[in] Buffer - A pointer to buffer header
586 @param[in] BufferSize - Buffer size
587
588 @retval TRUE - The padding data is valid.
589 @retval TRUE - The padding data is invalid.
590
591 **/
592 BOOLEAN
593 CheckPaddingData (
594 IN UINT8 *Buffer,
595 IN UINT32 BufferSize
596 )
597 {
598 UINT32 index;
599
600 for (index = 0; index < BufferSize; index++) {
601 if (Buffer[index] != 0xFF) {
602 return FALSE;
603 }
604 }
605
606 return TRUE;
607 }
608
609 /**
610 Check the integrity of NvVarStore.
611
612 @param[in] NvVarStoreBase - A pointer to NvVarStore header
613 @param[in] NvVarStoreSize - NvVarStore size
614
615 @retval TRUE - The NvVarStore is valid.
616 @retval FALSE - The NvVarStore is invalid.
617
618 **/
619 BOOLEAN
620 EFIAPI
621 PlatformValidateNvVarStore (
622 IN UINT8 *NvVarStoreBase,
623 IN UINT32 NvVarStoreSize
624 )
625 {
626 UINT16 Checksum;
627 UINTN VariableBase;
628 UINT32 VariableOffset;
629 UINT32 VariableOffsetBeforeAlign;
630 EFI_FIRMWARE_VOLUME_HEADER *NvVarStoreFvHeader;
631 VARIABLE_STORE_HEADER *NvVarStoreHeader;
632 AUTHENTICATED_VARIABLE_HEADER *VariableHeader;
633
634 static EFI_GUID FvHdrGUID = EFI_SYSTEM_NV_DATA_FV_GUID;
635 static EFI_GUID VarStoreHdrGUID = EFI_AUTHENTICATED_VARIABLE_GUID;
636
637 VariableOffset = 0;
638
639 if (NvVarStoreBase == NULL) {
640 DEBUG ((DEBUG_ERROR, "NvVarStore pointer is NULL.\n"));
641 return FALSE;
642 }
643
644 //
645 // Verify the header zerovetor, filesystemguid,
646 // revision, signature, attributes, fvlength, checksum
647 // HeaderLength cannot be an odd number
648 //
649 NvVarStoreFvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)NvVarStoreBase;
650
651 if ((!IsZeroBuffer (NvVarStoreFvHeader->ZeroVector, 16)) ||
652 (!CompareGuid (&FvHdrGUID, &NvVarStoreFvHeader->FileSystemGuid)) ||
653 (NvVarStoreFvHeader->Signature != EFI_FVH_SIGNATURE) ||
654 (NvVarStoreFvHeader->Attributes != 0x4feff) ||
655 ((NvVarStoreFvHeader->HeaderLength & 0x01) != 0) ||
656 (NvVarStoreFvHeader->Revision != EFI_FVH_REVISION) ||
657 (NvVarStoreFvHeader->FvLength != NvVarStoreSize)
658 )
659 {
660 DEBUG ((DEBUG_ERROR, "NvVarStore FV headers were invalid.\n"));
661 return FALSE;
662 }
663
664 //
665 // Verify the header checksum
666 //
667 Checksum = CalculateSum16 ((VOID *)NvVarStoreFvHeader, NvVarStoreFvHeader->HeaderLength);
668
669 if (Checksum != 0) {
670 DEBUG ((DEBUG_ERROR, "NvVarStore FV checksum was invalid.\n"));
671 return FALSE;
672 }
673
674 //
675 // Verify the header signature, size, format, state
676 //
677 NvVarStoreHeader = (VARIABLE_STORE_HEADER *)(NvVarStoreBase + NvVarStoreFvHeader->HeaderLength);
678 if ((!CompareGuid (&VarStoreHdrGUID, &NvVarStoreHeader->Signature)) ||
679 (NvVarStoreHeader->Format != VARIABLE_STORE_FORMATTED) ||
680 (NvVarStoreHeader->State != VARIABLE_STORE_HEALTHY) ||
681 (NvVarStoreHeader->Size > (NvVarStoreFvHeader->FvLength - NvVarStoreFvHeader->HeaderLength)) ||
682 (NvVarStoreHeader->Size < sizeof (VARIABLE_STORE_HEADER))
683 )
684 {
685 DEBUG ((DEBUG_ERROR, "NvVarStore header signature/size/format/state were invalid.\n"));
686 return FALSE;
687 }
688
689 //
690 // Verify the header startId, state
691 // Verify data to the end
692 //
693 VariableBase = (UINTN)NvVarStoreBase + NvVarStoreFvHeader->HeaderLength + sizeof (VARIABLE_STORE_HEADER);
694 while (VariableOffset < (NvVarStoreHeader->Size - sizeof (VARIABLE_STORE_HEADER))) {
695 VariableHeader = (AUTHENTICATED_VARIABLE_HEADER *)(VariableBase + VariableOffset);
696 if (VariableHeader->StartId != VARIABLE_DATA) {
697 if (!CheckPaddingData ((UINT8 *)VariableHeader, NvVarStoreHeader->Size - sizeof (VARIABLE_STORE_HEADER) - VariableOffset)) {
698 DEBUG ((DEBUG_ERROR, "NvVarStore variable header StartId was invalid.\n"));
699 return FALSE;
700 }
701
702 VariableOffset = NvVarStoreHeader->Size - sizeof (VARIABLE_STORE_HEADER);
703 } else {
704 if (!((VariableHeader->State == VAR_HEADER_VALID_ONLY) ||
705 (VariableHeader->State == VAR_ADDED) ||
706 (VariableHeader->State == (VAR_ADDED & VAR_DELETED)) ||
707 (VariableHeader->State == (VAR_ADDED & VAR_IN_DELETED_TRANSITION)) ||
708 (VariableHeader->State == (VAR_ADDED & VAR_IN_DELETED_TRANSITION & VAR_DELETED))))
709 {
710 DEBUG ((DEBUG_ERROR, "NvVarStore Variable header State was invalid.\n"));
711 return FALSE;
712 }
713
714 VariableOffset += sizeof (AUTHENTICATED_VARIABLE_HEADER) + VariableHeader->NameSize + VariableHeader->DataSize;
715 // Verify VariableOffset should be less than or equal NvVarStoreHeader->Size - sizeof(VARIABLE_STORE_HEADER)
716 if (VariableOffset > (NvVarStoreHeader->Size - sizeof (VARIABLE_STORE_HEADER))) {
717 DEBUG ((DEBUG_ERROR, "NvVarStore Variable header VariableOffset was invalid.\n"));
718 return FALSE;
719 }
720
721 VariableOffsetBeforeAlign = VariableOffset;
722 // 4 byte align
723 VariableOffset = (VariableOffset + 3) & (UINTN)(~3);
724
725 if (!CheckPaddingData ((UINT8 *)(VariableBase + VariableOffsetBeforeAlign), VariableOffset - VariableOffsetBeforeAlign)) {
726 DEBUG ((DEBUG_ERROR, "NvVarStore Variable header PaddingData was invalid.\n"));
727 return FALSE;
728 }
729 }
730 }
731
732 return TRUE;
733 }
734
735 /**
736 Allocate storage for NV variables early on so it will be
737 at a consistent address. Since VM memory is preserved
738 across reboots, this allows the NV variable storage to survive
739 a VM reboot.
740
741 *
742 * @retval VOID* The pointer to the storage for NV Variables
743 */
744 VOID *
745 EFIAPI
746 PlatformReserveEmuVariableNvStore (
747 VOID
748 )
749 {
750 VOID *VariableStore;
751 UINT32 VarStoreSize;
752
753 VarStoreSize = 2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize);
754 //
755 // Allocate storage for NV variables early on so it will be
756 // at a consistent address. Since VM memory is preserved
757 // across reboots, this allows the NV variable storage to survive
758 // a VM reboot.
759 //
760 VariableStore =
761 AllocateRuntimePages (
762 EFI_SIZE_TO_PAGES (VarStoreSize)
763 );
764 DEBUG ((
765 DEBUG_INFO,
766 "Reserved variable store memory: 0x%p; size: %dkb\n",
767 VariableStore,
768 VarStoreSize / 1024
769 ));
770
771 return VariableStore;
772 }
773
774 /**
775 When OVMF is lauched with -bios parameter, UEFI variables will be
776 partially emulated, and non-volatile variables may lose their contents
777 after a reboot. This makes the secure boot feature not working.
778
779 This function is used to initialize the EmuVariableNvStore
780 with the conent in PcdOvmfFlashNvStorageVariableBase.
781
782 @param[in] EmuVariableNvStore - A pointer to EmuVariableNvStore
783
784 @retval EFI_SUCCESS - Successfully init the EmuVariableNvStore
785 @retval Others - As the error code indicates
786 */
787 EFI_STATUS
788 EFIAPI
789 PlatformInitEmuVariableNvStore (
790 IN VOID *EmuVariableNvStore
791 )
792 {
793 UINT8 *Base;
794 UINT32 Size;
795 UINT32 EmuVariableNvStoreSize;
796
797 EmuVariableNvStoreSize = 2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize);
798 if ((EmuVariableNvStore == NULL) || (EmuVariableNvStoreSize == 0)) {
799 DEBUG ((DEBUG_ERROR, "Invalid EmuVariableNvStore parameter.\n"));
800 return EFI_INVALID_PARAMETER;
801 }
802
803 Base = (UINT8 *)(UINTN)PcdGet32 (PcdOvmfFlashNvStorageVariableBase);
804 Size = (UINT32)PcdGet32 (PcdFlashNvStorageVariableSize);
805 ASSERT (Size < EmuVariableNvStoreSize);
806
807 if (!PlatformValidateNvVarStore (Base, PcdGet32 (PcdCfvRawDataSize))) {
808 ASSERT (FALSE);
809 return EFI_INVALID_PARAMETER;
810 }
811
812 DEBUG ((DEBUG_INFO, "Init EmuVariableNvStore with the content in FlashNvStorage\n"));
813
814 CopyMem (EmuVariableNvStore, Base, Size);
815
816 return EFI_SUCCESS;
817 }
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