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UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm
[mirror_edk2.git] / OvmfPkg / Library / PlatformInitLib / Platform.c
1 /**@file
2
3 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
4 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
5
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 **/
9
10 //
11 // The package level header files this module uses
12 //
13 #include <PiPei.h>
14
15 //
16 // The Library classes this module consumes
17 //
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/BaseLib.h>
20 #include <Library/DebugLib.h>
21 #include <Library/HobLib.h>
22 #include <Library/IoLib.h>
23 #include <IndustryStandard/I440FxPiix4.h>
24 #include <IndustryStandard/Microvm.h>
25 #include <IndustryStandard/Pci22.h>
26 #include <IndustryStandard/Q35MchIch9.h>
27 #include <IndustryStandard/QemuCpuHotplug.h>
28 #include <Library/QemuFwCfgLib.h>
29 #include <Library/QemuFwCfgS3Lib.h>
30 #include <Library/QemuFwCfgSimpleParserLib.h>
31 #include <Library/PciLib.h>
32 #include <OvmfPlatforms.h>
33
34 #include <Library/PlatformInitLib.h>
35
36 VOID
37 EFIAPI
38 PlatformAddIoMemoryBaseSizeHob (
39 IN EFI_PHYSICAL_ADDRESS MemoryBase,
40 IN UINT64 MemorySize
41 )
42 {
43 BuildResourceDescriptorHob (
44 EFI_RESOURCE_MEMORY_MAPPED_IO,
45 EFI_RESOURCE_ATTRIBUTE_PRESENT |
46 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
47 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
48 EFI_RESOURCE_ATTRIBUTE_TESTED,
49 MemoryBase,
50 MemorySize
51 );
52 }
53
54 VOID
55 EFIAPI
56 PlatformAddReservedMemoryBaseSizeHob (
57 IN EFI_PHYSICAL_ADDRESS MemoryBase,
58 IN UINT64 MemorySize,
59 IN BOOLEAN Cacheable
60 )
61 {
62 BuildResourceDescriptorHob (
63 EFI_RESOURCE_MEMORY_RESERVED,
64 EFI_RESOURCE_ATTRIBUTE_PRESENT |
65 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
66 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
67 (Cacheable ?
68 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
69 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
70 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
71 0
72 ) |
73 EFI_RESOURCE_ATTRIBUTE_TESTED,
74 MemoryBase,
75 MemorySize
76 );
77 }
78
79 VOID
80 EFIAPI
81 PlatformAddIoMemoryRangeHob (
82 IN EFI_PHYSICAL_ADDRESS MemoryBase,
83 IN EFI_PHYSICAL_ADDRESS MemoryLimit
84 )
85 {
86 PlatformAddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
87 }
88
89 VOID
90 EFIAPI
91 PlatformAddMemoryBaseSizeHob (
92 IN EFI_PHYSICAL_ADDRESS MemoryBase,
93 IN UINT64 MemorySize
94 )
95 {
96 BuildResourceDescriptorHob (
97 EFI_RESOURCE_SYSTEM_MEMORY,
98 EFI_RESOURCE_ATTRIBUTE_PRESENT |
99 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
100 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
101 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
102 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
103 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
104 EFI_RESOURCE_ATTRIBUTE_TESTED,
105 MemoryBase,
106 MemorySize
107 );
108 }
109
110 VOID
111 EFIAPI
112 PlatformAddMemoryRangeHob (
113 IN EFI_PHYSICAL_ADDRESS MemoryBase,
114 IN EFI_PHYSICAL_ADDRESS MemoryLimit
115 )
116 {
117 PlatformAddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
118 }
119
120 VOID
121 EFIAPI
122 PlatformMemMapInitialization (
123 IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
124 )
125 {
126 UINT64 PciIoBase;
127 UINT64 PciIoSize;
128 UINT32 TopOfLowRam;
129 UINT64 PciExBarBase;
130 UINT32 PciBase;
131 UINT32 PciSize;
132
133 PciIoBase = 0xC000;
134 PciIoSize = 0x4000;
135
136 //
137 // Video memory + Legacy BIOS region
138 //
139 if (!TdIsEnabled ()) {
140 PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB);
141 }
142
143 if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) {
144 PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);
145 PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */
146 PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */
147 return;
148 }
149
150 TopOfLowRam = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);
151 PciExBarBase = 0;
152 if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
153 //
154 // The MMCONFIG area is expected to fall between the top of low RAM and
155 // the base of the 32-bit PCI host aperture.
156 //
157 PciExBarBase = PcdGet64 (PcdPciExpressBaseAddress);
158 ASSERT (TopOfLowRam <= PciExBarBase);
159 ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
160 PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
161 } else {
162 ASSERT (TopOfLowRam <= PlatformInfoHob->Uc32Base);
163 PciBase = PlatformInfoHob->Uc32Base;
164 }
165
166 //
167 // address purpose size
168 // ------------ -------- -------------------------
169 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
170 // 0xFC000000 gap 44 MB
171 // 0xFEC00000 IO-APIC 4 KB
172 // 0xFEC01000 gap 1020 KB
173 // 0xFED00000 HPET 1 KB
174 // 0xFED00400 gap 111 KB
175 // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
176 // 0xFED20000 gap 896 KB
177 // 0xFEE00000 LAPIC 1 MB
178 //
179 PciSize = 0xFC000000 - PciBase;
180 PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize);
181
182 PlatformInfoHob->PcdPciMmio32Base = PciBase;
183 PlatformInfoHob->PcdPciMmio32Size = PciSize;
184
185 PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
186 PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
187 if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
188 PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
189 //
190 // Note: there should be an
191 //
192 // PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
193 //
194 // call below, just like the one above for RCBA. However, Linux insists
195 // that the MMCONFIG area be marked in the E820 or UEFI memory map as
196 // "reserved memory" -- Linux does not content itself with a simple gap
197 // in the memory map wherever the MCFG ACPI table points to.
198 //
199 // This appears to be a safety measure. The PCI Firmware Specification
200 // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
201 // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
202 // [...]". (Emphasis added here.)
203 //
204 // Normally we add memory resource descriptor HOBs in
205 // QemuInitializeRam(), and pre-allocate from those with memory
206 // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
207 // is most definitely not RAM; so, as an exception, cover it with
208 // uncacheable reserved memory right here.
209 //
210 PlatformAddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
211 BuildMemoryAllocationHob (
212 PciExBarBase,
213 SIZE_256MB,
214 EfiReservedMemoryType
215 );
216 }
217
218 PlatformAddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);
219
220 //
221 // On Q35, the IO Port space is available for PCI resource allocations from
222 // 0x6000 up.
223 //
224 if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
225 PciIoBase = 0x6000;
226 PciIoSize = 0xA000;
227 ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
228 }
229
230 //
231 // Add PCI IO Port space available for PCI resource allocations.
232 //
233 BuildResourceDescriptorHob (
234 EFI_RESOURCE_IO,
235 EFI_RESOURCE_ATTRIBUTE_PRESENT |
236 EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
237 PciIoBase,
238 PciIoSize
239 );
240
241 PlatformInfoHob->PcdPciIoBase = PciIoBase;
242 PlatformInfoHob->PcdPciIoSize = PciIoSize;
243 }
244
245 /**
246 * Fetch "opt/ovmf/PcdSetNxForStack" from QEMU
247 *
248 * @param Setting The pointer to the setting of "/opt/ovmf/PcdSetNxForStack".
249 * @return EFI_SUCCESS Successfully fetch the settings.
250 */
251 EFI_STATUS
252 EFIAPI
253 PlatformNoexecDxeInitialization (
254 IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
255 )
256 {
257 return QemuFwCfgParseBool ("opt/ovmf/PcdSetNxForStack", &PlatformInfoHob->PcdSetNxForStack);
258 }
259
260 VOID
261 PciExBarInitialization (
262 VOID
263 )
264 {
265 union {
266 UINT64 Uint64;
267 UINT32 Uint32[2];
268 } PciExBarBase;
269
270 //
271 // We only support the 256MB size for the MMCONFIG area:
272 // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
273 //
274 // The masks used below enforce the Q35 requirements that the MMCONFIG area
275 // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
276 //
277 // Note that (b) also ensures that the minimum address width we have
278 // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
279 // for DXE's page tables to cover the MMCONFIG area.
280 //
281 PciExBarBase.Uint64 = PcdGet64 (PcdPciExpressBaseAddress);
282 ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
283 ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
284
285 //
286 // Clear the PCIEXBAREN bit first, before programming the high register.
287 //
288 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
289
290 //
291 // Program the high register. Then program the low register, setting the
292 // MMCONFIG area size and enabling decoding at once.
293 //
294 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
295 PciWrite32 (
296 DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
297 PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
298 );
299 }
300
301 VOID
302 EFIAPI
303 PlatformMiscInitialization (
304 IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
305 )
306 {
307 UINTN PmCmd;
308 UINTN Pmba;
309 UINT32 PmbaAndVal;
310 UINT32 PmbaOrVal;
311 UINTN AcpiCtlReg;
312 UINT8 AcpiEnBit;
313
314 //
315 // Disable A20 Mask
316 //
317 if (PlatformInfoHob->HostBridgeDevId != CLOUDHV_DEVICE_ID) {
318 IoOr8 (0x92, BIT1);
319 }
320
321 //
322 // Build the CPU HOB with guest RAM size dependent address width and 16-bits
323 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
324 // S3 resume as well, so we build it unconditionally.)
325 //
326 BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16);
327
328 //
329 // Determine platform type and save Host Bridge DID to PCD
330 //
331 switch (PlatformInfoHob->HostBridgeDevId) {
332 case INTEL_82441_DEVICE_ID:
333 PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
334 Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
335 PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
336 PmbaOrVal = PIIX4_PMBA_VALUE;
337 AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
338 AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
339 break;
340 case INTEL_Q35_MCH_DEVICE_ID:
341 PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
342 Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
343 PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
344 PmbaOrVal = ICH9_PMBASE_VALUE;
345 AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
346 AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
347 break;
348 case CLOUDHV_DEVICE_ID:
349 break;
350 default:
351 DEBUG ((
352 DEBUG_ERROR,
353 "%a: Unknown Host Bridge Device ID: 0x%04x\n",
354 __FUNCTION__,
355 PlatformInfoHob->HostBridgeDevId
356 ));
357 ASSERT (FALSE);
358 return;
359 }
360
361 if (PlatformInfoHob->HostBridgeDevId == CLOUDHV_DEVICE_ID) {
362 DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor is done.\n", __FUNCTION__));
363 return;
364 }
365
366 //
367 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has
368 // been configured and skip the setup here. This matches the logic in
369 // AcpiTimerLibConstructor ().
370 //
371 if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
372 //
373 // The PEI phase should be exited with fully accessibe ACPI PM IO space:
374 // 1. set PMBA
375 //
376 PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
377
378 //
379 // 2. set PCICMD/IOSE
380 //
381 PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
382
383 //
384 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
385 //
386 PciOr8 (AcpiCtlReg, AcpiEnBit);
387 }
388
389 if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
390 //
391 // Set Root Complex Register Block BAR
392 //
393 PciWrite32 (
394 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
395 ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
396 );
397
398 //
399 // Set PCI Express Register Range Base Address
400 //
401 PciExBarInitialization ();
402 }
403 }
404
405 /**
406 Fetch the boot CPU count and the possible CPU count from QEMU, and expose
407 them to UefiCpuPkg modules.
408 **/
409 VOID
410 EFIAPI
411 PlatformMaxCpuCountInitialization (
412 IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
413 )
414 {
415 UINT16 BootCpuCount = 0;
416 UINT32 MaxCpuCount;
417
418 //
419 // Try to fetch the boot CPU count.
420 //
421 if (QemuFwCfgIsAvailable ()) {
422 QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);
423 BootCpuCount = QemuFwCfgRead16 ();
424 }
425
426 if (BootCpuCount == 0) {
427 //
428 // QEMU doesn't report the boot CPU count. (BootCpuCount == 0) will let
429 // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or
430 // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reached
431 // first).
432 //
433 DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__));
434 MaxCpuCount = PlatformInfoHob->DefaultMaxCpuNumber;
435 } else {
436 //
437 // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs up to
438 // (BootCpuCount - 1) precisely, regardless of timeout.
439 //
440 // Now try to fetch the possible CPU count.
441 //
442 UINTN CpuHpBase;
443 UINT32 CmdData2;
444
445 CpuHpBase = ((PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?
446 ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);
447
448 //
449 // If only legacy mode is available in the CPU hotplug register block, or
450 // the register block is completely missing, then the writes below are
451 // no-ops.
452 //
453 // 1. Switch the hotplug register block to modern mode.
454 //
455 IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);
456 //
457 // 2. Select a valid CPU for deterministic reading of
458 // QEMU_CPUHP_R_CMD_DATA2.
459 //
460 // CPU#0 is always valid; it is the always present and non-removable
461 // BSP.
462 //
463 IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);
464 //
465 // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to
466 // read as zero, and which does not invalidate the selector. (The
467 // selector may change, but it must not become invalid.)
468 //
469 // Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later.
470 //
471 IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING);
472 //
473 // 4. Read QEMU_CPUHP_R_CMD_DATA2.
474 //
475 // If the register block is entirely missing, then this is an unassigned
476 // IO read, returning all-bits-one.
477 //
478 // If only legacy mode is available, then bit#0 stands for CPU#0 in the
479 // "CPU present bitmap". CPU#0 is always present.
480 //
481 // Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (returning
482 // all-bits-zero), or it is specified to read as zero after the above
483 // steps. Both cases confirm modern mode.
484 //
485 CmdData2 = IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2);
486 DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=0x%x\n", __FUNCTION__, CmdData2));
487 if (CmdData2 != 0) {
488 //
489 // QEMU doesn't support the modern CPU hotplug interface. Assume that the
490 // possible CPU count equals the boot CPU count (precluding hotplug).
491 //
492 DEBUG ((
493 DEBUG_WARN,
494 "%a: modern CPU hotplug interface unavailable\n",
495 __FUNCTION__
496 ));
497 MaxCpuCount = BootCpuCount;
498 } else {
499 //
500 // Grab the possible CPU count from the modern CPU hotplug interface.
501 //
502 UINT32 Present, Possible, Selected;
503
504 Present = 0;
505 Possible = 0;
506
507 //
508 // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures
509 // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However,
510 // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pending
511 // hotplug events; therefore, select CPU#0 forcibly.
512 //
513 IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);
514
515 do {
516 UINT8 CpuStatus;
517
518 //
519 // Read the status of the currently selected CPU. This will help with a
520 // sanity check against "BootCpuCount".
521 //
522 CpuStatus = IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT);
523 if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) != 0) {
524 ++Present;
525 }
526
527 //
528 // Attempt to select the next CPU.
529 //
530 ++Possible;
531 IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);
532 //
533 // If the selection is successful, then the following read will return
534 // the selector (which we know is positive at this point). Otherwise,
535 // the read will return 0.
536 //
537 Selected = IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA);
538 ASSERT (Selected == Possible || Selected == 0);
539 } while (Selected > 0);
540
541 //
542 // Sanity check: fw_cfg and the modern CPU hotplug interface should
543 // return the same boot CPU count.
544 //
545 if (BootCpuCount != Present) {
546 DEBUG ((
547 DEBUG_WARN,
548 "%a: QEMU v2.7 reset bug: BootCpuCount=%d "
549 "Present=%u\n",
550 __FUNCTION__,
551 BootCpuCount,
552 Present
553 ));
554 //
555 // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug plus
556 // platform reset (including S3), was corrected in QEMU commit
557 // e3cadac073a9 ("pc: fix FW_CFG_NB_CPUS to account for -device added
558 // CPUs", 2016-11-16), part of release v2.8.0.
559 //
560 BootCpuCount = (UINT16)Present;
561 }
562
563 MaxCpuCount = Possible;
564 }
565 }
566
567 DEBUG ((
568 DEBUG_INFO,
569 "%a: BootCpuCount=%d MaxCpuCount=%u\n",
570 __FUNCTION__,
571 BootCpuCount,
572 MaxCpuCount
573 ));
574 ASSERT (BootCpuCount <= MaxCpuCount);
575
576 PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber = MaxCpuCount;
577 PlatformInfoHob->PcdCpuBootLogicalProcessorNumber = BootCpuCount;
578 }
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