3 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
4 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
11 // The package level header files this module uses
16 // The Library classes this module consumes
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/BaseLib.h>
20 #include <Library/DebugLib.h>
21 #include <Library/HobLib.h>
22 #include <Library/IoLib.h>
23 #include <IndustryStandard/I440FxPiix4.h>
24 #include <IndustryStandard/Microvm.h>
25 #include <IndustryStandard/Pci22.h>
26 #include <IndustryStandard/Q35MchIch9.h>
27 #include <IndustryStandard/QemuCpuHotplug.h>
28 #include <Library/MemoryAllocationLib.h>
29 #include <Library/QemuFwCfgLib.h>
30 #include <Library/QemuFwCfgS3Lib.h>
31 #include <Library/QemuFwCfgSimpleParserLib.h>
32 #include <Library/PciLib.h>
33 #include <Guid/SystemNvDataGuid.h>
34 #include <Guid/VariableFormat.h>
35 #include <OvmfPlatforms.h>
37 #include <Library/PlatformInitLib.h>
41 PlatformAddIoMemoryBaseSizeHob (
42 IN EFI_PHYSICAL_ADDRESS MemoryBase
,
46 BuildResourceDescriptorHob (
47 EFI_RESOURCE_MEMORY_MAPPED_IO
,
48 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
49 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
50 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
51 EFI_RESOURCE_ATTRIBUTE_TESTED
,
59 PlatformAddReservedMemoryBaseSizeHob (
60 IN EFI_PHYSICAL_ADDRESS MemoryBase
,
65 BuildResourceDescriptorHob (
66 EFI_RESOURCE_MEMORY_RESERVED
,
67 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
68 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
69 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
71 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
72 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
73 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
:
76 EFI_RESOURCE_ATTRIBUTE_TESTED
,
84 PlatformAddIoMemoryRangeHob (
85 IN EFI_PHYSICAL_ADDRESS MemoryBase
,
86 IN EFI_PHYSICAL_ADDRESS MemoryLimit
89 PlatformAddIoMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
94 PlatformAddMemoryBaseSizeHob (
95 IN EFI_PHYSICAL_ADDRESS MemoryBase
,
99 BuildResourceDescriptorHob (
100 EFI_RESOURCE_SYSTEM_MEMORY
,
101 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
102 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
103 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
104 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
105 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
106 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
|
107 EFI_RESOURCE_ATTRIBUTE_TESTED
,
115 PlatformAddMemoryRangeHob (
116 IN EFI_PHYSICAL_ADDRESS MemoryBase
,
117 IN EFI_PHYSICAL_ADDRESS MemoryLimit
120 PlatformAddMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
125 PlatformMemMapInitialization (
126 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
139 // Video memory + Legacy BIOS region
141 if (!TdIsEnabled ()) {
142 PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB
);
145 if (PlatformInfoHob
->HostBridgeDevId
== 0xffff /* microvm */) {
146 PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE
, SIZE_4KB
);
147 PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB
); /* ioapic #1 */
148 PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB
); /* ioapic #2 */
152 PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob
);
154 if (PlatformInfoHob
->HostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
156 // The MMCONFIG area is expected to fall between the top of low RAM and
157 // the base of the 32-bit PCI host aperture.
159 PciExBarBase
= PcdGet64 (PcdPciExpressBaseAddress
);
160 ASSERT (PlatformInfoHob
->LowMemory
<= PciExBarBase
);
161 ASSERT (PciExBarBase
<= MAX_UINT32
- SIZE_256MB
);
162 PciBase
= (UINT32
)(PciExBarBase
+ SIZE_256MB
);
164 ASSERT (PlatformInfoHob
->LowMemory
<= PlatformInfoHob
->Uc32Base
);
165 PciBase
= PlatformInfoHob
->Uc32Base
;
169 // address purpose size
170 // ------------ -------- -------------------------
171 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
172 // 0xFC000000 gap 44 MB
173 // 0xFEC00000 IO-APIC 4 KB
174 // 0xFEC01000 gap 1020 KB
175 // 0xFED00000 HPET 1 KB
176 // 0xFED00400 gap 111 KB
177 // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
178 // 0xFED20000 gap 896 KB
179 // 0xFEE00000 LAPIC 1 MB
181 PciSize
= 0xFC000000 - PciBase
;
182 PlatformAddIoMemoryBaseSizeHob (PciBase
, PciSize
);
184 PlatformInfoHob
->PcdPciMmio32Base
= PciBase
;
185 PlatformInfoHob
->PcdPciMmio32Size
= PciSize
;
187 PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB
);
188 PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB
);
189 if (PlatformInfoHob
->HostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
190 PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE
, SIZE_16KB
);
192 // Note: there should be an
194 // PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
196 // call below, just like the one above for RCBA. However, Linux insists
197 // that the MMCONFIG area be marked in the E820 or UEFI memory map as
198 // "reserved memory" -- Linux does not content itself with a simple gap
199 // in the memory map wherever the MCFG ACPI table points to.
201 // This appears to be a safety measure. The PCI Firmware Specification
202 // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
203 // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
204 // [...]". (Emphasis added here.)
206 // Normally we add memory resource descriptor HOBs in
207 // QemuInitializeRam(), and pre-allocate from those with memory
208 // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
209 // is most definitely not RAM; so, as an exception, cover it with
210 // uncacheable reserved memory right here.
212 PlatformAddReservedMemoryBaseSizeHob (PciExBarBase
, SIZE_256MB
, FALSE
);
213 BuildMemoryAllocationHob (
216 EfiReservedMemoryType
220 PlatformAddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress
), SIZE_1MB
);
223 // On Q35, the IO Port space is available for PCI resource allocations from
226 if (PlatformInfoHob
->HostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
229 ASSERT ((ICH9_PMBASE_VALUE
& 0xF000) < PciIoBase
);
233 // Add PCI IO Port space available for PCI resource allocations.
235 BuildResourceDescriptorHob (
237 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
238 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
,
243 PlatformInfoHob
->PcdPciIoBase
= PciIoBase
;
244 PlatformInfoHob
->PcdPciIoSize
= PciIoSize
;
248 * Fetch "opt/ovmf/PcdSetNxForStack" from QEMU
250 * @param Setting The pointer to the setting of "/opt/ovmf/PcdSetNxForStack".
251 * @return EFI_SUCCESS Successfully fetch the settings.
255 PlatformNoexecDxeInitialization (
256 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
259 return QemuFwCfgParseBool ("opt/ovmf/PcdSetNxForStack", &PlatformInfoHob
->PcdSetNxForStack
);
263 PciExBarInitialization (
273 // We only support the 256MB size for the MMCONFIG area:
274 // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
276 // The masks used below enforce the Q35 requirements that the MMCONFIG area
277 // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
279 // Note that (b) also ensures that the minimum address width we have
280 // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
281 // for DXE's page tables to cover the MMCONFIG area.
283 PciExBarBase
.Uint64
= PcdGet64 (PcdPciExpressBaseAddress
);
284 ASSERT ((PciExBarBase
.Uint32
[1] & MCH_PCIEXBAR_HIGHMASK
) == 0);
285 ASSERT ((PciExBarBase
.Uint32
[0] & MCH_PCIEXBAR_LOWMASK
) == 0);
288 // Clear the PCIEXBAREN bit first, before programming the high register.
290 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW
), 0);
293 // Program the high register. Then program the low register, setting the
294 // MMCONFIG area size and enabling decoding at once.
296 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH
), PciExBarBase
.Uint32
[1]);
298 DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW
),
299 PciExBarBase
.Uint32
[0] | MCH_PCIEXBAR_BUS_FF
| MCH_PCIEXBAR_EN
305 PlatformMiscInitialization (
306 IN EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
319 if (PlatformInfoHob
->HostBridgeDevId
!= CLOUDHV_DEVICE_ID
) {
324 // Build the CPU HOB with guest RAM size dependent address width and 16-bits
325 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
326 // S3 resume as well, so we build it unconditionally.)
328 BuildCpuHob (PlatformInfoHob
->PhysMemAddressWidth
, 16);
331 // Determine platform type and save Host Bridge DID to PCD
333 switch (PlatformInfoHob
->HostBridgeDevId
) {
334 case INTEL_82441_DEVICE_ID
:
335 PmCmd
= POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET
);
336 Pmba
= POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA
);
337 PmbaAndVal
= ~(UINT32
)PIIX4_PMBA_MASK
;
338 PmbaOrVal
= PIIX4_PMBA_VALUE
;
339 AcpiCtlReg
= POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC
);
340 AcpiEnBit
= PIIX4_PMREGMISC_PMIOSE
;
342 case INTEL_Q35_MCH_DEVICE_ID
:
343 PmCmd
= POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET
);
344 Pmba
= POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE
);
345 PmbaAndVal
= ~(UINT32
)ICH9_PMBASE_MASK
;
346 PmbaOrVal
= ICH9_PMBASE_VALUE
;
347 AcpiCtlReg
= POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL
);
348 AcpiEnBit
= ICH9_ACPI_CNTL_ACPI_EN
;
350 case CLOUDHV_DEVICE_ID
:
355 "%a: Unknown Host Bridge Device ID: 0x%04x\n",
357 PlatformInfoHob
->HostBridgeDevId
363 if (PlatformInfoHob
->HostBridgeDevId
== CLOUDHV_DEVICE_ID
) {
364 DEBUG ((DEBUG_INFO
, "%a: Cloud Hypervisor is done.\n", __FUNCTION__
));
369 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has
370 // been configured and skip the setup here. This matches the logic in
371 // AcpiTimerLibConstructor ().
373 if ((PciRead8 (AcpiCtlReg
) & AcpiEnBit
) == 0) {
375 // The PEI phase should be exited with fully accessibe ACPI PM IO space:
378 PciAndThenOr32 (Pmba
, PmbaAndVal
, PmbaOrVal
);
381 // 2. set PCICMD/IOSE
383 PciOr8 (PmCmd
, EFI_PCI_COMMAND_IO_SPACE
);
386 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
388 PciOr8 (AcpiCtlReg
, AcpiEnBit
);
391 if (PlatformInfoHob
->HostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
393 // Set Root Complex Register Block BAR
396 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA
),
397 ICH9_ROOT_COMPLEX_BASE
| ICH9_RCBA_EN
401 // Set PCI Express Register Range Base Address
403 PciExBarInitialization ();
408 Check for various QEMU bugs concerning CPU numbers.
410 Compensate for those bugs if various conditions are satisfied, by updating a
411 suitable subset of the input-output parameters. The function may not return
412 (it may hang deliberately), even in RELEASE builds, if the QEMU bug is
413 impossible to cover up.
415 @param[in,out] BootCpuCount On input, the boot CPU count reported by QEMU via
416 fw_cfg (QemuFwCfgItemSmpCpuCount). The caller is
417 responsible for ensuring (BootCpuCount > 0); that
418 is, if QEMU does not provide the boot CPU count
419 via fw_cfg *at all*, then this function must not
422 @param[in,out] Present On input, the number of present-at-boot CPUs, as
423 reported by QEMU through the modern CPU hotplug
426 @param[in,out] Possible On input, the number of possible CPUs, as
427 reported by QEMU through the modern CPU hotplug
432 PlatformCpuCountBugCheck (
433 IN OUT UINT16
*BootCpuCount
,
434 IN OUT UINT32
*Present
,
435 IN OUT UINT32
*Possible
438 ASSERT (*BootCpuCount
> 0);
441 // Sanity check: fw_cfg and the modern CPU hotplug interface should expose the
442 // same boot CPU count.
444 if (*BootCpuCount
!= *Present
) {
447 "%a: QEMU v2.7 reset bug: BootCpuCount=%d Present=%u\n",
453 // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug plus
454 // platform reset (including S3), was corrected in QEMU commit e3cadac073a9
455 // ("pc: fix FW_CFG_NB_CPUS to account for -device added CPUs", 2016-11-16),
456 // part of release v2.8.0.
458 *BootCpuCount
= (UINT16
)*Present
;
463 Fetch the boot CPU count and the possible CPU count from QEMU, and expose
464 them to UefiCpuPkg modules.
468 PlatformMaxCpuCountInitialization (
469 IN OUT EFI_HOB_PLATFORM_INFO
*PlatformInfoHob
472 UINT16 BootCpuCount
= 0;
476 // Try to fetch the boot CPU count.
478 if (QemuFwCfgIsAvailable ()) {
479 QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount
);
480 BootCpuCount
= QemuFwCfgRead16 ();
483 if (BootCpuCount
== 0) {
485 // QEMU doesn't report the boot CPU count. (BootCpuCount == 0) will let
486 // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or
487 // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reached
490 DEBUG ((DEBUG_WARN
, "%a: boot CPU count unavailable\n", __FUNCTION__
));
491 MaxCpuCount
= PlatformInfoHob
->DefaultMaxCpuNumber
;
494 // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs up to
495 // (BootCpuCount - 1) precisely, regardless of timeout.
497 // Now try to fetch the possible CPU count.
502 CpuHpBase
= ((PlatformInfoHob
->HostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) ?
503 ICH9_CPU_HOTPLUG_BASE
: PIIX4_CPU_HOTPLUG_BASE
);
506 // If only legacy mode is available in the CPU hotplug register block, or
507 // the register block is completely missing, then the writes below are
510 // 1. Switch the hotplug register block to modern mode.
512 IoWrite32 (CpuHpBase
+ QEMU_CPUHP_W_CPU_SEL
, 0);
514 // 2. Select a valid CPU for deterministic reading of
515 // QEMU_CPUHP_R_CMD_DATA2.
517 // CPU#0 is always valid; it is the always present and non-removable
520 IoWrite32 (CpuHpBase
+ QEMU_CPUHP_W_CPU_SEL
, 0);
522 // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to
523 // read as zero, and which does not invalidate the selector. (The
524 // selector may change, but it must not become invalid.)
526 // Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later.
528 IoWrite8 (CpuHpBase
+ QEMU_CPUHP_W_CMD
, QEMU_CPUHP_CMD_GET_PENDING
);
530 // 4. Read QEMU_CPUHP_R_CMD_DATA2.
532 // If the register block is entirely missing, then this is an unassigned
533 // IO read, returning all-bits-one.
535 // If only legacy mode is available, then bit#0 stands for CPU#0 in the
536 // "CPU present bitmap". CPU#0 is always present.
538 // Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (returning
539 // all-bits-zero), or it is specified to read as zero after the above
540 // steps. Both cases confirm modern mode.
542 CmdData2
= IoRead32 (CpuHpBase
+ QEMU_CPUHP_R_CMD_DATA2
);
543 DEBUG ((DEBUG_VERBOSE
, "%a: CmdData2=0x%x\n", __FUNCTION__
, CmdData2
));
546 // QEMU doesn't support the modern CPU hotplug interface. Assume that the
547 // possible CPU count equals the boot CPU count (precluding hotplug).
551 "%a: modern CPU hotplug interface unavailable\n",
554 MaxCpuCount
= BootCpuCount
;
557 // Grab the possible CPU count from the modern CPU hotplug interface.
559 UINT32 Present
, Possible
, Selected
;
565 // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures
566 // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However,
567 // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pending
568 // hotplug events; therefore, select CPU#0 forcibly.
570 IoWrite32 (CpuHpBase
+ QEMU_CPUHP_W_CPU_SEL
, Possible
);
576 // Read the status of the currently selected CPU. This will help with
577 // various CPU count sanity checks.
579 CpuStatus
= IoRead8 (CpuHpBase
+ QEMU_CPUHP_R_CPU_STAT
);
580 if ((CpuStatus
& QEMU_CPUHP_STAT_ENABLED
) != 0) {
585 // Attempt to select the next CPU.
588 IoWrite32 (CpuHpBase
+ QEMU_CPUHP_W_CPU_SEL
, Possible
);
590 // If the selection is successful, then the following read will return
591 // the selector (which we know is positive at this point). Otherwise,
592 // the read will return 0.
594 Selected
= IoRead32 (CpuHpBase
+ QEMU_CPUHP_RW_CMD_DATA
);
595 ASSERT (Selected
== Possible
|| Selected
== 0);
596 } while (Selected
> 0);
598 PlatformCpuCountBugCheck (&BootCpuCount
, &Present
, &Possible
);
600 MaxCpuCount
= Possible
;
606 "%a: BootCpuCount=%d MaxCpuCount=%u\n",
611 ASSERT (BootCpuCount
<= MaxCpuCount
);
613 PlatformInfoHob
->PcdCpuMaxLogicalProcessorNumber
= MaxCpuCount
;
614 PlatformInfoHob
->PcdCpuBootLogicalProcessorNumber
= BootCpuCount
;
618 Check padding data all bit should be 1.
620 @param[in] Buffer - A pointer to buffer header
621 @param[in] BufferSize - Buffer size
623 @retval TRUE - The padding data is valid.
624 @retval TRUE - The padding data is invalid.
635 for (index
= 0; index
< BufferSize
; index
++) {
636 if (Buffer
[index
] != 0xFF) {
645 Check the integrity of NvVarStore.
647 @param[in] NvVarStoreBase - A pointer to NvVarStore header
648 @param[in] NvVarStoreSize - NvVarStore size
650 @retval TRUE - The NvVarStore is valid.
651 @retval FALSE - The NvVarStore is invalid.
656 PlatformValidateNvVarStore (
657 IN UINT8
*NvVarStoreBase
,
658 IN UINT32 NvVarStoreSize
663 UINT32 VariableOffset
;
664 UINT32 VariableOffsetBeforeAlign
;
665 EFI_FIRMWARE_VOLUME_HEADER
*NvVarStoreFvHeader
;
666 VARIABLE_STORE_HEADER
*NvVarStoreHeader
;
667 AUTHENTICATED_VARIABLE_HEADER
*VariableHeader
;
669 static EFI_GUID FvHdrGUID
= EFI_SYSTEM_NV_DATA_FV_GUID
;
670 static EFI_GUID VarStoreHdrGUID
= EFI_AUTHENTICATED_VARIABLE_GUID
;
674 if (NvVarStoreBase
== NULL
) {
675 DEBUG ((DEBUG_ERROR
, "NvVarStore pointer is NULL.\n"));
680 // Verify the header zerovetor, filesystemguid,
681 // revision, signature, attributes, fvlength, checksum
682 // HeaderLength cannot be an odd number
684 NvVarStoreFvHeader
= (EFI_FIRMWARE_VOLUME_HEADER
*)NvVarStoreBase
;
686 if ((!IsZeroBuffer (NvVarStoreFvHeader
->ZeroVector
, 16)) ||
687 (!CompareGuid (&FvHdrGUID
, &NvVarStoreFvHeader
->FileSystemGuid
)) ||
688 (NvVarStoreFvHeader
->Signature
!= EFI_FVH_SIGNATURE
) ||
689 (NvVarStoreFvHeader
->Attributes
!= 0x4feff) ||
690 ((NvVarStoreFvHeader
->HeaderLength
& 0x01) != 0) ||
691 (NvVarStoreFvHeader
->Revision
!= EFI_FVH_REVISION
) ||
692 (NvVarStoreFvHeader
->FvLength
!= NvVarStoreSize
)
695 DEBUG ((DEBUG_ERROR
, "NvVarStore FV headers were invalid.\n"));
700 // Verify the header checksum
702 Checksum
= CalculateSum16 ((VOID
*)NvVarStoreFvHeader
, NvVarStoreFvHeader
->HeaderLength
);
705 DEBUG ((DEBUG_ERROR
, "NvVarStore FV checksum was invalid.\n"));
710 // Verify the header signature, size, format, state
712 NvVarStoreHeader
= (VARIABLE_STORE_HEADER
*)(NvVarStoreBase
+ NvVarStoreFvHeader
->HeaderLength
);
713 if ((!CompareGuid (&VarStoreHdrGUID
, &NvVarStoreHeader
->Signature
)) ||
714 (NvVarStoreHeader
->Format
!= VARIABLE_STORE_FORMATTED
) ||
715 (NvVarStoreHeader
->State
!= VARIABLE_STORE_HEALTHY
) ||
716 (NvVarStoreHeader
->Size
> (NvVarStoreFvHeader
->FvLength
- NvVarStoreFvHeader
->HeaderLength
)) ||
717 (NvVarStoreHeader
->Size
< sizeof (VARIABLE_STORE_HEADER
))
720 DEBUG ((DEBUG_ERROR
, "NvVarStore header signature/size/format/state were invalid.\n"));
725 // Verify the header startId, state
726 // Verify data to the end
728 VariableBase
= (UINTN
)NvVarStoreBase
+ NvVarStoreFvHeader
->HeaderLength
+ sizeof (VARIABLE_STORE_HEADER
);
729 while (VariableOffset
< (NvVarStoreHeader
->Size
- sizeof (VARIABLE_STORE_HEADER
))) {
730 VariableHeader
= (AUTHENTICATED_VARIABLE_HEADER
*)(VariableBase
+ VariableOffset
);
731 if (VariableHeader
->StartId
!= VARIABLE_DATA
) {
732 if (!CheckPaddingData ((UINT8
*)VariableHeader
, NvVarStoreHeader
->Size
- sizeof (VARIABLE_STORE_HEADER
) - VariableOffset
)) {
733 DEBUG ((DEBUG_ERROR
, "NvVarStore variable header StartId was invalid.\n"));
737 VariableOffset
= NvVarStoreHeader
->Size
- sizeof (VARIABLE_STORE_HEADER
);
739 if (!((VariableHeader
->State
== VAR_HEADER_VALID_ONLY
) ||
740 (VariableHeader
->State
== VAR_ADDED
) ||
741 (VariableHeader
->State
== (VAR_ADDED
& VAR_DELETED
)) ||
742 (VariableHeader
->State
== (VAR_ADDED
& VAR_IN_DELETED_TRANSITION
)) ||
743 (VariableHeader
->State
== (VAR_ADDED
& VAR_IN_DELETED_TRANSITION
& VAR_DELETED
))))
745 DEBUG ((DEBUG_ERROR
, "NvVarStore Variable header State was invalid.\n"));
749 VariableOffset
+= sizeof (AUTHENTICATED_VARIABLE_HEADER
) + VariableHeader
->NameSize
+ VariableHeader
->DataSize
;
750 // Verify VariableOffset should be less than or equal NvVarStoreHeader->Size - sizeof(VARIABLE_STORE_HEADER)
751 if (VariableOffset
> (NvVarStoreHeader
->Size
- sizeof (VARIABLE_STORE_HEADER
))) {
752 DEBUG ((DEBUG_ERROR
, "NvVarStore Variable header VariableOffset was invalid.\n"));
756 VariableOffsetBeforeAlign
= VariableOffset
;
758 VariableOffset
= (VariableOffset
+ 3) & (UINTN
)(~3);
760 if (!CheckPaddingData ((UINT8
*)(VariableBase
+ VariableOffsetBeforeAlign
), VariableOffset
- VariableOffsetBeforeAlign
)) {
761 DEBUG ((DEBUG_ERROR
, "NvVarStore Variable header PaddingData was invalid.\n"));
771 Allocate storage for NV variables early on so it will be
772 at a consistent address. Since VM memory is preserved
773 across reboots, this allows the NV variable storage to survive
777 * @retval VOID* The pointer to the storage for NV Variables
781 PlatformReserveEmuVariableNvStore (
788 VarStoreSize
= 2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
);
790 // Allocate storage for NV variables early on so it will be
791 // at a consistent address. Since VM memory is preserved
792 // across reboots, this allows the NV variable storage to survive
796 AllocateRuntimePages (
797 EFI_SIZE_TO_PAGES (VarStoreSize
)
801 "Reserved variable store memory: 0x%p; size: %dkb\n",
806 return VariableStore
;
810 When OVMF is lauched with -bios parameter, UEFI variables will be
811 partially emulated, and non-volatile variables may lose their contents
812 after a reboot. This makes the secure boot feature not working.
814 This function is used to initialize the EmuVariableNvStore
815 with the conent in PcdOvmfFlashNvStorageVariableBase.
817 @param[in] EmuVariableNvStore - A pointer to EmuVariableNvStore
819 @retval EFI_SUCCESS - Successfully init the EmuVariableNvStore
820 @retval Others - As the error code indicates
824 PlatformInitEmuVariableNvStore (
825 IN VOID
*EmuVariableNvStore
830 UINT32 EmuVariableNvStoreSize
;
832 EmuVariableNvStoreSize
= 2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
);
833 if ((EmuVariableNvStore
== NULL
) || (EmuVariableNvStoreSize
== 0)) {
834 DEBUG ((DEBUG_ERROR
, "Invalid EmuVariableNvStore parameter.\n"));
835 return EFI_INVALID_PARAMETER
;
838 Base
= (UINT8
*)(UINTN
)PcdGet32 (PcdOvmfFlashNvStorageVariableBase
);
839 Size
= (UINT32
)PcdGet32 (PcdFlashNvStorageVariableSize
);
840 ASSERT (Size
< EmuVariableNvStoreSize
);
842 if (!PlatformValidateNvVarStore (Base
, PcdGet32 (PcdCfvRawDataSize
))) {
844 return EFI_INVALID_PARAMETER
;
847 DEBUG ((DEBUG_INFO
, "Init EmuVariableNvStore with the content in FlashNvStorage\n"));
849 CopyMem (EmuVariableNvStore
, Base
, Size
);