2 The CPU specific programming for PiSmmCpuDxeSmm module.
4 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials are licensed and made available
7 under the terms and conditions of the BSD License which accompanies this
8 distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
12 WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <Library/BaseLib.h>
16 #include <Library/BaseMemoryLib.h>
17 #include <Library/DebugLib.h>
18 #include <Library/SmmCpuFeaturesLib.h>
19 #include <Library/SmmServicesTableLib.h>
21 #include <Register/QemuSmramSaveStateMap.h>
24 // EFER register LMA bit
29 The constructor function
31 @param[in] ImageHandle The firmware allocated handle for the EFI image.
32 @param[in] SystemTable A pointer to the EFI System Table.
34 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
39 SmmCpuFeaturesLibConstructor (
40 IN EFI_HANDLE ImageHandle
,
41 IN EFI_SYSTEM_TABLE
*SystemTable
45 // No need to program SMRRs on our virtual platform.
51 Called during the very first SMI into System Management Mode to initialize
52 CPU features, including SMBASE, for the currently executing CPU. Since this
53 is the first SMI, the SMRAM Save State Map is at the default address of
54 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
55 CPU is specified by CpuIndex and CpuIndex can be used to access information
56 about the currently executing CPU in the ProcessorInfo array and the
57 HotPlugCpuData data structure.
59 @param[in] CpuIndex The index of the CPU to initialize. The value
60 must be between 0 and the NumberOfCpus field in
61 the System Management System Table (SMST).
62 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
63 was elected as monarch during System Management
65 FALSE if the CpuIndex is not the index of the CPU
66 that was elected as monarch during System
67 Management Mode initialization.
68 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
69 structures. ProcessorInfo[CpuIndex] contains the
70 information for the currently executing CPU.
71 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
72 contains the ApidId and SmBase arrays.
76 SmmCpuFeaturesInitializeProcessor (
79 IN EFI_PROCESSOR_INFORMATION
*ProcessorInfo
,
80 IN CPU_HOT_PLUG_DATA
*CpuHotPlugData
83 QEMU_SMRAM_SAVE_STATE_MAP
*CpuState
;
88 CpuState
= (QEMU_SMRAM_SAVE_STATE_MAP
*)(UINTN
)(
90 SMRAM_SAVE_STATE_MAP_OFFSET
92 if ((CpuState
->x86
.SMMRevId
& 0xFFFF) == 0) {
93 CpuState
->x86
.SMBASE
= (UINT32
)CpuHotPlugData
->SmBase
[CpuIndex
];
95 CpuState
->x64
.SMBASE
= (UINT32
)CpuHotPlugData
->SmBase
[CpuIndex
];
99 // No need to program SMRRs on our virtual platform.
104 This function updates the SMRAM save state on the currently executing CPU
105 to resume execution at a specific address after an RSM instruction. This
106 function must evaluate the SMRAM save state to determine the execution mode
107 the RSM instruction resumes and update the resume execution address with
108 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart
109 flag in the SMRAM save state must always be cleared. This function returns
110 the value of the instruction pointer from the SMRAM save state that was
111 replaced. If this function returns 0, then the SMRAM save state was not
114 This function is called during the very first SMI on each CPU after
115 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
116 to signal that the SMBASE of each CPU has been updated before the default
117 SMBASE address is used for the first SMI to the next CPU.
119 @param[in] CpuIndex The index of the CPU to hook. The value
120 must be between 0 and the NumberOfCpus
121 field in the System Management System
123 @param[in] CpuState Pointer to SMRAM Save State Map for the
124 currently executing CPU.
125 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
126 32-bit execution mode from 64-bit SMM.
127 @param[in] NewInstructionPointer Instruction pointer to use if resuming to
128 same execution mode as SMM.
130 @retval 0 This function did modify the SMRAM save state.
131 @retval > 0 The original instruction pointer value from the SMRAM save state
132 before it was replaced.
136 SmmCpuFeaturesHookReturnFromSmm (
138 IN SMRAM_SAVE_STATE_MAP
*CpuState
,
139 IN UINT64 NewInstructionPointer32
,
140 IN UINT64 NewInstructionPointer
143 UINT64 OriginalInstructionPointer
;
144 QEMU_SMRAM_SAVE_STATE_MAP
*CpuSaveState
;
146 CpuSaveState
= (QEMU_SMRAM_SAVE_STATE_MAP
*)CpuState
;
147 if ((CpuSaveState
->x86
.SMMRevId
& 0xFFFF) == 0) {
148 OriginalInstructionPointer
= (UINT64
)CpuSaveState
->x86
._EIP
;
149 CpuSaveState
->x86
._EIP
= (UINT32
)NewInstructionPointer
;
151 // Clear the auto HALT restart flag so the RSM instruction returns
152 // program control to the instruction following the HLT instruction.
154 if ((CpuSaveState
->x86
.AutoHALTRestart
& BIT0
) != 0) {
155 CpuSaveState
->x86
.AutoHALTRestart
&= ~BIT0
;
158 OriginalInstructionPointer
= CpuSaveState
->x64
._RIP
;
159 if ((CpuSaveState
->x64
.IA32_EFER
& LMA
) == 0) {
160 CpuSaveState
->x64
._RIP
= (UINT32
)NewInstructionPointer32
;
162 CpuSaveState
->x64
._RIP
= (UINT32
)NewInstructionPointer
;
165 // Clear the auto HALT restart flag so the RSM instruction returns
166 // program control to the instruction following the HLT instruction.
168 if ((CpuSaveState
->x64
.AutoHALTRestart
& BIT0
) != 0) {
169 CpuSaveState
->x64
.AutoHALTRestart
&= ~BIT0
;
172 return OriginalInstructionPointer
;
176 Hook point in normal execution mode that allows the one CPU that was elected
177 as monarch during System Management Mode initialization to perform additional
178 initialization actions immediately after all of the CPUs have processed their
179 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE
180 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().
184 SmmCpuFeaturesSmmRelocationComplete (
191 Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
192 returned, then a custom SMI handler is not provided by this library,
193 and the default SMI handler must be used.
195 @retval 0 Use the default SMI handler.
196 @retval > 0 Use the SMI handler installed by
197 SmmCpuFeaturesInstallSmiHandler(). The caller is required to
198 allocate enough SMRAM for each CPU to support the size of the
203 SmmCpuFeaturesGetSmiHandlerSize (
211 Install a custom SMI handler for the CPU specified by CpuIndex. This
212 function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size
213 is greater than zero and is called by the CPU that was elected as monarch
214 during System Management Mode initialization.
216 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
217 The value must be between 0 and the NumberOfCpus field
218 in the System Management System Table (SMST).
219 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
220 @param[in] SmiStack The stack to use when an SMI is processed by the
221 the CPU specified by CpuIndex.
222 @param[in] StackSize The size, in bytes, if the stack used when an SMI is
223 processed by the CPU specified by CpuIndex.
224 @param[in] GdtBase The base address of the GDT to use when an SMI is
225 processed by the CPU specified by CpuIndex.
226 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
227 processed by the CPU specified by CpuIndex.
228 @param[in] IdtBase The base address of the IDT to use when an SMI is
229 processed by the CPU specified by CpuIndex.
230 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
231 processed by the CPU specified by CpuIndex.
232 @param[in] Cr3 The base address of the page tables to use when an SMI
233 is processed by the CPU specified by CpuIndex.
237 SmmCpuFeaturesInstallSmiHandler (
252 Determines if MTRR registers must be configured to set SMRAM cache-ability
253 when executing in System Management Mode.
255 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
256 @retval FALSE MTRR registers do not need to be configured to set SMRAM
261 SmmCpuFeaturesNeedConfigureMtrrs (
269 Disable SMRR register if SMRR is supported and
270 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.
274 SmmCpuFeaturesDisableSmrr (
279 // No SMRR support, nothing to do
284 Enable SMRR register if SMRR is supported and
285 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.
289 SmmCpuFeaturesReenableSmrr (
294 // No SMRR support, nothing to do
299 Processor specific hook point each time a CPU enters System Management Mode.
301 @param[in] CpuIndex The index of the CPU that has entered SMM. The value
302 must be between 0 and the NumberOfCpus field in the
303 System Management System Table (SMST).
307 SmmCpuFeaturesRendezvousEntry (
312 // No SMRR support, nothing to do
317 Processor specific hook point each time a CPU exits System Management Mode.
319 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value
320 must be between 0 and the NumberOfCpus field in the
321 System Management System Table (SMST).
325 SmmCpuFeaturesRendezvousExit (
332 Check to see if an SMM register is supported by a specified CPU.
334 @param[in] CpuIndex The index of the CPU to check for SMM register support.
335 The value must be between 0 and the NumberOfCpus field
336 in the System Management System Table (SMST).
337 @param[in] RegName Identifies the SMM register to check for support.
339 @retval TRUE The SMM register specified by RegName is supported by the CPU
340 specified by CpuIndex.
341 @retval FALSE The SMM register specified by RegName is not supported by the
342 CPU specified by CpuIndex.
346 SmmCpuFeaturesIsSmmRegisterSupported (
348 IN SMM_REG_NAME RegName
351 ASSERT (RegName
== SmmRegFeatureControl
);
356 Returns the current value of the SMM register for the specified CPU.
357 If the SMM register is not supported, then 0 is returned.
359 @param[in] CpuIndex The index of the CPU to read the SMM register. The
360 value must be between 0 and the NumberOfCpus field in
361 the System Management System Table (SMST).
362 @param[in] RegName Identifies the SMM register to read.
364 @return The value of the SMM register specified by RegName from the CPU
365 specified by CpuIndex.
369 SmmCpuFeaturesGetSmmRegister (
371 IN SMM_REG_NAME RegName
375 // This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable.
376 // The last of these should actually be SmmRegSmmDisable, so we can just
383 Sets the value of an SMM register on a specified CPU.
384 If the SMM register is not supported, then no action is performed.
386 @param[in] CpuIndex The index of the CPU to write the SMM register. The
387 value must be between 0 and the NumberOfCpus field in
388 the System Management System Table (SMST).
389 @param[in] RegName Identifies the SMM register to write.
390 registers are read-only.
391 @param[in] Value The value to write to the SMM register.
395 SmmCpuFeaturesSetSmmRegister (
397 IN SMM_REG_NAME RegName
,
405 /// Macro used to simplify the lookup table entries of type
406 /// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
408 #define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)
411 /// Macro used to simplify the lookup table entries of type
412 /// CPU_SMM_SAVE_STATE_REGISTER_RANGE
414 #define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
417 /// Structure used to describe a range of registers
420 EFI_SMM_SAVE_STATE_REGISTER Start
;
421 EFI_SMM_SAVE_STATE_REGISTER End
;
423 } CPU_SMM_SAVE_STATE_REGISTER_RANGE
;
426 /// Structure used to build a lookup table to retrieve the widths and offsets
427 /// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
430 #define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1
439 } CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
;
442 /// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
443 /// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
445 STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges
[] = {
447 EFI_SMM_SAVE_STATE_REGISTER_GDTBASE
,
448 EFI_SMM_SAVE_STATE_REGISTER_LDTINFO
451 EFI_SMM_SAVE_STATE_REGISTER_ES
,
452 EFI_SMM_SAVE_STATE_REGISTER_RIP
455 EFI_SMM_SAVE_STATE_REGISTER_RFLAGS
,
456 EFI_SMM_SAVE_STATE_REGISTER_CR4
458 { (EFI_SMM_SAVE_STATE_REGISTER
)0, (EFI_SMM_SAVE_STATE_REGISTER
)0, 0 }
462 /// Lookup table used to retrieve the widths and offsets associated with each
463 /// supported EFI_SMM_SAVE_STATE_REGISTER value
465 STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset
[] = {
476 // CPU Save State registers defined in PI SMM CPU Protocol.
482 SMM_CPU_OFFSET (x64
._GDTRBase
), // Offset64Lo
483 SMM_CPU_OFFSET (x64
._GDTRBase
) + 4, // Offset64Hi
485 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
491 SMM_CPU_OFFSET (x64
._IDTRBase
), // Offset64Lo
492 SMM_CPU_OFFSET (x64
._IDTRBase
) + 4, // Offset64Hi
494 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
500 SMM_CPU_OFFSET (x64
._LDTRBase
), // Offset64Lo
501 SMM_CPU_OFFSET (x64
._LDTRBase
) + 4, // Offset64Hi
503 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
509 SMM_CPU_OFFSET (x64
._GDTRLimit
), // Offset64Lo
510 SMM_CPU_OFFSET (x64
._GDTRLimit
) + 4, // Offset64Hi
512 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
518 SMM_CPU_OFFSET (x64
._IDTRLimit
), // Offset64Lo
519 SMM_CPU_OFFSET (x64
._IDTRLimit
) + 4, // Offset64Hi
521 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
527 SMM_CPU_OFFSET (x64
._LDTRLimit
), // Offset64Lo
528 SMM_CPU_OFFSET (x64
._LDTRLimit
) + 4, // Offset64Hi
530 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
539 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
544 SMM_CPU_OFFSET (x86
._ES
), // Offset32
545 SMM_CPU_OFFSET (x64
._ES
), // Offset64Lo
548 }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
553 SMM_CPU_OFFSET (x86
._CS
), // Offset32
554 SMM_CPU_OFFSET (x64
._CS
), // Offset64Lo
557 }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
562 SMM_CPU_OFFSET (x86
._SS
), // Offset32
563 SMM_CPU_OFFSET (x64
._SS
), // Offset64Lo
566 }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
571 SMM_CPU_OFFSET (x86
._DS
), // Offset32
572 SMM_CPU_OFFSET (x64
._DS
), // Offset64Lo
575 }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
580 SMM_CPU_OFFSET (x86
._FS
), // Offset32
581 SMM_CPU_OFFSET (x64
._FS
), // Offset64Lo
584 }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
589 SMM_CPU_OFFSET (x86
._GS
), // Offset32
590 SMM_CPU_OFFSET (x64
._GS
), // Offset64Lo
593 }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
599 SMM_CPU_OFFSET (x64
._LDTR
), // Offset64Lo
602 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
607 SMM_CPU_OFFSET (x86
._TR
), // Offset32
608 SMM_CPU_OFFSET (x64
._TR
), // Offset64Lo
611 }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
616 SMM_CPU_OFFSET (x86
._DR7
), // Offset32
617 SMM_CPU_OFFSET (x64
._DR7
), // Offset64Lo
618 SMM_CPU_OFFSET (x64
._DR7
) + 4, // Offset64Hi
620 }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
625 SMM_CPU_OFFSET (x86
._DR6
), // Offset32
626 SMM_CPU_OFFSET (x64
._DR6
), // Offset64Lo
627 SMM_CPU_OFFSET (x64
._DR6
) + 4, // Offset64Hi
629 }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
635 SMM_CPU_OFFSET (x64
._R8
), // Offset64Lo
636 SMM_CPU_OFFSET (x64
._R8
) + 4, // Offset64Hi
638 }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
644 SMM_CPU_OFFSET (x64
._R9
), // Offset64Lo
645 SMM_CPU_OFFSET (x64
._R9
) + 4, // Offset64Hi
647 }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
653 SMM_CPU_OFFSET (x64
._R10
), // Offset64Lo
654 SMM_CPU_OFFSET (x64
._R10
) + 4, // Offset64Hi
656 }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
662 SMM_CPU_OFFSET (x64
._R11
), // Offset64Lo
663 SMM_CPU_OFFSET (x64
._R11
) + 4, // Offset64Hi
665 }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
671 SMM_CPU_OFFSET (x64
._R12
), // Offset64Lo
672 SMM_CPU_OFFSET (x64
._R12
) + 4, // Offset64Hi
674 }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
680 SMM_CPU_OFFSET (x64
._R13
), // Offset64Lo
681 SMM_CPU_OFFSET (x64
._R13
) + 4, // Offset64Hi
683 }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
689 SMM_CPU_OFFSET (x64
._R14
), // Offset64Lo
690 SMM_CPU_OFFSET (x64
._R14
) + 4, // Offset64Hi
692 }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
698 SMM_CPU_OFFSET (x64
._R15
), // Offset64Lo
699 SMM_CPU_OFFSET (x64
._R15
) + 4, // Offset64Hi
701 }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
706 SMM_CPU_OFFSET (x86
._EAX
), // Offset32
707 SMM_CPU_OFFSET (x64
._RAX
), // Offset64Lo
708 SMM_CPU_OFFSET (x64
._RAX
) + 4, // Offset64Hi
710 }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
715 SMM_CPU_OFFSET (x86
._EBX
), // Offset32
716 SMM_CPU_OFFSET (x64
._RBX
), // Offset64Lo
717 SMM_CPU_OFFSET (x64
._RBX
) + 4, // Offset64Hi
719 }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
724 SMM_CPU_OFFSET (x86
._ECX
), // Offset32
725 SMM_CPU_OFFSET (x64
._RCX
), // Offset64Lo
726 SMM_CPU_OFFSET (x64
._RCX
) + 4, // Offset64Hi
728 }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
733 SMM_CPU_OFFSET (x86
._EDX
), // Offset32
734 SMM_CPU_OFFSET (x64
._RDX
), // Offset64Lo
735 SMM_CPU_OFFSET (x64
._RDX
) + 4, // Offset64Hi
737 }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
742 SMM_CPU_OFFSET (x86
._ESP
), // Offset32
743 SMM_CPU_OFFSET (x64
._RSP
), // Offset64Lo
744 SMM_CPU_OFFSET (x64
._RSP
) + 4, // Offset64Hi
746 }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
751 SMM_CPU_OFFSET (x86
._EBP
), // Offset32
752 SMM_CPU_OFFSET (x64
._RBP
), // Offset64Lo
753 SMM_CPU_OFFSET (x64
._RBP
) + 4, // Offset64Hi
755 }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
760 SMM_CPU_OFFSET (x86
._ESI
), // Offset32
761 SMM_CPU_OFFSET (x64
._RSI
), // Offset64Lo
762 SMM_CPU_OFFSET (x64
._RSI
) + 4, // Offset64Hi
764 }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
769 SMM_CPU_OFFSET (x86
._EDI
), // Offset32
770 SMM_CPU_OFFSET (x64
._RDI
), // Offset64Lo
771 SMM_CPU_OFFSET (x64
._RDI
) + 4, // Offset64Hi
773 }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
778 SMM_CPU_OFFSET (x86
._EIP
), // Offset32
779 SMM_CPU_OFFSET (x64
._RIP
), // Offset64Lo
780 SMM_CPU_OFFSET (x64
._RIP
) + 4, // Offset64Hi
782 }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
787 SMM_CPU_OFFSET (x86
._EFLAGS
), // Offset32
788 SMM_CPU_OFFSET (x64
._RFLAGS
), // Offset64Lo
789 SMM_CPU_OFFSET (x64
._RFLAGS
) + 4, // Offset64Hi
791 }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
796 SMM_CPU_OFFSET (x86
._CR0
), // Offset32
797 SMM_CPU_OFFSET (x64
._CR0
), // Offset64Lo
798 SMM_CPU_OFFSET (x64
._CR0
) + 4, // Offset64Hi
800 }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
805 SMM_CPU_OFFSET (x86
._CR3
), // Offset32
806 SMM_CPU_OFFSET (x64
._CR3
), // Offset64Lo
807 SMM_CPU_OFFSET (x64
._CR3
) + 4, // Offset64Hi
809 }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
815 SMM_CPU_OFFSET (x64
._CR4
), // Offset64Lo
816 SMM_CPU_OFFSET (x64
._CR4
) + 4, // Offset64Hi
818 }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
822 // No support for I/O restart
826 Read information from the CPU save state.
828 @param Register Specifies the CPU register to read form the save state.
830 @retval 0 Register is not valid
831 @retval >0 Index into mSmmCpuWidthOffset[] associated with Register
837 IN EFI_SMM_SAVE_STATE_REGISTER Register
843 for (Index
= 0, Offset
= SMM_SAVE_STATE_REGISTER_FIRST_INDEX
;
844 mSmmCpuRegisterRanges
[Index
].Length
!= 0;
846 if (Register
>= mSmmCpuRegisterRanges
[Index
].Start
&&
847 Register
<= mSmmCpuRegisterRanges
[Index
].End
) {
848 return Register
- mSmmCpuRegisterRanges
[Index
].Start
+ Offset
;
850 Offset
+= mSmmCpuRegisterRanges
[Index
].Length
;
856 Read a CPU Save State register on the target processor.
858 This function abstracts the differences that whether the CPU Save State
859 register is in the IA32 CPU Save State Map or X64 CPU Save State Map.
861 This function supports reading a CPU Save State register in SMBase relocation
864 @param[in] CpuIndex Specifies the zero-based index of the CPU save
866 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
867 @param[in] Width The number of bytes to read from the CPU save
869 @param[out] Buffer Upon return, this holds the CPU register value
870 read from the save state.
872 @retval EFI_SUCCESS The register was read from Save State.
873 @retval EFI_NOT_FOUND The register is not defined for the Save State
875 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
880 ReadSaveStateRegisterByIndex (
882 IN UINTN RegisterIndex
,
887 QEMU_SMRAM_SAVE_STATE_MAP
*CpuSaveState
;
889 CpuSaveState
= (QEMU_SMRAM_SAVE_STATE_MAP
*)gSmst
->CpuSaveState
[CpuIndex
];
891 if ((CpuSaveState
->x86
.SMMRevId
& 0xFFFF) == 0) {
893 // If 32-bit mode width is zero, then the specified register can not be
896 if (mSmmCpuWidthOffset
[RegisterIndex
].Width32
== 0) {
897 return EFI_NOT_FOUND
;
901 // If Width is bigger than the 32-bit mode width, then the specified
902 // register can not be accessed
904 if (Width
> mSmmCpuWidthOffset
[RegisterIndex
].Width32
) {
905 return EFI_INVALID_PARAMETER
;
909 // Write return buffer
911 ASSERT(CpuSaveState
!= NULL
);
914 (UINT8
*)CpuSaveState
+ mSmmCpuWidthOffset
[RegisterIndex
].Offset32
,
919 // If 64-bit mode width is zero, then the specified register can not be
922 if (mSmmCpuWidthOffset
[RegisterIndex
].Width64
== 0) {
923 return EFI_NOT_FOUND
;
927 // If Width is bigger than the 64-bit mode width, then the specified
928 // register can not be accessed
930 if (Width
> mSmmCpuWidthOffset
[RegisterIndex
].Width64
) {
931 return EFI_INVALID_PARAMETER
;
935 // Write lower 32-bits of return buffer
939 (UINT8
*)CpuSaveState
+ mSmmCpuWidthOffset
[RegisterIndex
].Offset64Lo
,
944 // Write upper 32-bits of return buffer
948 (UINT8
*)CpuSaveState
+ mSmmCpuWidthOffset
[RegisterIndex
].Offset64Hi
,
957 Read an SMM Save State register on the target processor. If this function
958 returns EFI_UNSUPPORTED, then the caller is responsible for reading the
959 SMM Save Sate register.
961 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
962 value must be between 0 and the NumberOfCpus field in
963 the System Management System Table (SMST).
964 @param[in] Register The SMM Save State register to read.
965 @param[in] Width The number of bytes to read from the CPU save state.
966 @param[out] Buffer Upon return, this holds the CPU register value read
969 @retval EFI_SUCCESS The register was read from Save State.
970 @retval EFI_INVALID_PARAMTER Buffer is NULL.
971 @retval EFI_UNSUPPORTED This function does not support reading
976 SmmCpuFeaturesReadSaveStateRegister (
978 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
984 QEMU_SMRAM_SAVE_STATE_MAP
*CpuSaveState
;
987 // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
989 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_LMA
) {
991 // Only byte access is supported for this register
994 return EFI_INVALID_PARAMETER
;
997 CpuSaveState
= (QEMU_SMRAM_SAVE_STATE_MAP
*)gSmst
->CpuSaveState
[CpuIndex
];
1002 if ((CpuSaveState
->x86
.SMMRevId
& 0xFFFF) == 0) {
1003 *(UINT8
*)Buffer
= 32;
1005 *(UINT8
*)Buffer
= 64;
1012 // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO
1014 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_IO
) {
1015 return EFI_NOT_FOUND
;
1019 // Convert Register to a register lookup table index. Let
1020 // PiSmmCpuDxeSmm implement other special registers (currently
1021 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
1023 RegisterIndex
= GetRegisterIndex (Register
);
1024 if (RegisterIndex
== 0) {
1025 return (Register
< EFI_SMM_SAVE_STATE_REGISTER_IO
?
1030 return ReadSaveStateRegisterByIndex (CpuIndex
, RegisterIndex
, Width
, Buffer
);
1034 Writes an SMM Save State register on the target processor. If this function
1035 returns EFI_UNSUPPORTED, then the caller is responsible for writing the
1036 SMM Save Sate register.
1038 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The
1039 value must be between 0 and the NumberOfCpus field in
1040 the System Management System Table (SMST).
1041 @param[in] Register The SMM Save State register to write.
1042 @param[in] Width The number of bytes to write to the CPU save state.
1043 @param[in] Buffer Upon entry, this holds the new CPU register value.
1045 @retval EFI_SUCCESS The register was written to Save State.
1046 @retval EFI_INVALID_PARAMTER Buffer is NULL.
1047 @retval EFI_UNSUPPORTED This function does not support writing
1052 SmmCpuFeaturesWriteSaveStateRegister (
1054 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
1056 IN CONST VOID
*Buffer
1059 UINTN RegisterIndex
;
1060 QEMU_SMRAM_SAVE_STATE_MAP
*CpuSaveState
;
1063 // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
1065 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_LMA
) {
1070 // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported
1072 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_IO
) {
1073 return EFI_NOT_FOUND
;
1077 // Convert Register to a register lookup table index. Let
1078 // PiSmmCpuDxeSmm implement other special registers (currently
1079 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
1081 RegisterIndex
= GetRegisterIndex (Register
);
1082 if (RegisterIndex
== 0) {
1083 return (Register
< EFI_SMM_SAVE_STATE_REGISTER_IO
?
1088 CpuSaveState
= (QEMU_SMRAM_SAVE_STATE_MAP
*)gSmst
->CpuSaveState
[CpuIndex
];
1091 // Do not write non-writable SaveState, because it will cause exception.
1093 if (!mSmmCpuWidthOffset
[RegisterIndex
].Writeable
) {
1094 return EFI_UNSUPPORTED
;
1100 if ((CpuSaveState
->x86
.SMMRevId
& 0xFFFF) == 0) {
1102 // If 32-bit mode width is zero, then the specified register can not be
1105 if (mSmmCpuWidthOffset
[RegisterIndex
].Width32
== 0) {
1106 return EFI_NOT_FOUND
;
1110 // If Width is bigger than the 32-bit mode width, then the specified
1111 // register can not be accessed
1113 if (Width
> mSmmCpuWidthOffset
[RegisterIndex
].Width32
) {
1114 return EFI_INVALID_PARAMETER
;
1117 // Write SMM State register
1119 ASSERT (CpuSaveState
!= NULL
);
1121 (UINT8
*)CpuSaveState
+ mSmmCpuWidthOffset
[RegisterIndex
].Offset32
,
1127 // If 64-bit mode width is zero, then the specified register can not be
1130 if (mSmmCpuWidthOffset
[RegisterIndex
].Width64
== 0) {
1131 return EFI_NOT_FOUND
;
1135 // If Width is bigger than the 64-bit mode width, then the specified
1136 // register can not be accessed
1138 if (Width
> mSmmCpuWidthOffset
[RegisterIndex
].Width64
) {
1139 return EFI_INVALID_PARAMETER
;
1143 // Write lower 32-bits of SMM State register
1146 (UINT8
*)CpuSaveState
+ mSmmCpuWidthOffset
[RegisterIndex
].Offset64Lo
,
1152 // Write upper 32-bits of SMM State register
1155 (UINT8
*)CpuSaveState
+ mSmmCpuWidthOffset
[RegisterIndex
].Offset64Hi
,
1156 (UINT8
*)Buffer
+ 4,
1165 This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
1166 notification is completely processed.
1170 SmmCpuFeaturesCompleteSmmReadyToLock (
1177 This API provides a method for a CPU to allocate a specific region for
1178 storing page tables.
1180 This API can be called more once to allocate memory for page tables.
1182 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns
1183 a pointer to the allocated buffer. The buffer returned is aligned on a 4KB
1184 boundary. If Pages is 0, then NULL is returned. If there is not enough
1185 memory remaining to satisfy the request, then NULL is returned.
1187 This function can also return NULL if there is no preference on where the
1188 page tables are allocated in SMRAM.
1190 @param Pages The number of 4 KB pages to allocate.
1192 @return A pointer to the allocated buffer for page tables.
1193 @retval NULL Fail to allocate a specific region for storing page tables,
1194 Or there is no preference on where the page tables are
1200 SmmCpuFeaturesAllocatePageTableMemory (