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1 /** @file
2 The CPU specific programming for PiSmmCpuDxeSmm module.
3
4 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
5
6 This program and the accompanying materials are licensed and made available
7 under the terms and conditions of the BSD License which accompanies this
8 distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
12 WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 **/
14
15 #include <PiSmm.h>
16 #include <Library/SmmCpuFeaturesLib.h>
17 #include <Library/BaseLib.h>
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/PcdLib.h>
20 #include <Library/MemoryAllocationLib.h>
21 #include <Library/SmmServicesTableLib.h>
22 #include <Library/DebugLib.h>
23 #include <Register/QemuSmramSaveStateMap.h>
24
25 //
26 // EFER register LMA bit
27 //
28 #define LMA BIT10
29
30 /**
31 The constructor function
32
33 @param[in] ImageHandle The firmware allocated handle for the EFI image.
34 @param[in] SystemTable A pointer to the EFI System Table.
35
36 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
37
38 **/
39 EFI_STATUS
40 EFIAPI
41 SmmCpuFeaturesLibConstructor (
42 IN EFI_HANDLE ImageHandle,
43 IN EFI_SYSTEM_TABLE *SystemTable
44 )
45 {
46 //
47 // No need to program SMRRs on our virtual platform.
48 //
49 return EFI_SUCCESS;
50 }
51
52 /**
53 Called during the very first SMI into System Management Mode to initialize
54 CPU features, including SMBASE, for the currently executing CPU. Since this
55 is the first SMI, the SMRAM Save State Map is at the default address of
56 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
57 CPU is specified by CpuIndex and CpuIndex can be used to access information
58 about the currently executing CPU in the ProcessorInfo array and the
59 HotPlugCpuData data structure.
60
61 @param[in] CpuIndex The index of the CPU to initialize. The value
62 must be between 0 and the NumberOfCpus field in
63 the System Management System Table (SMST).
64 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
65 was elected as monarch during System Management
66 Mode initialization.
67 FALSE if the CpuIndex is not the index of the CPU
68 that was elected as monarch during System
69 Management Mode initialization.
70 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
71 structures. ProcessorInfo[CpuIndex] contains the
72 information for the currently executing CPU.
73 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
74 contains the ApidId and SmBase arrays.
75 **/
76 VOID
77 EFIAPI
78 SmmCpuFeaturesInitializeProcessor (
79 IN UINTN CpuIndex,
80 IN BOOLEAN IsMonarch,
81 IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,
82 IN CPU_HOT_PLUG_DATA *CpuHotPlugData
83 )
84 {
85 QEMU_SMRAM_SAVE_STATE_MAP *CpuState;
86
87 //
88 // Configure SMBASE.
89 //
90 CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(
91 SMM_DEFAULT_SMBASE +
92 SMRAM_SAVE_STATE_MAP_OFFSET
93 );
94 if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) {
95 CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
96 } else {
97 CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
98 }
99
100 //
101 // No need to program SMRRs on our virtual platform.
102 //
103 }
104
105 /**
106 This function updates the SMRAM save state on the currently executing CPU
107 to resume execution at a specific address after an RSM instruction. This
108 function must evaluate the SMRAM save state to determine the execution mode
109 the RSM instruction resumes and update the resume execution address with
110 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart
111 flag in the SMRAM save state must always be cleared. This function returns
112 the value of the instruction pointer from the SMRAM save state that was
113 replaced. If this function returns 0, then the SMRAM save state was not
114 modified.
115
116 This function is called during the very first SMI on each CPU after
117 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
118 to signal that the SMBASE of each CPU has been updated before the default
119 SMBASE address is used for the first SMI to the next CPU.
120
121 @param[in] CpuIndex The index of the CPU to hook. The value
122 must be between 0 and the NumberOfCpus
123 field in the System Management System
124 Table (SMST).
125 @param[in] CpuState Pointer to SMRAM Save State Map for the
126 currently executing CPU.
127 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
128 32-bit execution mode from 64-bit SMM.
129 @param[in] NewInstructionPointer Instruction pointer to use if resuming to
130 same execution mode as SMM.
131
132 @retval 0 This function did modify the SMRAM save state.
133 @retval > 0 The original instruction pointer value from the SMRAM save state
134 before it was replaced.
135 **/
136 UINT64
137 EFIAPI
138 SmmCpuFeaturesHookReturnFromSmm (
139 IN UINTN CpuIndex,
140 IN SMRAM_SAVE_STATE_MAP *CpuState,
141 IN UINT64 NewInstructionPointer32,
142 IN UINT64 NewInstructionPointer
143 )
144 {
145 UINT64 OriginalInstructionPointer;
146 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
147
148 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;
149 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
150 OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;
151 CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;
152 //
153 // Clear the auto HALT restart flag so the RSM instruction returns
154 // program control to the instruction following the HLT instruction.
155 //
156 if ((CpuSaveState->x86.AutoHALTRestart & BIT0) != 0) {
157 CpuSaveState->x86.AutoHALTRestart &= ~BIT0;
158 }
159 } else {
160 OriginalInstructionPointer = CpuSaveState->x64._RIP;
161 if ((CpuSaveState->x64.IA32_EFER & LMA) == 0) {
162 CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer32;
163 } else {
164 CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer;
165 }
166 //
167 // Clear the auto HALT restart flag so the RSM instruction returns
168 // program control to the instruction following the HLT instruction.
169 //
170 if ((CpuSaveState->x64.AutoHALTRestart & BIT0) != 0) {
171 CpuSaveState->x64.AutoHALTRestart &= ~BIT0;
172 }
173 }
174 return OriginalInstructionPointer;
175 }
176
177 /**
178 Hook point in normal execution mode that allows the one CPU that was elected
179 as monarch during System Management Mode initialization to perform additional
180 initialization actions immediately after all of the CPUs have processed their
181 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE
182 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().
183 **/
184 VOID
185 EFIAPI
186 SmmCpuFeaturesSmmRelocationComplete (
187 VOID
188 )
189 {
190 }
191
192 /**
193 Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
194 returned, then a custom SMI handler is not provided by this library,
195 and the default SMI handler must be used.
196
197 @retval 0 Use the default SMI handler.
198 @retval > 0 Use the SMI handler installed by
199 SmmCpuFeaturesInstallSmiHandler(). The caller is required to
200 allocate enough SMRAM for each CPU to support the size of the
201 custom SMI handler.
202 **/
203 UINTN
204 EFIAPI
205 SmmCpuFeaturesGetSmiHandlerSize (
206 VOID
207 )
208 {
209 return 0;
210 }
211
212 /**
213 Install a custom SMI handler for the CPU specified by CpuIndex. This
214 function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size
215 is greater than zero and is called by the CPU that was elected as monarch
216 during System Management Mode initialization.
217
218 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
219 The value must be between 0 and the NumberOfCpus field
220 in the System Management System Table (SMST).
221 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
222 @param[in] SmiStack The stack to use when an SMI is processed by the
223 the CPU specified by CpuIndex.
224 @param[in] StackSize The size, in bytes, if the stack used when an SMI is
225 processed by the CPU specified by CpuIndex.
226 @param[in] GdtBase The base address of the GDT to use when an SMI is
227 processed by the CPU specified by CpuIndex.
228 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
229 processed by the CPU specified by CpuIndex.
230 @param[in] IdtBase The base address of the IDT to use when an SMI is
231 processed by the CPU specified by CpuIndex.
232 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
233 processed by the CPU specified by CpuIndex.
234 @param[in] Cr3 The base address of the page tables to use when an SMI
235 is processed by the CPU specified by CpuIndex.
236 **/
237 VOID
238 EFIAPI
239 SmmCpuFeaturesInstallSmiHandler (
240 IN UINTN CpuIndex,
241 IN UINT32 SmBase,
242 IN VOID *SmiStack,
243 IN UINTN StackSize,
244 IN UINTN GdtBase,
245 IN UINTN GdtSize,
246 IN UINTN IdtBase,
247 IN UINTN IdtSize,
248 IN UINT32 Cr3
249 )
250 {
251 }
252
253 /**
254 Determines if MTRR registers must be configured to set SMRAM cache-ability
255 when executing in System Management Mode.
256
257 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
258 @retval FALSE MTRR registers do not need to be configured to set SMRAM
259 cache-ability.
260 **/
261 BOOLEAN
262 EFIAPI
263 SmmCpuFeaturesNeedConfigureMtrrs (
264 VOID
265 )
266 {
267 return FALSE;
268 }
269
270 /**
271 Disable SMRR register if SMRR is supported and
272 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.
273 **/
274 VOID
275 EFIAPI
276 SmmCpuFeaturesDisableSmrr (
277 VOID
278 )
279 {
280 //
281 // No SMRR support, nothing to do
282 //
283 }
284
285 /**
286 Enable SMRR register if SMRR is supported and
287 SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.
288 **/
289 VOID
290 EFIAPI
291 SmmCpuFeaturesReenableSmrr (
292 VOID
293 )
294 {
295 //
296 // No SMRR support, nothing to do
297 //
298 }
299
300 /**
301 Processor specific hook point each time a CPU enters System Management Mode.
302
303 @param[in] CpuIndex The index of the CPU that has entered SMM. The value
304 must be between 0 and the NumberOfCpus field in the
305 System Management System Table (SMST).
306 **/
307 VOID
308 EFIAPI
309 SmmCpuFeaturesRendezvousEntry (
310 IN UINTN CpuIndex
311 )
312 {
313 //
314 // No SMRR support, nothing to do
315 //
316 }
317
318 /**
319 Processor specific hook point each time a CPU exits System Management Mode.
320
321 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value
322 must be between 0 and the NumberOfCpus field in the
323 System Management System Table (SMST).
324 **/
325 VOID
326 EFIAPI
327 SmmCpuFeaturesRendezvousExit (
328 IN UINTN CpuIndex
329 )
330 {
331 }
332
333 /**
334 Check to see if an SMM register is supported by a specified CPU.
335
336 @param[in] CpuIndex The index of the CPU to check for SMM register support.
337 The value must be between 0 and the NumberOfCpus field
338 in the System Management System Table (SMST).
339 @param[in] RegName Identifies the SMM register to check for support.
340
341 @retval TRUE The SMM register specified by RegName is supported by the CPU
342 specified by CpuIndex.
343 @retval FALSE The SMM register specified by RegName is not supported by the
344 CPU specified by CpuIndex.
345 **/
346 BOOLEAN
347 EFIAPI
348 SmmCpuFeaturesIsSmmRegisterSupported (
349 IN UINTN CpuIndex,
350 IN SMM_REG_NAME RegName
351 )
352 {
353 ASSERT (RegName == SmmRegFeatureControl);
354 return FALSE;
355 }
356
357 /**
358 Returns the current value of the SMM register for the specified CPU.
359 If the SMM register is not supported, then 0 is returned.
360
361 @param[in] CpuIndex The index of the CPU to read the SMM register. The
362 value must be between 0 and the NumberOfCpus field in
363 the System Management System Table (SMST).
364 @param[in] RegName Identifies the SMM register to read.
365
366 @return The value of the SMM register specified by RegName from the CPU
367 specified by CpuIndex.
368 **/
369 UINT64
370 EFIAPI
371 SmmCpuFeaturesGetSmmRegister (
372 IN UINTN CpuIndex,
373 IN SMM_REG_NAME RegName
374 )
375 {
376 //
377 // This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable.
378 // The last of these should actually be SmmRegSmmDisable, so we can just
379 // return FALSE.
380 //
381 return 0;
382 }
383
384 /**
385 Sets the value of an SMM register on a specified CPU.
386 If the SMM register is not supported, then no action is performed.
387
388 @param[in] CpuIndex The index of the CPU to write the SMM register. The
389 value must be between 0 and the NumberOfCpus field in
390 the System Management System Table (SMST).
391 @param[in] RegName Identifies the SMM register to write.
392 registers are read-only.
393 @param[in] Value The value to write to the SMM register.
394 **/
395 VOID
396 EFIAPI
397 SmmCpuFeaturesSetSmmRegister (
398 IN UINTN CpuIndex,
399 IN SMM_REG_NAME RegName,
400 IN UINT64 Value
401 )
402 {
403 ASSERT (FALSE);
404 }
405
406 ///
407 /// Macro used to simplify the lookup table entries of type
408 /// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
409 ///
410 #define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)
411
412 ///
413 /// Macro used to simplify the lookup table entries of type
414 /// CPU_SMM_SAVE_STATE_REGISTER_RANGE
415 ///
416 #define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
417
418 ///
419 /// Structure used to describe a range of registers
420 ///
421 typedef struct {
422 EFI_SMM_SAVE_STATE_REGISTER Start;
423 EFI_SMM_SAVE_STATE_REGISTER End;
424 UINTN Length;
425 } CPU_SMM_SAVE_STATE_REGISTER_RANGE;
426
427 ///
428 /// Structure used to build a lookup table to retrieve the widths and offsets
429 /// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
430 ///
431
432 #define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1
433
434 typedef struct {
435 UINT8 Width32;
436 UINT8 Width64;
437 UINT16 Offset32;
438 UINT16 Offset64Lo;
439 UINT16 Offset64Hi;
440 BOOLEAN Writeable;
441 } CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
442
443 ///
444 /// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
445 /// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
446 ///
447 static CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {
448 SMM_REGISTER_RANGE (
449 EFI_SMM_SAVE_STATE_REGISTER_GDTBASE,
450 EFI_SMM_SAVE_STATE_REGISTER_LDTINFO
451 ),
452 SMM_REGISTER_RANGE (
453 EFI_SMM_SAVE_STATE_REGISTER_ES,
454 EFI_SMM_SAVE_STATE_REGISTER_RIP
455 ),
456 SMM_REGISTER_RANGE (
457 EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,
458 EFI_SMM_SAVE_STATE_REGISTER_CR4
459 ),
460 { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }
461 };
462
463 ///
464 /// Lookup table used to retrieve the widths and offsets associated with each
465 /// supported EFI_SMM_SAVE_STATE_REGISTER value
466 ///
467 static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
468 {
469 0, // Width32
470 0, // Width64
471 0, // Offset32
472 0, // Offset64Lo
473 0, // Offset64Hi
474 FALSE // Writeable
475 }, // Reserved
476
477 //
478 // CPU Save State registers defined in PI SMM CPU Protocol.
479 //
480 {
481 0, // Width32
482 8, // Width64
483 0, // Offset32
484 SMM_CPU_OFFSET (x64._GDTRBase), // Offset64Lo
485 SMM_CPU_OFFSET (x64._GDTRBase) + 4, // Offset64Hi
486 FALSE // Writeable
487 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
488
489 {
490 0, // Width32
491 8, // Width64
492 0, // Offset32
493 SMM_CPU_OFFSET (x64._IDTRBase), // Offset64Lo
494 SMM_CPU_OFFSET (x64._IDTRBase) + 4, // Offset64Hi
495 FALSE // Writeable
496 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
497
498 {
499 0, // Width32
500 8, // Width64
501 0, // Offset32
502 SMM_CPU_OFFSET (x64._LDTRBase), // Offset64Lo
503 SMM_CPU_OFFSET (x64._LDTRBase) + 4, // Offset64Hi
504 FALSE // Writeable
505 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
506
507 {
508 0, // Width32
509 0, // Width64
510 0, // Offset32
511 SMM_CPU_OFFSET (x64._GDTRLimit), // Offset64Lo
512 SMM_CPU_OFFSET (x64._GDTRLimit) + 4, // Offset64Hi
513 FALSE // Writeable
514 }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
515
516 {
517 0, // Width32
518 0, // Width64
519 0, // Offset32
520 SMM_CPU_OFFSET (x64._IDTRLimit), // Offset64Lo
521 SMM_CPU_OFFSET (x64._IDTRLimit) + 4, // Offset64Hi
522 FALSE // Writeable
523 }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
524
525 {
526 0, // Width32
527 0, // Width64
528 0, // Offset32
529 SMM_CPU_OFFSET (x64._LDTRLimit), // Offset64Lo
530 SMM_CPU_OFFSET (x64._LDTRLimit) + 4, // Offset64Hi
531 FALSE // Writeable
532 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
533
534 {
535 0, // Width32
536 0, // Width64
537 0, // Offset32
538 0, // Offset64Lo
539 0 + 4, // Offset64Hi
540 FALSE // Writeable
541 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
542
543 {
544 4, // Width32
545 4, // Width64
546 SMM_CPU_OFFSET (x86._ES), // Offset32
547 SMM_CPU_OFFSET (x64._ES), // Offset64Lo
548 0, // Offset64Hi
549 FALSE // Writeable
550 }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
551
552 {
553 4, // Width32
554 4, // Width64
555 SMM_CPU_OFFSET (x86._CS), // Offset32
556 SMM_CPU_OFFSET (x64._CS), // Offset64Lo
557 0, // Offset64Hi
558 FALSE // Writeable
559 }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
560
561 {
562 4, // Width32
563 4, // Width64
564 SMM_CPU_OFFSET (x86._SS), // Offset32
565 SMM_CPU_OFFSET (x64._SS), // Offset64Lo
566 0, // Offset64Hi
567 FALSE // Writeable
568 }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
569
570 {
571 4, // Width32
572 4, // Width64
573 SMM_CPU_OFFSET (x86._DS), // Offset32
574 SMM_CPU_OFFSET (x64._DS), // Offset64Lo
575 0, // Offset64Hi
576 FALSE // Writeable
577 }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
578
579 {
580 4, // Width32
581 4, // Width64
582 SMM_CPU_OFFSET (x86._FS), // Offset32
583 SMM_CPU_OFFSET (x64._FS), // Offset64Lo
584 0, // Offset64Hi
585 FALSE // Writeable
586 }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
587
588 {
589 4, // Width32
590 4, // Width64
591 SMM_CPU_OFFSET (x86._GS), // Offset32
592 SMM_CPU_OFFSET (x64._GS), // Offset64Lo
593 0, // Offset64Hi
594 FALSE // Writeable
595 }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
596
597 {
598 0, // Width32
599 4, // Width64
600 0, // Offset32
601 SMM_CPU_OFFSET (x64._LDTR), // Offset64Lo
602 0, // Offset64Hi
603 FALSE // Writeable
604 }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
605
606 {
607 4, // Width32
608 4, // Width64
609 SMM_CPU_OFFSET (x86._TR), // Offset32
610 SMM_CPU_OFFSET (x64._TR), // Offset64Lo
611 0, // Offset64Hi
612 FALSE // Writeable
613 }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
614
615 {
616 4, // Width32
617 8, // Width64
618 SMM_CPU_OFFSET (x86._DR7), // Offset32
619 SMM_CPU_OFFSET (x64._DR7), // Offset64Lo
620 SMM_CPU_OFFSET (x64._DR7) + 4, // Offset64Hi
621 FALSE // Writeable
622 }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
623
624 {
625 4, // Width32
626 8, // Width64
627 SMM_CPU_OFFSET (x86._DR6), // Offset32
628 SMM_CPU_OFFSET (x64._DR6), // Offset64Lo
629 SMM_CPU_OFFSET (x64._DR6) + 4, // Offset64Hi
630 FALSE // Writeable
631 }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
632
633 {
634 0, // Width32
635 8, // Width64
636 0, // Offset32
637 SMM_CPU_OFFSET (x64._R8), // Offset64Lo
638 SMM_CPU_OFFSET (x64._R8) + 4, // Offset64Hi
639 TRUE // Writeable
640 }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
641
642 {
643 0, // Width32
644 8, // Width64
645 0, // Offset32
646 SMM_CPU_OFFSET (x64._R9), // Offset64Lo
647 SMM_CPU_OFFSET (x64._R9) + 4, // Offset64Hi
648 TRUE // Writeable
649 }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
650
651 {
652 0, // Width32
653 8, // Width64
654 0, // Offset32
655 SMM_CPU_OFFSET (x64._R10), // Offset64Lo
656 SMM_CPU_OFFSET (x64._R10) + 4, // Offset64Hi
657 TRUE // Writeable
658 }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
659
660 {
661 0, // Width32
662 8, // Width64
663 0, // Offset32
664 SMM_CPU_OFFSET (x64._R11), // Offset64Lo
665 SMM_CPU_OFFSET (x64._R11) + 4, // Offset64Hi
666 TRUE // Writeable
667 }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
668
669 {
670 0, // Width32
671 8, // Width64
672 0, // Offset32
673 SMM_CPU_OFFSET (x64._R12), // Offset64Lo
674 SMM_CPU_OFFSET (x64._R12) + 4, // Offset64Hi
675 TRUE // Writeable
676 }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
677
678 {
679 0, // Width32
680 8, // Width64
681 0, // Offset32
682 SMM_CPU_OFFSET (x64._R13), // Offset64Lo
683 SMM_CPU_OFFSET (x64._R13) + 4, // Offset64Hi
684 TRUE // Writeable
685 }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
686
687 {
688 0, // Width32
689 8, // Width64
690 0, // Offset32
691 SMM_CPU_OFFSET (x64._R14), // Offset64Lo
692 SMM_CPU_OFFSET (x64._R14) + 4, // Offset64Hi
693 TRUE // Writeable
694 }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
695
696 {
697 0, // Width32
698 8, // Width64
699 0, // Offset32
700 SMM_CPU_OFFSET (x64._R15), // Offset64Lo
701 SMM_CPU_OFFSET (x64._R15) + 4, // Offset64Hi
702 TRUE // Writeable
703 }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
704
705 {
706 4, // Width32
707 8, // Width64
708 SMM_CPU_OFFSET (x86._EAX), // Offset32
709 SMM_CPU_OFFSET (x64._RAX), // Offset64Lo
710 SMM_CPU_OFFSET (x64._RAX) + 4, // Offset64Hi
711 TRUE // Writeable
712 }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
713
714 {
715 4, // Width32
716 8, // Width64
717 SMM_CPU_OFFSET (x86._EBX), // Offset32
718 SMM_CPU_OFFSET (x64._RBX), // Offset64Lo
719 SMM_CPU_OFFSET (x64._RBX) + 4, // Offset64Hi
720 TRUE // Writeable
721 }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
722
723 {
724 4, // Width32
725 8, // Width64
726 SMM_CPU_OFFSET (x86._ECX), // Offset32
727 SMM_CPU_OFFSET (x64._RCX), // Offset64Lo
728 SMM_CPU_OFFSET (x64._RCX) + 4, // Offset64Hi
729 TRUE // Writeable
730 }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
731
732 {
733 4, // Width32
734 8, // Width64
735 SMM_CPU_OFFSET (x86._EDX), // Offset32
736 SMM_CPU_OFFSET (x64._RDX), // Offset64Lo
737 SMM_CPU_OFFSET (x64._RDX) + 4, // Offset64Hi
738 TRUE // Writeable
739 }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
740
741 {
742 4, // Width32
743 8, // Width64
744 SMM_CPU_OFFSET (x86._ESP), // Offset32
745 SMM_CPU_OFFSET (x64._RSP), // Offset64Lo
746 SMM_CPU_OFFSET (x64._RSP) + 4, // Offset64Hi
747 TRUE // Writeable
748 }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
749
750 {
751 4, // Width32
752 8, // Width64
753 SMM_CPU_OFFSET (x86._EBP), // Offset32
754 SMM_CPU_OFFSET (x64._RBP), // Offset64Lo
755 SMM_CPU_OFFSET (x64._RBP) + 4, // Offset64Hi
756 TRUE // Writeable
757 }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
758
759 {
760 4, // Width32
761 8, // Width64
762 SMM_CPU_OFFSET (x86._ESI), // Offset32
763 SMM_CPU_OFFSET (x64._RSI), // Offset64Lo
764 SMM_CPU_OFFSET (x64._RSI) + 4, // Offset64Hi
765 TRUE // Writeable
766 }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
767
768 {
769 4, // Width32
770 8, // Width64
771 SMM_CPU_OFFSET (x86._EDI), // Offset32
772 SMM_CPU_OFFSET (x64._RDI), // Offset64Lo
773 SMM_CPU_OFFSET (x64._RDI) + 4, // Offset64Hi
774 TRUE // Writeable
775 }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
776
777 {
778 4, // Width32
779 8, // Width64
780 SMM_CPU_OFFSET (x86._EIP), // Offset32
781 SMM_CPU_OFFSET (x64._RIP), // Offset64Lo
782 SMM_CPU_OFFSET (x64._RIP) + 4, // Offset64Hi
783 TRUE // Writeable
784 }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
785
786 {
787 4, // Width32
788 8, // Width64
789 SMM_CPU_OFFSET (x86._EFLAGS), // Offset32
790 SMM_CPU_OFFSET (x64._RFLAGS), // Offset64Lo
791 SMM_CPU_OFFSET (x64._RFLAGS) + 4, // Offset64Hi
792 TRUE // Writeable
793 }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
794
795 {
796 4, // Width32
797 8, // Width64
798 SMM_CPU_OFFSET (x86._CR0), // Offset32
799 SMM_CPU_OFFSET (x64._CR0), // Offset64Lo
800 SMM_CPU_OFFSET (x64._CR0) + 4, // Offset64Hi
801 FALSE // Writeable
802 }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
803
804 {
805 4, // Width32
806 8, // Width64
807 SMM_CPU_OFFSET (x86._CR3), // Offset32
808 SMM_CPU_OFFSET (x64._CR3), // Offset64Lo
809 SMM_CPU_OFFSET (x64._CR3) + 4, // Offset64Hi
810 FALSE // Writeable
811 }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
812
813 {
814 0, // Width32
815 4, // Width64
816 0, // Offset32
817 SMM_CPU_OFFSET (x64._CR4), // Offset64Lo
818 SMM_CPU_OFFSET (x64._CR4) + 4, // Offset64Hi
819 FALSE // Writeable
820 }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
821 };
822
823 //
824 // No support for I/O restart
825 //
826
827 /**
828 Read information from the CPU save state.
829
830 @param Register Specifies the CPU register to read form the save state.
831
832 @retval 0 Register is not valid
833 @retval >0 Index into mSmmCpuWidthOffset[] associated with Register
834
835 **/
836 static UINTN
837 GetRegisterIndex (
838 IN EFI_SMM_SAVE_STATE_REGISTER Register
839 )
840 {
841 UINTN Index;
842 UINTN Offset;
843
844 for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX;
845 mSmmCpuRegisterRanges[Index].Length != 0;
846 Index++) {
847 if (Register >= mSmmCpuRegisterRanges[Index].Start &&
848 Register <= mSmmCpuRegisterRanges[Index].End) {
849 return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
850 }
851 Offset += mSmmCpuRegisterRanges[Index].Length;
852 }
853 return 0;
854 }
855
856 /**
857 Read a CPU Save State register on the target processor.
858
859 This function abstracts the differences that whether the CPU Save State
860 register is in the IA32 CPU Save State Map or X64 CPU Save State Map.
861
862 This function supports reading a CPU Save State register in SMBase relocation
863 handler.
864
865 @param[in] CpuIndex Specifies the zero-based index of the CPU save
866 state.
867 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
868 @param[in] Width The number of bytes to read from the CPU save
869 state.
870 @param[out] Buffer Upon return, this holds the CPU register value
871 read from the save state.
872
873 @retval EFI_SUCCESS The register was read from Save State.
874 @retval EFI_NOT_FOUND The register is not defined for the Save State
875 of Processor.
876 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
877
878 **/
879 static EFI_STATUS
880 ReadSaveStateRegisterByIndex (
881 IN UINTN CpuIndex,
882 IN UINTN RegisterIndex,
883 IN UINTN Width,
884 OUT VOID *Buffer
885 )
886 {
887 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
888
889 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
890
891 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
892 //
893 // If 32-bit mode width is zero, then the specified register can not be
894 // accessed
895 //
896 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
897 return EFI_NOT_FOUND;
898 }
899
900 //
901 // If Width is bigger than the 32-bit mode width, then the specified
902 // register can not be accessed
903 //
904 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
905 return EFI_INVALID_PARAMETER;
906 }
907
908 //
909 // Write return buffer
910 //
911 ASSERT(CpuSaveState != NULL);
912 CopyMem (
913 Buffer,
914 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,
915 Width
916 );
917 } else {
918 //
919 // If 64-bit mode width is zero, then the specified register can not be
920 // accessed
921 //
922 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
923 return EFI_NOT_FOUND;
924 }
925
926 //
927 // If Width is bigger than the 64-bit mode width, then the specified
928 // register can not be accessed
929 //
930 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
931 return EFI_INVALID_PARAMETER;
932 }
933
934 //
935 // Write lower 32-bits of return buffer
936 //
937 CopyMem (
938 Buffer,
939 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,
940 MIN (4, Width)
941 );
942 if (Width >= 4) {
943 //
944 // Write upper 32-bits of return buffer
945 //
946 CopyMem (
947 (UINT8 *)Buffer + 4,
948 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,
949 Width - 4
950 );
951 }
952 }
953 return EFI_SUCCESS;
954 }
955
956 /**
957 Read an SMM Save State register on the target processor. If this function
958 returns EFI_UNSUPPORTED, then the caller is responsible for reading the
959 SMM Save Sate register.
960
961 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
962 value must be between 0 and the NumberOfCpus field in
963 the System Management System Table (SMST).
964 @param[in] Register The SMM Save State register to read.
965 @param[in] Width The number of bytes to read from the CPU save state.
966 @param[out] Buffer Upon return, this holds the CPU register value read
967 from the save state.
968
969 @retval EFI_SUCCESS The register was read from Save State.
970 @retval EFI_INVALID_PARAMTER Buffer is NULL.
971 @retval EFI_UNSUPPORTED This function does not support reading
972 Register.
973 **/
974 EFI_STATUS
975 EFIAPI
976 SmmCpuFeaturesReadSaveStateRegister (
977 IN UINTN CpuIndex,
978 IN EFI_SMM_SAVE_STATE_REGISTER Register,
979 IN UINTN Width,
980 OUT VOID *Buffer
981 )
982 {
983 UINTN RegisterIndex;
984 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
985
986 //
987 // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
988 //
989 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
990 //
991 // Only byte access is supported for this register
992 //
993 if (Width != 1) {
994 return EFI_INVALID_PARAMETER;
995 }
996
997 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
998
999 //
1000 // Check CPU mode
1001 //
1002 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
1003 *(UINT8 *)Buffer = 32;
1004 } else {
1005 *(UINT8 *)Buffer = 64;
1006 }
1007
1008 return EFI_SUCCESS;
1009 }
1010
1011 //
1012 // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO
1013 //
1014 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
1015 return EFI_NOT_FOUND;
1016 }
1017
1018 //
1019 // Convert Register to a register lookup table index. Let
1020 // PiSmmCpuDxeSmm implement other special registers (currently
1021 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
1022 //
1023 RegisterIndex = GetRegisterIndex (Register);
1024 if (RegisterIndex == 0) {
1025 return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?
1026 EFI_NOT_FOUND :
1027 EFI_UNSUPPORTED);
1028 }
1029
1030 return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buffer);
1031 }
1032
1033 /**
1034 Writes an SMM Save State register on the target processor. If this function
1035 returns EFI_UNSUPPORTED, then the caller is responsible for writing the
1036 SMM Save Sate register.
1037
1038 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The
1039 value must be between 0 and the NumberOfCpus field in
1040 the System Management System Table (SMST).
1041 @param[in] Register The SMM Save State register to write.
1042 @param[in] Width The number of bytes to write to the CPU save state.
1043 @param[in] Buffer Upon entry, this holds the new CPU register value.
1044
1045 @retval EFI_SUCCESS The register was written to Save State.
1046 @retval EFI_INVALID_PARAMTER Buffer is NULL.
1047 @retval EFI_UNSUPPORTED This function does not support writing
1048 Register.
1049 **/
1050 EFI_STATUS
1051 EFIAPI
1052 SmmCpuFeaturesWriteSaveStateRegister (
1053 IN UINTN CpuIndex,
1054 IN EFI_SMM_SAVE_STATE_REGISTER Register,
1055 IN UINTN Width,
1056 IN CONST VOID *Buffer
1057 )
1058 {
1059 UINTN RegisterIndex;
1060 QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
1061
1062 //
1063 // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
1064 //
1065 if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
1066 return EFI_SUCCESS;
1067 }
1068
1069 //
1070 // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported
1071 //
1072 if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
1073 return EFI_NOT_FOUND;
1074 }
1075
1076 //
1077 // Convert Register to a register lookup table index. Let
1078 // PiSmmCpuDxeSmm implement other special registers (currently
1079 // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
1080 //
1081 RegisterIndex = GetRegisterIndex (Register);
1082 if (RegisterIndex == 0) {
1083 return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?
1084 EFI_NOT_FOUND :
1085 EFI_UNSUPPORTED);
1086 }
1087
1088 CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
1089
1090 //
1091 // Do not write non-writable SaveState, because it will cause exception.
1092 //
1093 if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {
1094 return EFI_UNSUPPORTED;
1095 }
1096
1097 //
1098 // Check CPU mode
1099 //
1100 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
1101 //
1102 // If 32-bit mode width is zero, then the specified register can not be
1103 // accessed
1104 //
1105 if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
1106 return EFI_NOT_FOUND;
1107 }
1108
1109 //
1110 // If Width is bigger than the 32-bit mode width, then the specified
1111 // register can not be accessed
1112 //
1113 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
1114 return EFI_INVALID_PARAMETER;
1115 }
1116 //
1117 // Write SMM State register
1118 //
1119 ASSERT (CpuSaveState != NULL);
1120 CopyMem (
1121 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,
1122 Buffer,
1123 Width
1124 );
1125 } else {
1126 //
1127 // If 64-bit mode width is zero, then the specified register can not be
1128 // accessed
1129 //
1130 if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
1131 return EFI_NOT_FOUND;
1132 }
1133
1134 //
1135 // If Width is bigger than the 64-bit mode width, then the specified
1136 // register can not be accessed
1137 //
1138 if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
1139 return EFI_INVALID_PARAMETER;
1140 }
1141
1142 //
1143 // Write lower 32-bits of SMM State register
1144 //
1145 CopyMem (
1146 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,
1147 Buffer,
1148 MIN (4, Width)
1149 );
1150 if (Width >= 4) {
1151 //
1152 // Write upper 32-bits of SMM State register
1153 //
1154 CopyMem (
1155 (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,
1156 (UINT8 *)Buffer + 4,
1157 Width - 4
1158 );
1159 }
1160 }
1161 return EFI_SUCCESS;
1162 }
1163
1164 /**
1165 This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
1166 notification is completely processed.
1167 **/
1168 VOID
1169 EFIAPI
1170 SmmCpuFeaturesCompleteSmmReadyToLock (
1171 VOID
1172 )
1173 {
1174 }
1175
1176 /**
1177 This API provides a method for a CPU to allocate a specific region for
1178 storing page tables.
1179
1180 This API can be called more once to allocate memory for page tables.
1181
1182 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns
1183 a pointer to the allocated buffer. The buffer returned is aligned on a 4KB
1184 boundary. If Pages is 0, then NULL is returned. If there is not enough
1185 memory remaining to satisfy the request, then NULL is returned.
1186
1187 This function can also return NULL if there is no preference on where the
1188 page tables are allocated in SMRAM.
1189
1190 @param Pages The number of 4 KB pages to allocate.
1191
1192 @return A pointer to the allocated buffer for page tables.
1193 @retval NULL Fail to allocate a specific region for storing page tables,
1194 Or there is no preference on where the page tables are
1195 allocated in SMRAM.
1196
1197 **/
1198 VOID *
1199 EFIAPI
1200 SmmCpuFeaturesAllocatePageTableMemory (
1201 IN UINTN Pages
1202 )
1203 {
1204 return NULL;
1205 }
1206
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