OvmfPkg/OvmfPkg.dec

   1 ## @file
   2 #  EFI/Framework Open Virtual Machine Firmware (OVMF) platform
   3 #
   4 #  Copyright (c) 2020, Rebecca Cran <rebecca@bsdio.com>
   5 #  Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
   6 #  Copyright (c) 2014, Pluribus Networks, Inc.
   7 #
   8 #  SPDX-License-Identifier: BSD-2-Clause-Patent
   9 #
  10 ##
  11
  12 [Defines]
  13   DEC_SPECIFICATION              = 0x00010005
  14   PACKAGE_NAME                   = OvmfPkg
  15   PACKAGE_GUID                   = 2daf5f34-50e5-4b9d-b8e3-5562334d87e5
  16   PACKAGE_VERSION                = 0.1
  17
  18 [Includes]
  19   Include
  20   Csm/Include
  21
  22 [LibraryClasses]
  23   ##  @libraryclass  Access bhyve's firmware control interface.
  24   BhyveFwCtlLib|Include/Library/BhyveFwCtlLib.h
  25
  26   ##  @libraryclass  Verify blobs read from the VMM
  27   BlobVerifierLib|Include/Library/BlobVerifierLib.h
  28
  29   ##  @libraryclass  Loads and boots a Linux kernel image
  30   #
  31   LoadLinuxLib|Include/Library/LoadLinuxLib.h
  32
  33   ##  @libraryclass  Declares helper functions for Secure Encrypted
  34   #                  Virtualization (SEV) guests.
  35   MemEncryptSevLib|Include/Library/MemEncryptSevLib.h
  36
  37   ##  @libraryclass  Declares helper functions for TDX guests.
  38   #
  39   MemEncryptTdxLib|Include/Library/MemEncryptTdxLib.h
  40
  41   ##  @libraryclass  Save and restore variables using a file
  42   #
  43   NvVarsFileLib|Include/Library/NvVarsFileLib.h
  44
  45   ##  @libraryclass  Provides services to work with PCI capabilities in PCI
  46   #                  config space.
  47   PciCapLib|Include/Library/PciCapLib.h
  48
  49   ##  @libraryclass  Layered on top of PciCapLib, allows clients to plug an
  50   #                  EFI_PCI_IO_PROTOCOL backend into PciCapLib, for config
  51   #                  space access.
  52   PciCapPciIoLib|Include/Library/PciCapPciIoLib.h
  53
  54   ##  @libraryclass  Layered on top of PciCapLib, allows clients to plug a
  55   #                  PciSegmentLib backend into PciCapLib, for config space
  56   #                  access.
  57   PciCapPciSegmentLib|Include/Library/PciCapPciSegmentLib.h
  58
  59   ##  @libraryclass  Provide common utility functions to PciHostBridgeLib
  60   #                  instances in ArmVirtPkg and OvmfPkg.
  61   PciHostBridgeUtilityLib|Include/Library/PciHostBridgeUtilityLib.h
  62
  63   ##  @libraryclass  Register a status code handler for printing the Boot
  64   #                  Manager's LoadImage() and StartImage() preparations, and
  65   #                  return codes, to the UEFI console.
  66   PlatformBmPrintScLib|Include/Library/PlatformBmPrintScLib.h
  67
  68   ##  @libraryclass  Customize FVB2 protocol member functions for a platform.
  69   PlatformFvbLib|Include/Library/PlatformFvbLib.h
  70
  71   ##  @libraryclass  Access QEMU's firmware configuration interface
  72   #
  73   QemuFwCfgLib|Include/Library/QemuFwCfgLib.h
  74
  75   ##  @libraryclass  S3 support for QEMU fw_cfg
  76   #
  77   QemuFwCfgS3Lib|Include/Library/QemuFwCfgS3Lib.h
  78
  79   ##  @libraryclass  Parse the contents of named fw_cfg files as simple
  80   #                  (scalar) data types.
  81   QemuFwCfgSimpleParserLib|Include/Library/QemuFwCfgSimpleParserLib.h
  82
  83   ##  @libraryclass  Rewrite the BootOrder NvVar based on QEMU's "bootorder"
  84   #                  fw_cfg file.
  85   #
  86   QemuBootOrderLib|Include/Library/QemuBootOrderLib.h
  87
  88   ##  @libraryclass  Load a kernel image and command line passed to QEMU via
  89   #                  the command line
  90   #
  91   QemuLoadImageLib|Include/Library/QemuLoadImageLib.h
  92
  93   ##  @libraryclass  Serialize (and deserialize) variables
  94   #
  95   SerializeVariablesLib|Include/Library/SerializeVariablesLib.h
  96
  97   ##  @libraryclass  Declares utility functions for virtio device drivers.
  98   VirtioLib|Include/Library/VirtioLib.h
  99
 100   ##  @libraryclass  Install Virtio Device Protocol instances on virtio-mmio
 101   #                  transports.
 102   VirtioMmioDeviceLib|Include/Library/VirtioMmioDeviceLib.h
 103
 104   ##  @libraryclass  Invoke Xen hypercalls
 105   #
 106   XenHypercallLib|Include/Library/XenHypercallLib.h
 107
 108   ##  @libraryclass  Manage XenBus device path and I/O handles
 109   #
 110   XenIoMmioLib|Include/Library/XenIoMmioLib.h
 111
 112   ##  @libraryclass  Get information about Xen
 113   #
 114   XenPlatformLib|Include/Library/XenPlatformLib.h
 115
 116   ##  @libraryclass  TdxMailboxLib
 117   #
 118   TdxMailboxLib|Include/Library/TdxMailboxLib.h
 119
 120   ##  @libraryclass  PlatformInitLib
 121   #
 122   PlatformInitLib|Include/Library/PlatformInitLib.h
 123
 124 [Guids]
 125   gUefiOvmfPkgTokenSpaceGuid            = {0x93bb96af, 0xb9f2, 0x4eb8, {0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}}
 126   gEfiXenInfoGuid                       = {0xd3b46f3b, 0xd441, 0x1244, {0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}}
 127   gOvmfPkKek1AppPrefixGuid              = {0x4e32566d, 0x8e9e, 0x4f52, {0x81, 0xd3, 0x5b, 0xb9, 0x71, 0x5f, 0x97, 0x27}}
 128   gOvmfPlatformConfigGuid               = {0x7235c51c, 0x0c80, 0x4cab, {0x87, 0xac, 0x3b, 0x08, 0x4a, 0x63, 0x04, 0xb1}}
 129   gVirtioMmioTransportGuid              = {0x837dca9e, 0xe874, 0x4d82, {0xb2, 0x9a, 0x23, 0xfe, 0x0e, 0x23, 0xd1, 0xe2}}
 130   gQemuRamfbGuid                        = {0x557423a1, 0x63ab, 0x406c, {0xbe, 0x7e, 0x91, 0xcd, 0xbc, 0x08, 0xc4, 0x57}}
 131   gXenBusRootDeviceGuid                 = {0xa732241f, 0x383d, 0x4d9c, {0x8a, 0xe1, 0x8e, 0x09, 0x83, 0x75, 0x89, 0xd7}}
 132   gRootBridgesConnectedEventGroupGuid   = {0x24a2d66f, 0xeedd, 0x4086, {0x90, 0x42, 0xf2, 0x6e, 0x47, 0x97, 0xee, 0x69}}
 133   gMicrosoftVendorGuid                  = {0x77fa9abd, 0x0359, 0x4d32, {0xbd, 0x60, 0x28, 0xf4, 0xe7, 0x8f, 0x78, 0x4b}}
 134   gEfiLegacyBiosGuid                    = {0x2E3044AC, 0x879F, 0x490F, {0x97, 0x60, 0xBB, 0xDF, 0xAF, 0x69, 0x5F, 0x50}}
 135   gEfiLegacyDevOrderVariableGuid        = {0xa56074db, 0x65fe, 0x45f7, {0xbd, 0x21, 0x2d, 0x2b, 0xdd, 0x8e, 0x96, 0x52}}
 136   gQemuKernelLoaderFsMediaGuid          = {0x1428f772, 0xb64a, 0x441e, {0xb8, 0xc3, 0x9e, 0xbd, 0xd7, 0xf8, 0x93, 0xc7}}
 137   gGrubFileGuid                         = {0xb5ae312c, 0xbc8a, 0x43b1, {0x9c, 0x62, 0xeb, 0xb8, 0x26, 0xdd, 0x5d, 0x07}}
 138   gConfidentialComputingSecretGuid      = {0xadf956ad, 0xe98c, 0x484c, {0xae, 0x11, 0xb5, 0x1c, 0x7d, 0x33, 0x64, 0x47}}
 139   gConfidentialComputingSevSnpBlobGuid  = {0x067b1f5f, 0xcf26, 0x44c5, {0x85, 0x54, 0x93, 0xd7, 0x77, 0x91, 0x2d, 0x42}}
 140   gUefiOvmfPkgPlatformInfoGuid          = {0xdec9b486, 0x1f16, 0x47c7, {0x8f, 0x68, 0xdf, 0x1a, 0x41, 0x88, 0x8b, 0xa5}}
 141
 142 [Ppis]
 143   # PPI whose presence in the PPI database signals that the TPM base address
 144   # has been discovered and recorded
 145   gOvmfTpmDiscoveredPpiGuid             = {0xb9a61ad0, 0x2802, 0x41f3, {0xb5, 0x13, 0x96, 0x51, 0xce, 0x6b, 0xd5, 0x75}}
 146
 147   # This PPI signals that accessing the MMIO range of the TPM is possible in
 148   # the PEI phase, regardless of memory encryption
 149   gOvmfTpmMmioAccessiblePpiGuid         = {0x35c84ff2, 0x7bfe, 0x453d, {0x84, 0x5f, 0x68, 0x3a, 0x49, 0x2c, 0xf7, 0xb7}}
 150
 151 [Protocols]
 152   gVirtioDeviceProtocolGuid             = {0xfa920010, 0x6785, 0x4941, {0xb6, 0xec, 0x49, 0x8c, 0x57, 0x9f, 0x16, 0x0a}}
 153   gXenBusProtocolGuid                   = {0x3d3ca290, 0xb9a5, 0x11e3, {0xb7, 0x5d, 0xb8, 0xac, 0x6f, 0x7d, 0x65, 0xe6}}
 154   gXenIoProtocolGuid                    = {0x6efac84f, 0x0ab0, 0x4747, {0x81, 0xbe, 0x85, 0x55, 0x62, 0x59, 0x04, 0x49}}
 155   gIoMmuAbsentProtocolGuid              = {0xf8775d50, 0x8abd, 0x4adf, {0x92, 0xac, 0x85, 0x3e, 0x51, 0xf6, 0xc8, 0xdc}}
 156   gEfiLegacy8259ProtocolGuid            = {0x38321dba, 0x4fe0, 0x4e17, {0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1}}
 157   gEfiFirmwareVolumeProtocolGuid        = {0x389F751F, 0x1838, 0x4388, {0x83, 0x90, 0xcd, 0x81, 0x54, 0xbd, 0x27, 0xf8}}
 158   gEfiIsaAcpiProtocolGuid               = {0x64a892dc, 0x5561, 0x4536, {0x92, 0xc7, 0x79, 0x9b, 0xfc, 0x18, 0x33, 0x55}}
 159   gEfiIsaIoProtocolGuid                 = {0x7ee2bd44, 0x3da0, 0x11d4, {0x9a, 0x38, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}}
 160   gEfiLegacyBiosProtocolGuid            = {0xdb9a1e3d, 0x45cb, 0x4abb, {0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d}}
 161   gEfiLegacyBiosPlatformProtocolGuid    = {0x783658a3, 0x4172, 0x4421, {0xa2, 0x99, 0xe0, 0x09, 0x07, 0x9c, 0x0c, 0xb4}}
 162   gEfiLegacyInterruptProtocolGuid       = {0x31ce593d, 0x108a, 0x485d, {0xad, 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66, 0xbe}}
 163   gEfiVgaMiniPortProtocolGuid           = {0xc7735a2f, 0x88f5, 0x4882, {0xae, 0x63, 0xfa, 0xac, 0x8c, 0x8b, 0x86, 0xb3}}
 164   gOvmfLoadedX86LinuxKernelProtocolGuid = {0xa3edc05d, 0xb618, 0x4ff6, {0x95, 0x52, 0x76, 0xd7, 0x88, 0x63, 0x43, 0xc8}}
 165
 166 [PcdsFixedAtBuild]
 167   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase|0x0|UINT32|0
 168   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize|0x0|UINT32|1
 169   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|0x0|UINT32|0x15
 170   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize|0x0|UINT32|0x16
 171
 172   ## This flag is used to control the destination port for PlatformDebugLibIoPort
 173   gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort|0x402|UINT16|4
 174
 175   ## When VirtioScsiDxe is instantiated for a HBA, the numbers of targets and
 176   #  LUNs are retrieved from the host during virtio-scsi setup.
 177   #  MdeModulePkg/Bus/Scsi/ScsiBusDxe then scans all MaxTarget * MaxLun
 178   #  possible devices. This can take extremely long, for example with
 179   #  MaxTarget=255 and MaxLun=16383. The *inclusive* constants below limit
 180   #  MaxTarget and MaxLun, independently, should the host report higher values,
 181   #  so that scanning the number of devices given by their product is still
 182   #  acceptably fast.
 183   gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxTargetLimit|31|UINT16|6
 184   gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit|7|UINT32|7
 185
 186   ## Sets the *inclusive* number of targets and LUNs that PvScsi exposes for
 187   #  scan by ScsiBusDxe.
 188   #  As specified above for VirtioScsi, ScsiBusDxe scans all MaxTarget * MaxLun
 189   #  possible devices, which can take extremely long. Thus, the below constants
 190   #  are used so that scanning the number of devices given by their product
 191   #  is still acceptably fast.
 192   gUefiOvmfPkgTokenSpaceGuid.PcdPvScsiMaxTargetLimit|64|UINT8|0x36
 193   gUefiOvmfPkgTokenSpaceGuid.PcdPvScsiMaxLunLimit|0|UINT8|0x37
 194
 195   ## After PvScsiDxe sends a SCSI request to the device, it waits for
 196   #  the request completion in a polling loop.
 197   #  This constant defines how many micro-seconds to wait between each
 198   #  polling loop iteration.
 199   gUefiOvmfPkgTokenSpaceGuid.PcdPvScsiWaitForCmpStallInUsecs|5|UINT32|0x38
 200
 201   ## Set the *inclusive* number of targets that MptScsi exposes for scan
 202   #  by ScsiBusDxe.
 203   gUefiOvmfPkgTokenSpaceGuid.PcdMptScsiMaxTargetLimit|7|UINT8|0x39
 204
 205   ## Microseconds to stall between polling for MptScsi request result
 206   gUefiOvmfPkgTokenSpaceGuid.PcdMptScsiStallPerPollUsec|5|UINT32|0x3a
 207
 208   ## Set the *inclusive* number of targets and LUNs that LsiScsi exposes for
 209   #  scan by ScsiBusDxe.
 210   gUefiOvmfPkgTokenSpaceGuid.PcdLsiScsiMaxTargetLimit|7|UINT8|0x3b
 211   gUefiOvmfPkgTokenSpaceGuid.PcdLsiScsiMaxLunLimit|0|UINT8|0x3c
 212
 213   ## Microseconds to stall between polling for LsiScsi request result
 214   gUefiOvmfPkgTokenSpaceGuid.PcdLsiScsiStallPerPollUsec|5|UINT32|0x3d
 215
 216   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|0x8
 217   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|0x9
 218   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0xa
 219   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0|UINT32|0xb
 220   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT32|0xc
 221   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT32|0xd
 222   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase|0x0|UINT32|0xe
 223   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress|0x0|UINT32|0xf
 224   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase|0x0|UINT32|0x11
 225   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize|0x0|UINT32|0x12
 226   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|0x0|UINT32|0x13
 227   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize|0x0|UINT32|0x14
 228   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase|0x0|UINT32|0x18
 229   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize|0x0|UINT32|0x19
 230   gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|UINT32|0x1a
 231   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd|0x0|UINT32|0x1f
 232
 233   ## Pcd8259LegacyModeMask defines the default mask value for platform. This
 234   #  value is determined.
 235   #  1) If platform only support pure UEFI, value should be set to 0xFFFF or
 236   #     0xFFFE; Because only clock interrupt is allowed in legacy mode in pure
 237   #     UEFI platform.
 238   #  2) If platform install CSM and use thunk module:
 239   #     a) If thunk call provided by CSM binary requires some legacy interrupt
 240   #        support, the corresponding bit should be opened as 0.
 241   #        For example, if keyboard interfaces provided CSM binary use legacy
 242   #        keyboard interrupt in 8259 bit 1, then the value should be set to
 243   #        0xFFFC.
 244   #     b) If all thunk call provied by CSM binary do not require legacy
 245   #        interrupt support, value should be set to 0xFFFF or 0xFFFE.
 246   #
 247   #  The default value of legacy mode mask could be changed by
 248   #  EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely need change it
 249   #  except some special cases such as when initializing the CSM binary, it
 250   #  should be set to 0xFFFF to mask all legacy interrupt. Please restore the
 251   #  original legacy mask value if changing is made for these special case.
 252   gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF|UINT16|0x3
 253
 254   ## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy
 255   #  mode's interrrupt controller.
 256   #  For the corresponding bits, 0 = Edge triggered and 1 = Level triggered.
 257   gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x0000|UINT16|0x5
 258
 259   ## Indicates if BiosVideo driver will switch to 80x25 Text VGA Mode when
 260   #  exiting boot service.
 261   #   TRUE  - Switch to Text VGA Mode.
 262   #   FALSE - Does not switch to Text VGA Mode.
 263   gUefiOvmfPkgTokenSpaceGuid.PcdBiosVideoSetTextVgaModeEnable|FALSE|BOOLEAN|0x28
 264
 265   ## Indicates if BiosVideo driver will check for VESA BIOS Extension service
 266   #  support.
 267   #   TRUE  - Check for VESA BIOS Extension service.
 268   #   FALSE - Does not check for VESA BIOS Extension service.
 269   gUefiOvmfPkgTokenSpaceGuid.PcdBiosVideoCheckVbeEnable|TRUE|BOOLEAN|0x29
 270
 271   ## Indicates if BiosVideo driver will check for VGA service support.
 272   #  NOTE: If both PcdBiosVideoCheckVbeEnable and PcdBiosVideoCheckVgaEnable
 273   #  are set to FALSE, that means Graphics Output protocol will not be
 274   #  installed, the VGA miniport protocol will be installed instead.
 275   #   TRUE  - Check for VGA service.<BR>
 276   #   FALSE - Does not check for VGA service.<BR>
 277   gUefiOvmfPkgTokenSpaceGuid.PcdBiosVideoCheckVgaEnable|TRUE|BOOLEAN|0x2a
 278
 279   ## Indicates if memory space for legacy region will be set as cacheable.
 280   #   TRUE  - Set cachebility for legacy region.
 281   #   FALSE - Does not set cachebility for legacy region.
 282   gUefiOvmfPkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion|TRUE|BOOLEAN|0x2b
 283
 284   ## Specify memory size with bytes to reserve EBDA below 640K for OPROM.
 285   #  The value should be a multiple of 4KB.
 286   gUefiOvmfPkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x8000|UINT32|0x2c
 287
 288   ## Specify memory base address for OPROM to find free memory.
 289   #  Some OPROMs do not use EBDA or PMM to allocate memory for its usage,
 290   #  instead they find the memory filled with zero from 0x20000.
 291   #  The value should be a multiple of 4KB.
 292   #  The range should be below the EBDA reserved range from
 293   #  (CONVENTIONAL_MEMORY_TOP - Reserved EBDA Memory Size) to
 294   #  CONVENTIONAL_MEMORY_TOP.
 295   gUefiOvmfPkgTokenSpaceGuid.PcdOpromReservedMemoryBase|0x60000|UINT32|0x2d
 296
 297   ## Specify memory size with bytes for OPROM to find free memory.
 298   #  The value should be a multiple of 4KB. And the range should be below the
 299   #  EBDA reserved range from
 300   #  (CONVENTIONAL_MEMORY_TOP - Reserved EBDA Memory Size) to
 301   #  CONVENTIONAL_MEMORY_TOP.
 302   gUefiOvmfPkgTokenSpaceGuid.PcdOpromReservedMemorySize|0x28000|UINT32|0x2e
 303
 304   ## Specify the end of address below 1MB for the OPROM.
 305   #  The last shadowed OpROM should not exceed this address.
 306   gUefiOvmfPkgTokenSpaceGuid.PcdEndOpromShadowAddress|0xdffff|UINT32|0x2f
 307
 308   ## Specify the low PMM (Post Memory Manager) size with bytes below 1MB.
 309   #  The value should be a multiple of 4KB.
 310   # @Prompt Low PMM (Post Memory Manager) Size
 311   gUefiOvmfPkgTokenSpaceGuid.PcdLowPmmMemorySize|0x10000|UINT32|0x30
 312
 313   ## Specify the high PMM (Post Memory Manager) size with bytes above 1MB.
 314   #  The value should be a multiple of 4KB.
 315   gUefiOvmfPkgTokenSpaceGuid.PcdHighPmmMemorySize|0x400000|UINT32|0x31
 316
 317   gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtr|0x0|UINT32|0x17
 318   gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtrSize|0x0|UINT32|0x32
 319
 320   ## Number of page frames to use for storing grant table entries.
 321   gUefiOvmfPkgTokenSpaceGuid.PcdXenGrantFrames|4|UINT32|0x33
 322
 323   ## Specify the extra page table needed to mark the GHCB as unencrypted.
 324   #  The value should be a multiple of 4KB for each.
 325   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase|0x0|UINT32|0x3e
 326   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize|0x0|UINT32|0x3f
 327
 328   ## The base address of the SEC GHCB page used by SEV-ES.
 329   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase|0|UINT32|0x40
 330   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize|0|UINT32|0x41
 331   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase|0|UINT32|0x44
 332   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize|0|UINT32|0x45
 333
 334   ## The base address and size of the SEV Launch Secret Area provisioned
 335   #  after remote attestation.  If this is set in the .fdf, the platform
 336   #  is responsible for protecting the area from DXE phase overwrites.
 337   gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretBase|0x0|UINT32|0x42
 338   gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretSize|0x0|UINT32|0x43
 339
 340   ## The base address and size of a hash table confirming allowed
 341   #  parameters to be passed in via the Qemu firmware configuration
 342   #  device
 343   gUefiOvmfPkgTokenSpaceGuid.PcdQemuHashTableBase|0x0|UINT32|0x47
 344   gUefiOvmfPkgTokenSpaceGuid.PcdQemuHashTableSize|0x0|UINT32|0x48
 345
 346   ## The base address and size of the work area used during the SEC
 347   # phase by the SEV and TDX supports.
 348   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase|0|UINT32|0x49
 349   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize|0|UINT32|0x50
 350
 351   ## The work area contains a fixed size header in the Include/WorkArea.h.
 352   # The size of this header is used early boot, and is provided through
 353   # a fixed PCD. It need to be kept in sync with any changes to the
 354   # header definition.
 355   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader|4|UINT32|0x51
 356
 357   ## The base address and size of the TDX Cfv base and size.
 358   gUefiOvmfPkgTokenSpaceGuid.PcdCfvBase|0|UINT32|0x52
 359   gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataOffset|0|UINT32|0x53
 360   gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataSize|0|UINT32|0x54
 361
 362   ## The base address and size of the TDX Bfv base and size.
 363   gUefiOvmfPkgTokenSpaceGuid.PcdBfvBase|0|UINT32|0x55
 364   gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataOffset|0|UINT32|0x56
 365   gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataSize|0|UINT32|0x57
 366
 367   ## The base address and size of the SEV-SNP Secrets Area that contains
 368   #  the VM platform communication key used to send and recieve the
 369   #  messages to the PSP. If this is set in the .fdf, the platform
 370   #  is responsible to reserve this area from DXE phase overwrites.
 371   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSnpSecretsBase|0|UINT32|0x58
 372   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSnpSecretsSize|0|UINT32|0x59
 373
 374   ## The base address and size of a CPUID Area that contains the hypervisor
 375   #  provided CPUID results. In the case of SEV-SNP, the CPUID results are
 376   #  filtered by the SEV-SNP firmware. If this is set in the .fdf, the
 377   #  platform is responsible to reserve this area from DXE phase overwrites.
 378   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase|0|UINT32|0x60
 379   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize|0|UINT32|0x61
 380
 381   ## The range of memory that is validated by the SEC phase.
 382   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecValidatedStart|0|UINT32|0x62
 383   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecValidatedEnd|0|UINT32|0x63
 384
 385   ## The Tdx accept page size. 0x1000(4k),0x200000(2M)
 386   gUefiOvmfPkgTokenSpaceGuid.PcdTdxAcceptPageSize|0x200000|UINT32|0x65
 387
 388 [PcdsDynamic, PcdsDynamicEx]
 389   gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2
 390   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10
 391   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0|UINT16|0x1b
 392   gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE|BOOLEAN|0x21
 393
 394   ## The IO port aperture shared by all PCI root bridges.
 395   #
 396   gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22
 397   gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23
 398
 399   ## The 32-bit MMIO aperture shared by all PCI root bridges.
 400   #
 401   gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24
 402   gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25
 403
 404   ## The 64-bit MMIO aperture shared by all PCI root bridges.
 405   #
 406   gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26
 407   gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27
 408
 409   ## The following setting controls how many megabytes we configure as TSEG on
 410   #  Q35, for SMRAM purposes. Permitted defaults are: 1, 2, 8. Other defaults
 411   #  cause undefined behavior. During boot, the PCD is updated by PlatformPei
 412   #  to reflect the extended TSEG size, if one is advertized by QEMU.
 413   #
 414   #  This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).
 415   gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20
 416
 417   ## Set to TRUE by PlatformPei if the Q35 board supports the "SMRAM at default
 418   #  SMBASE" feature.
 419   #
 420   #  This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).
 421   gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase|FALSE|BOOLEAN|0x34
 422
 423   ## This PCD adds a communication channel between OVMF's SmmCpuFeaturesLib
 424   #  instance in PiSmmCpuDxeSmm, and CpuHotplugSmm.
 425   gUefiOvmfPkgTokenSpaceGuid.PcdCpuHotEjectDataAddress|0|UINT64|0x46
 426
 427   ## This PCD tracks where PcdVideo{Horizontal,Vertical}Resolution
 428   #  values are coming from.
 429   #    0 - unset (defaults from platform dsc)
 430   #    1 - set from PlatformConfig
 431   #    2 - set by GOP Driver.
 432   gUefiOvmfPkgTokenSpaceGuid.PcdVideoResolutionSource|0|UINT8|0x64
 433
 434 [PcdsFeatureFlag]
 435   gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c
 436   gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN|0x1d
 437
 438   ## This feature flag enables SMM/SMRAM support. Note that it also requires
 439   #  such support from the underlying QEMU instance; if that support is not
 440   #  present, the firmware will reject continuing after a certain point.
 441   #
 442   #  The flag also acts as a general "security switch"; when TRUE, many
 443   #  components will change behavior, with the goal of preventing a malicious
 444   #  runtime OS from tampering with firmware structures (special memory ranges
 445   #  used by OVMF, the varstore pflash chip, LockBox etc).
 446   gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire|FALSE|BOOLEAN|0x1e
 447
 448   ## Informs modules (including pre-DXE-phase modules) whether the platform
 449   #  firmware contains a CSM (Compatibility Support Module).
 450   #
 451   gUefiOvmfPkgTokenSpaceGuid.PcdCsmEnable|FALSE|BOOLEAN|0x35