2 Memory Detection for Virtual Machines.
4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
14 // The package level header files this module uses
16 #include <IndustryStandard/E820.h>
17 #include <IndustryStandard/Q35MchIch9.h>
21 // The Library classes this module consumes
23 #include <Library/BaseLib.h>
24 #include <Library/BaseMemoryLib.h>
25 #include <Library/DebugLib.h>
26 #include <Library/HobLib.h>
27 #include <Library/IoLib.h>
28 #include <Library/PcdLib.h>
29 #include <Library/PciLib.h>
30 #include <Library/PeimEntryPoint.h>
31 #include <Library/ResourcePublicationLib.h>
32 #include <Library/MtrrLib.h>
33 #include <Library/QemuFwCfgLib.h>
38 UINT8 mPhysMemAddressWidth
;
40 STATIC UINT32 mS3AcpiReservedMemoryBase
;
41 STATIC UINT32 mS3AcpiReservedMemorySize
;
43 STATIC UINT16 mQ35TsegMbytes
;
46 Q35TsegMbytesInitialization (
50 UINT16 ExtendedTsegMbytes
;
51 RETURN_STATUS PcdStatus
;
53 if (mHostBridgeDevId
!= INTEL_Q35_MCH_DEVICE_ID
) {
56 "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "
57 "only DID=0x%04x (Q35) is supported\n",
60 INTEL_Q35_MCH_DEVICE_ID
67 // Check if QEMU offers an extended TSEG.
69 // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB
70 // register, and reading back the register.
72 // On a QEMU machine type that does not offer an extended TSEG, the initial
73 // write overwrites whatever value a malicious guest OS may have placed in
74 // the (unimplemented) register, before entering S3 or rebooting.
75 // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.
77 // On a QEMU machine type that offers an extended TSEG, the initial write
78 // triggers an update to the register. Subsequently, the value read back
79 // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the
80 // number of megabytes.
82 PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB
), MCH_EXT_TSEG_MB_QUERY
);
83 ExtendedTsegMbytes
= PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB
));
84 if (ExtendedTsegMbytes
== MCH_EXT_TSEG_MB_QUERY
) {
85 mQ35TsegMbytes
= PcdGet16 (PcdQ35TsegMbytes
);
91 "%a: QEMU offers an extended TSEG (%d MB)\n",
95 PcdStatus
= PcdSet16S (PcdQ35TsegMbytes
, ExtendedTsegMbytes
);
96 ASSERT_RETURN_ERROR (PcdStatus
);
97 mQ35TsegMbytes
= ExtendedTsegMbytes
;
102 Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside
103 of the 32-bit address range.
105 Find the highest exclusive >=4GB RAM address, or produce memory resource
106 descriptor HOBs for RAM entries that start at or above 4GB.
108 @param[out] MaxAddress If MaxAddress is NULL, then ScanOrAdd64BitE820Ram()
109 produces memory resource descriptor HOBs for RAM
110 entries that start at or above 4GB.
112 Otherwise, MaxAddress holds the highest exclusive
113 >=4GB RAM address on output. If QEMU's fw_cfg E820
114 RAM map contains no RAM entry that starts outside of
115 the 32-bit address range, then MaxAddress is exactly
118 @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and processed.
120 @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a
121 whole multiple of sizeof(EFI_E820_ENTRY64). No
122 RAM entry was processed.
124 @return Error codes from QemuFwCfgFindFile(). No RAM
129 ScanOrAdd64BitE820Ram (
130 OUT UINT64
*MaxAddress OPTIONAL
134 FIRMWARE_CONFIG_ITEM FwCfgItem
;
136 EFI_E820_ENTRY64 E820Entry
;
139 Status
= QemuFwCfgFindFile ("etc/e820", &FwCfgItem
, &FwCfgSize
);
140 if (EFI_ERROR (Status
)) {
143 if (FwCfgSize
% sizeof E820Entry
!= 0) {
144 return EFI_PROTOCOL_ERROR
;
147 if (MaxAddress
!= NULL
) {
148 *MaxAddress
= BASE_4GB
;
151 QemuFwCfgSelectItem (FwCfgItem
);
152 for (Processed
= 0; Processed
< FwCfgSize
; Processed
+= sizeof E820Entry
) {
153 QemuFwCfgReadBytes (sizeof E820Entry
, &E820Entry
);
156 "%a: Base=0x%Lx Length=0x%Lx Type=%u\n",
162 if (E820Entry
.Type
== EfiAcpiAddressRangeMemory
&&
163 E820Entry
.BaseAddr
>= BASE_4GB
) {
164 if (MaxAddress
== NULL
) {
169 // Round up the start address, and round down the end address.
171 Base
= ALIGN_VALUE (E820Entry
.BaseAddr
, (UINT64
)EFI_PAGE_SIZE
);
172 End
= (E820Entry
.BaseAddr
+ E820Entry
.Length
) &
173 ~(UINT64
)EFI_PAGE_MASK
;
175 AddMemoryRangeHob (Base
, End
);
178 "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n",
187 Candidate
= E820Entry
.BaseAddr
+ E820Entry
.Length
;
188 if (Candidate
> *MaxAddress
) {
189 *MaxAddress
= Candidate
;
192 "%a: MaxAddress=0x%Lx\n",
205 GetSystemMemorySizeBelow4gb (
213 // CMOS 0x34/0x35 specifies the system memory above 16 MB.
214 // * CMOS(0x35) is the high byte
215 // * CMOS(0x34) is the low byte
216 // * The size is specified in 64kb chunks
217 // * Since this is memory above 16MB, the 16MB must be added
218 // into the calculation to get the total memory size.
221 Cmos0x34
= (UINT8
) CmosRead8 (0x34);
222 Cmos0x35
= (UINT8
) CmosRead8 (0x35);
224 return (UINT32
) (((UINTN
)((Cmos0x35
<< 8) + Cmos0x34
) << 16) + SIZE_16MB
);
230 GetSystemMemorySizeAbove4gb (
237 // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
238 // * CMOS(0x5d) is the most significant size byte
239 // * CMOS(0x5c) is the middle size byte
240 // * CMOS(0x5b) is the least significant size byte
241 // * The size is specified in 64kb chunks
245 for (CmosIndex
= 0x5d; CmosIndex
>= 0x5b; CmosIndex
--) {
246 Size
= (UINT32
) (Size
<< 8) + (UINT32
) CmosRead8 (CmosIndex
);
249 return LShiftU64 (Size
, 16);
254 Return the highest address that DXE could possibly use, plus one.
262 UINT64 FirstNonAddress
;
263 UINT64 Pci64Base
, Pci64Size
;
264 CHAR8 MbString
[7 + 1];
266 FIRMWARE_CONFIG_ITEM FwCfgItem
;
268 UINT64 HotPlugMemoryEnd
;
269 RETURN_STATUS PcdStatus
;
272 // set FirstNonAddress to suppress incorrect compiler/analyzer warnings
277 // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM
278 // address from it. This can express an address >= 4GB+1TB.
280 // Otherwise, get the flat size of the memory above 4GB from the CMOS (which
281 // can only express a size smaller than 1TB), and add it to 4GB.
283 Status
= ScanOrAdd64BitE820Ram (&FirstNonAddress
);
284 if (EFI_ERROR (Status
)) {
285 FirstNonAddress
= BASE_4GB
+ GetSystemMemorySizeAbove4gb ();
289 // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO
290 // resources to 32-bit anyway. See DegradeResource() in
291 // "PciResourceSupport.c".
294 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode
)) {
295 return FirstNonAddress
;
300 // Otherwise, in order to calculate the highest address plus one, we must
301 // consider the 64-bit PCI host aperture too. Fetch the default size.
303 Pci64Size
= PcdGet64 (PcdPciMmio64Size
);
306 // See if the user specified the number of megabytes for the 64-bit PCI host
307 // aperture. The number of non-NUL characters in MbString allows for
308 // 9,999,999 MB, which is approximately 10 TB.
310 // As signaled by the "X-" prefix, this knob is experimental, and might go
313 Status
= QemuFwCfgFindFile ("opt/ovmf/X-PciMmio64Mb", &FwCfgItem
,
315 if (!EFI_ERROR (Status
)) {
316 if (FwCfgSize
>= sizeof MbString
) {
318 "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",
321 QemuFwCfgSelectItem (FwCfgItem
);
322 QemuFwCfgReadBytes (FwCfgSize
, MbString
);
323 MbString
[FwCfgSize
] = '\0';
324 Pci64Size
= LShiftU64 (AsciiStrDecimalToUint64 (MbString
), 20);
328 if (Pci64Size
== 0) {
329 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
330 DEBUG ((EFI_D_INFO
, "%a: disabling 64-bit PCI host aperture\n",
332 PcdStatus
= PcdSet64S (PcdPciMmio64Size
, 0);
333 ASSERT_RETURN_ERROR (PcdStatus
);
337 // There's nothing more to do; the amount of memory above 4GB fully
338 // determines the highest address plus one. The memory hotplug area (see
339 // below) plays no role for the firmware in this case.
341 return FirstNonAddress
;
345 // The "etc/reserved-memory-end" fw_cfg file, when present, contains an
346 // absolute, exclusive end address for the memory hotplug area. This area
347 // starts right at the end of the memory above 4GB. The 64-bit PCI host
348 // aperture must be placed above it.
350 Status
= QemuFwCfgFindFile ("etc/reserved-memory-end", &FwCfgItem
,
352 if (!EFI_ERROR (Status
) && FwCfgSize
== sizeof HotPlugMemoryEnd
) {
353 QemuFwCfgSelectItem (FwCfgItem
);
354 QemuFwCfgReadBytes (FwCfgSize
, &HotPlugMemoryEnd
);
355 DEBUG ((DEBUG_VERBOSE
, "%a: HotPlugMemoryEnd=0x%Lx\n", __FUNCTION__
,
358 ASSERT (HotPlugMemoryEnd
>= FirstNonAddress
);
359 FirstNonAddress
= HotPlugMemoryEnd
;
363 // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so
364 // that the host can map it with 1GB hugepages. Follow suit.
366 Pci64Base
= ALIGN_VALUE (FirstNonAddress
, (UINT64
)SIZE_1GB
);
367 Pci64Size
= ALIGN_VALUE (Pci64Size
, (UINT64
)SIZE_1GB
);
370 // The 64-bit PCI host aperture should also be "naturally" aligned. The
371 // alignment is determined by rounding the size of the aperture down to the
372 // next smaller or equal power of two. That is, align the aperture by the
373 // largest BAR size that can fit into it.
375 Pci64Base
= ALIGN_VALUE (Pci64Base
, GetPowerOfTwo64 (Pci64Size
));
377 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
379 // The core PciHostBridgeDxe driver will automatically add this range to
380 // the GCD memory space map through our PciHostBridgeLib instance; here we
381 // only need to set the PCDs.
383 PcdStatus
= PcdSet64S (PcdPciMmio64Base
, Pci64Base
);
384 ASSERT_RETURN_ERROR (PcdStatus
);
385 PcdStatus
= PcdSet64S (PcdPciMmio64Size
, Pci64Size
);
386 ASSERT_RETURN_ERROR (PcdStatus
);
388 DEBUG ((EFI_D_INFO
, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
389 __FUNCTION__
, Pci64Base
, Pci64Size
));
393 // The useful address space ends with the 64-bit PCI host aperture.
395 FirstNonAddress
= Pci64Base
+ Pci64Size
;
396 return FirstNonAddress
;
401 Initialize the mPhysMemAddressWidth variable, based on guest RAM size.
404 AddressWidthInitialization (
408 UINT64 FirstNonAddress
;
411 // As guest-physical memory size grows, the permanent PEI RAM requirements
412 // are dominated by the identity-mapping page tables built by the DXE IPL.
413 // The DXL IPL keys off of the physical address bits advertized in the CPU
414 // HOB. To conserve memory, we calculate the minimum address width here.
416 FirstNonAddress
= GetFirstNonAddress ();
417 mPhysMemAddressWidth
= (UINT8
)HighBitSet64 (FirstNonAddress
);
420 // If FirstNonAddress is not an integral power of two, then we need an
423 if ((FirstNonAddress
& (FirstNonAddress
- 1)) != 0) {
424 ++mPhysMemAddressWidth
;
428 // The minimum address width is 36 (covers up to and excluding 64 GB, which
429 // is the maximum for Ia32 + PAE). The theoretical architecture maximum for
430 // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
431 // can simply assert that here, since 48 bits are good enough for 256 TB.
433 if (mPhysMemAddressWidth
<= 36) {
434 mPhysMemAddressWidth
= 36;
436 ASSERT (mPhysMemAddressWidth
<= 48);
441 Calculate the cap for the permanent PEI memory.
449 BOOLEAN Page1GSupport
;
457 // If DXE is 32-bit, then just return the traditional 64 MB cap.
460 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode
)) {
466 // Dependent on physical address width, PEI memory allocations can be
467 // dominated by the page tables built for 64-bit DXE. So we key the cap off
468 // of those. The code below is based on CreateIdentityMappingPageTables() in
469 // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".
471 Page1GSupport
= FALSE
;
472 if (PcdGetBool (PcdUse1GPageTable
)) {
473 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
474 if (RegEax
>= 0x80000001) {
475 AsmCpuid (0x80000001, NULL
, NULL
, NULL
, &RegEdx
);
476 if ((RegEdx
& BIT26
) != 0) {
477 Page1GSupport
= TRUE
;
482 if (mPhysMemAddressWidth
<= 39) {
484 PdpEntries
= 1 << (mPhysMemAddressWidth
- 30);
485 ASSERT (PdpEntries
<= 0x200);
487 Pml4Entries
= 1 << (mPhysMemAddressWidth
- 39);
488 ASSERT (Pml4Entries
<= 0x200);
492 TotalPages
= Page1GSupport
? Pml4Entries
+ 1 :
493 (PdpEntries
+ 1) * Pml4Entries
+ 1;
494 ASSERT (TotalPages
<= 0x40201);
497 // Add 64 MB for miscellaneous allocations. Note that for
498 // mPhysMemAddressWidth values close to 36, the cap will actually be
499 // dominated by this increment.
501 return (UINT32
)(EFI_PAGES_TO_SIZE (TotalPages
) + SIZE_64MB
);
506 Publish PEI core memory
508 @return EFI_SUCCESS The PEIM initialized successfully.
517 EFI_PHYSICAL_ADDRESS MemoryBase
;
519 UINT32 LowerMemorySize
;
522 LowerMemorySize
= GetSystemMemorySizeBelow4gb ();
523 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
525 // TSEG is chipped from the end of low RAM
527 LowerMemorySize
-= mQ35TsegMbytes
* SIZE_1MB
;
531 // If S3 is supported, then the S3 permanent PEI memory is placed next,
532 // downwards. Its size is primarily dictated by CpuMpPei. The formula below
533 // is an approximation.
536 mS3AcpiReservedMemorySize
= SIZE_512KB
+
538 PcdGet32 (PcdCpuApStackSize
);
539 mS3AcpiReservedMemoryBase
= LowerMemorySize
- mS3AcpiReservedMemorySize
;
540 LowerMemorySize
= mS3AcpiReservedMemoryBase
;
543 if (mBootMode
== BOOT_ON_S3_RESUME
) {
544 MemoryBase
= mS3AcpiReservedMemoryBase
;
545 MemorySize
= mS3AcpiReservedMemorySize
;
547 PeiMemoryCap
= GetPeiMemoryCap ();
548 DEBUG ((EFI_D_INFO
, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
549 __FUNCTION__
, mPhysMemAddressWidth
, PeiMemoryCap
>> 10));
552 // Determine the range of memory to use during PEI
554 // Technically we could lay the permanent PEI RAM over SEC's temporary
555 // decompression and scratch buffer even if "secure S3" is needed, since
556 // their lifetimes don't overlap. However, PeiFvInitialization() will cover
557 // RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory
558 // allocation HOB, and other allocations served from the permanent PEI RAM
559 // shouldn't overlap with that HOB.
561 MemoryBase
= mS3Supported
&& FeaturePcdGet (PcdSmmSmramRequire
) ?
562 PcdGet32 (PcdOvmfDecompressionScratchEnd
) :
563 PcdGet32 (PcdOvmfDxeMemFvBase
) + PcdGet32 (PcdOvmfDxeMemFvSize
);
564 MemorySize
= LowerMemorySize
- MemoryBase
;
565 if (MemorySize
> PeiMemoryCap
) {
566 MemoryBase
= LowerMemorySize
- PeiMemoryCap
;
567 MemorySize
= PeiMemoryCap
;
572 // Publish this memory to the PEI Core
574 Status
= PublishSystemMemory(MemoryBase
, MemorySize
);
575 ASSERT_EFI_ERROR (Status
);
582 Peform Memory Detection for QEMU / KVM
591 UINT64 LowerMemorySize
;
592 UINT64 UpperMemorySize
;
593 MTRR_SETTINGS MtrrSettings
;
596 DEBUG ((EFI_D_INFO
, "%a called\n", __FUNCTION__
));
599 // Determine total memory size available
601 LowerMemorySize
= GetSystemMemorySizeBelow4gb ();
602 UpperMemorySize
= GetSystemMemorySizeAbove4gb ();
604 if (mBootMode
== BOOT_ON_S3_RESUME
) {
606 // Create the following memory HOB as an exception on the S3 boot path.
608 // Normally we'd create memory HOBs only on the normal boot path. However,
609 // CpuMpPei specifically needs such a low-memory HOB on the S3 path as
610 // well, for "borrowing" a subset of it temporarily, for the AP startup
613 // CpuMpPei saves the original contents of the borrowed area in permanent
614 // PEI RAM, in a backup buffer allocated with the normal PEI services.
615 // CpuMpPei restores the original contents ("returns" the borrowed area) at
616 // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before
617 // transferring control to the OS's wakeup vector in the FACS.
619 // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to
620 // restore the original contents. Furthermore, we expect all such PEIMs
621 // (CpuMpPei included) to claim the borrowed areas by producing memory
622 // allocation HOBs, and to honor preexistent memory allocation HOBs when
623 // looking for an area to borrow.
625 AddMemoryRangeHob (0, BASE_512KB
+ BASE_128KB
);
628 // Create memory HOBs
630 AddMemoryRangeHob (0, BASE_512KB
+ BASE_128KB
);
632 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
635 TsegSize
= mQ35TsegMbytes
* SIZE_1MB
;
636 AddMemoryRangeHob (BASE_1MB
, LowerMemorySize
- TsegSize
);
637 AddReservedMemoryBaseSizeHob (LowerMemorySize
- TsegSize
, TsegSize
,
640 AddMemoryRangeHob (BASE_1MB
, LowerMemorySize
);
644 // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM
645 // entries. Otherwise, create a single memory HOB with the flat >=4GB
646 // memory size read from the CMOS.
648 Status
= ScanOrAdd64BitE820Ram (NULL
);
649 if (EFI_ERROR (Status
) && UpperMemorySize
!= 0) {
650 AddMemoryBaseSizeHob (BASE_4GB
, UpperMemorySize
);
655 // We'd like to keep the following ranges uncached:
657 // - [LowerMemorySize, 4 GB)
659 // Everything else should be WB. Unfortunately, programming the inverse (ie.
660 // keeping the default UC, and configuring the complement set of the above as
661 // WB) is not reliable in general, because the end of the upper RAM can have
662 // practically any alignment, and we may not have enough variable MTRRs to
665 if (IsMtrrSupported ()) {
666 MtrrGetAllMtrrs (&MtrrSettings
);
669 // MTRRs disabled, fixed MTRRs disabled, default type is uncached
671 ASSERT ((MtrrSettings
.MtrrDefType
& BIT11
) == 0);
672 ASSERT ((MtrrSettings
.MtrrDefType
& BIT10
) == 0);
673 ASSERT ((MtrrSettings
.MtrrDefType
& 0xFF) == 0);
676 // flip default type to writeback
678 SetMem (&MtrrSettings
.Fixed
, sizeof MtrrSettings
.Fixed
, 0x06);
679 ZeroMem (&MtrrSettings
.Variables
, sizeof MtrrSettings
.Variables
);
680 MtrrSettings
.MtrrDefType
|= BIT11
| BIT10
| 6;
681 MtrrSetAllMtrrs (&MtrrSettings
);
684 // Set memory range from 640KB to 1MB to uncacheable
686 Status
= MtrrSetMemoryAttribute (BASE_512KB
+ BASE_128KB
,
687 BASE_1MB
- (BASE_512KB
+ BASE_128KB
), CacheUncacheable
);
688 ASSERT_EFI_ERROR (Status
);
691 // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB as
694 Status
= MtrrSetMemoryAttribute (LowerMemorySize
,
695 SIZE_4GB
- LowerMemorySize
, CacheUncacheable
);
696 ASSERT_EFI_ERROR (Status
);
701 Publish system RAM and reserve memory regions
705 InitializeRamRegions (
710 QemuInitializeRam ();
712 XenPublishRamRegions ();
715 if (mS3Supported
&& mBootMode
!= BOOT_ON_S3_RESUME
) {
717 // This is the memory range that will be used for PEI on S3 resume
719 BuildMemoryAllocationHob (
720 mS3AcpiReservedMemoryBase
,
721 mS3AcpiReservedMemorySize
,
726 // Cover the initial RAM area used as stack and temporary PEI heap.
728 // This is reserved as ACPI NVS so it can be used on S3 resume.
730 BuildMemoryAllocationHob (
731 PcdGet32 (PcdOvmfSecPeiTempRamBase
),
732 PcdGet32 (PcdOvmfSecPeiTempRamSize
),
737 // SEC stores its table of GUIDed section handlers here.
739 BuildMemoryAllocationHob (
740 PcdGet64 (PcdGuidedExtractHandlerTableAddress
),
741 PcdGet32 (PcdGuidedExtractHandlerTableSize
),
747 // Reserve the initial page tables built by the reset vector code.
749 // Since this memory range will be used by the Reset Vector on S3
750 // resume, it must be reserved as ACPI NVS.
752 BuildMemoryAllocationHob (
753 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfSecPageTablesBase
),
754 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfSecPageTablesSize
),
760 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
761 if (!FeaturePcdGet (PcdSmmSmramRequire
)) {
763 // Reserve the lock box storage area
765 // Since this memory range will be used on S3 resume, it must be
766 // reserved as ACPI NVS.
768 // If S3 is unsupported, then various drivers might still write to the
769 // LockBox area. We ought to prevent DXE from serving allocation requests
770 // such that they would overlap the LockBox storage.
773 (VOID
*)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageBase
),
774 (UINTN
) PcdGet32 (PcdOvmfLockBoxStorageSize
)
776 BuildMemoryAllocationHob (
777 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageBase
),
778 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageSize
),
779 mS3Supported
? EfiACPIMemoryNVS
: EfiBootServicesData
783 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
787 // Make sure the TSEG area that we reported as a reserved memory resource
788 // cannot be used for reserved memory allocations.
790 TsegSize
= mQ35TsegMbytes
* SIZE_1MB
;
791 BuildMemoryAllocationHob (
792 GetSystemMemorySizeBelow4gb() - TsegSize
,
794 EfiReservedMemoryType