4 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 // The package level header files this module uses
23 // The Library classes this module consumes
25 #include <Library/DebugLib.h>
26 #include <Library/HobLib.h>
27 #include <Library/IoLib.h>
28 #include <Library/MemoryAllocationLib.h>
29 #include <Library/PcdLib.h>
30 #include <Library/PciLib.h>
31 #include <Library/PeimEntryPoint.h>
32 #include <Library/PeiServicesLib.h>
33 #include <Library/ResourcePublicationLib.h>
34 #include <Guid/MemoryTypeInformation.h>
35 #include <Ppi/MasterBootMode.h>
36 #include <IndustryStandard/Pci22.h>
41 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation
[] = {
42 { EfiACPIMemoryNVS
, 0x004 },
43 { EfiACPIReclaimMemory
, 0x008 },
44 { EfiReservedMemoryType
, 0x004 },
45 { EfiRuntimeServicesData
, 0x024 },
46 { EfiRuntimeServicesCode
, 0x030 },
47 { EfiBootServicesCode
, 0x180 },
48 { EfiBootServicesData
, 0xF00 },
49 { EfiMaxMemoryType
, 0x000 }
53 EFI_PEI_PPI_DESCRIPTOR mPpiBootMode
[] = {
55 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
56 &gEfiPeiMasterBootModePpiGuid
,
62 EFI_BOOT_MODE mBootMode
= BOOT_WITH_FULL_CONFIGURATION
;
66 AddIoMemoryBaseSizeHob (
67 EFI_PHYSICAL_ADDRESS MemoryBase
,
71 BuildResourceDescriptorHob (
72 EFI_RESOURCE_MEMORY_MAPPED_IO
,
73 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
74 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
75 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
76 EFI_RESOURCE_ATTRIBUTE_TESTED
,
83 AddReservedMemoryBaseSizeHob (
84 EFI_PHYSICAL_ADDRESS MemoryBase
,
88 BuildResourceDescriptorHob (
89 EFI_RESOURCE_MEMORY_RESERVED
,
90 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
91 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
92 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
93 EFI_RESOURCE_ATTRIBUTE_TESTED
,
100 AddIoMemoryRangeHob (
101 EFI_PHYSICAL_ADDRESS MemoryBase
,
102 EFI_PHYSICAL_ADDRESS MemoryLimit
105 AddIoMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
110 AddMemoryBaseSizeHob (
111 EFI_PHYSICAL_ADDRESS MemoryBase
,
115 BuildResourceDescriptorHob (
116 EFI_RESOURCE_SYSTEM_MEMORY
,
117 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
118 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
119 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
120 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
121 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
122 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
|
123 EFI_RESOURCE_ATTRIBUTE_TESTED
,
132 EFI_PHYSICAL_ADDRESS MemoryBase
,
133 EFI_PHYSICAL_ADDRESS MemoryLimit
136 AddMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
141 AddUntestedMemoryBaseSizeHob (
142 EFI_PHYSICAL_ADDRESS MemoryBase
,
146 BuildResourceDescriptorHob (
147 EFI_RESOURCE_SYSTEM_MEMORY
,
148 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
149 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
150 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
151 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
152 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
153 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
,
161 AddUntestedMemoryRangeHob (
162 EFI_PHYSICAL_ADDRESS MemoryBase
,
163 EFI_PHYSICAL_ADDRESS MemoryLimit
166 AddUntestedMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
170 MemMapInitialization (
175 // Create Memory Type Information HOB
178 &gEfiMemoryTypeInformationGuid
,
179 mDefaultMemoryTypeInformation
,
180 sizeof(mDefaultMemoryTypeInformation
)
184 // Add PCI IO Port space available for PCI resource allocations.
186 BuildResourceDescriptorHob (
188 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
189 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
,
195 // Video memory + Legacy BIOS region
197 AddIoMemoryRangeHob (0x0A0000, BASE_1MB
);
201 TopOfLowRam
= GetSystemMemorySizeBelow4gb ();
204 // address purpose size
205 // ------------ -------- -------------------------
206 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
207 // 0xFC000000 gap 44 MB
208 // 0xFEC00000 IO-APIC 4 KB
209 // 0xFEC01000 gap 1020 KB
210 // 0xFED00000 HPET 1 KB
211 // 0xFED00400 gap 1023 KB
212 // 0xFEE00000 LAPIC 1 MB
214 AddIoMemoryRangeHob (TopOfLowRam
< BASE_2GB
?
215 BASE_2GB
: TopOfLowRam
, 0xFC000000);
216 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB
);
217 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB
);
218 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress
), SIZE_1MB
);
234 // Build the CPU hob with 36-bit addressing and 16-bits of IO space.
236 BuildCpuHob (36, 16);
239 // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for
240 // example by Xen) and skip the setup here. This matches the logic in
241 // AcpiTimerLibConstructor ().
243 if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {
245 // The PEI phase should be exited with fully accessibe PIIX4 IO space:
249 PCI_LIB_ADDRESS (0, 1, 3, 0x40),
251 PcdGet16 (PcdAcpiPmBaseAddress
)
255 // 2. set PCICMD/IOSE
258 PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET
),
259 EFI_PCI_COMMAND_IO_SPACE
263 // 3. set PMREGMISC/PMIOSE
265 PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);
271 BootModeInitialization (
277 if (CmosRead8 (0xF) == 0xFE) {
278 mBootMode
= BOOT_ON_S3_RESUME
;
281 Status
= PeiServicesSetBootMode (mBootMode
);
282 ASSERT_EFI_ERROR (Status
);
284 Status
= PeiServicesInstallPpi (mPpiBootMode
);
285 ASSERT_EFI_ERROR (Status
);
290 ReserveEmuVariableNvStore (
293 EFI_PHYSICAL_ADDRESS VariableStore
;
296 // Allocate storage for NV variables early on so it will be
297 // at a consistent address. Since VM memory is preserved
298 // across reboots, this allows the NV variable storage to survive
302 (EFI_PHYSICAL_ADDRESS
)(UINTN
)
303 AllocateAlignedRuntimePages (
304 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
)),
305 PcdGet32 (PcdFlashNvStorageFtwSpareSize
)
308 "Reserved variable store memory: 0x%lX; size: %dkb\n",
310 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
)) / 1024
312 PcdSet64 (PcdEmuVariableNvStoreReserved
, VariableStore
);
323 DEBUG ((EFI_D_INFO
, "CMOS:\n"));
325 for (Loop
= 0; Loop
< 0x80; Loop
++) {
326 if ((Loop
% 0x10) == 0) {
327 DEBUG ((EFI_D_INFO
, "%02x:", Loop
));
329 DEBUG ((EFI_D_INFO
, " %02x", CmosRead8 (Loop
)));
330 if ((Loop
% 0x10) == 0xf) {
331 DEBUG ((EFI_D_INFO
, "\n"));
338 Perform Platform PEI initialization.
340 @param FileHandle Handle of the file being invoked.
341 @param PeiServices Describes the list of possible PEI Services.
343 @return EFI_SUCCESS The PEIM initialized successfully.
349 IN EFI_PEI_FILE_HANDLE FileHandle
,
350 IN CONST EFI_PEI_SERVICES
**PeiServices
353 DEBUG ((EFI_D_ERROR
, "Platform PEIM Loaded\n"));
359 BootModeInitialization ();
363 InitializeRamRegions ();
366 DEBUG ((EFI_D_INFO
, "Xen was detected\n"));
370 ReserveEmuVariableNvStore ();
372 PeiFvInitialization ();
374 MemMapInitialization ();
376 MiscInitialization ();