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1 /**@file
2 Platform PEI driver
3
4 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 //
16 // The package level header files this module uses
17 //
18 #include <PiPei.h>
19
20 //
21 // The Library classes this module consumes
22 //
23 #include <Library/DebugLib.h>
24 #include <Library/HobLib.h>
25 #include <Library/IoLib.h>
26 #include <Library/MemoryAllocationLib.h>
27 #include <Library/PcdLib.h>
28 #include <Library/PciLib.h>
29 #include <Library/PeimEntryPoint.h>
30 #include <Library/ResourcePublicationLib.h>
31 #include <Guid/MemoryTypeInformation.h>
32
33 #include "Platform.h"
34 #include "Cmos.h"
35
36 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
37 { EfiACPIMemoryNVS, 0x004 },
38 { EfiACPIReclaimMemory, 0x008 },
39 { EfiReservedMemoryType, 0x004 },
40 { EfiRuntimeServicesData, 0x024 },
41 { EfiRuntimeServicesCode, 0x030 },
42 { EfiBootServicesCode, 0x180 },
43 { EfiBootServicesData, 0xF00 },
44 { EfiMaxMemoryType, 0x000 }
45 };
46
47
48 VOID
49 AddIoMemoryBaseSizeHob (
50 EFI_PHYSICAL_ADDRESS MemoryBase,
51 UINT64 MemorySize
52 )
53 {
54 BuildResourceDescriptorHob (
55 EFI_RESOURCE_MEMORY_MAPPED_IO,
56 EFI_RESOURCE_ATTRIBUTE_PRESENT |
57 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
58 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
59 EFI_RESOURCE_ATTRIBUTE_TESTED,
60 MemoryBase,
61 MemorySize
62 );
63 }
64
65
66 VOID
67 AddIoMemoryRangeHob (
68 EFI_PHYSICAL_ADDRESS MemoryBase,
69 EFI_PHYSICAL_ADDRESS MemoryLimit
70 )
71 {
72 AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
73 }
74
75
76 VOID
77 AddMemoryBaseSizeHob (
78 EFI_PHYSICAL_ADDRESS MemoryBase,
79 UINT64 MemorySize
80 )
81 {
82 BuildResourceDescriptorHob (
83 EFI_RESOURCE_SYSTEM_MEMORY,
84 EFI_RESOURCE_ATTRIBUTE_PRESENT |
85 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
86 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
87 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
88 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
89 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
90 EFI_RESOURCE_ATTRIBUTE_TESTED,
91 MemoryBase,
92 MemorySize
93 );
94 }
95
96
97 VOID
98 AddMemoryRangeHob (
99 EFI_PHYSICAL_ADDRESS MemoryBase,
100 EFI_PHYSICAL_ADDRESS MemoryLimit
101 )
102 {
103 AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
104 }
105
106 VOID
107 MemMapInitialization (
108 EFI_PHYSICAL_ADDRESS TopOfMemory
109 )
110 {
111 //
112 // Create Memory Type Information HOB
113 //
114 BuildGuidDataHob (
115 &gEfiMemoryTypeInformationGuid,
116 mDefaultMemoryTypeInformation,
117 sizeof(mDefaultMemoryTypeInformation)
118 );
119
120 //
121 // Add PCI IO Port space available for PCI resource allocations.
122 //
123 BuildResourceDescriptorHob (
124 EFI_RESOURCE_IO,
125 EFI_RESOURCE_ATTRIBUTE_PRESENT |
126 EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
127 0x1000,
128 0xF000
129 );
130
131 //
132 // Add PCI MMIO space available to PCI resource allocations
133 //
134 if (TopOfMemory < BASE_2GB) {
135 AddIoMemoryBaseSizeHob (BASE_2GB, 0xFEC00000 - BASE_2GB);
136 } else {
137 AddIoMemoryBaseSizeHob (TopOfMemory, 0xFEC00000 - TopOfMemory);
138 }
139
140 //
141 // Local APIC range
142 //
143 AddIoMemoryBaseSizeHob (0xFEC80000, SIZE_512KB);
144
145 //
146 // I/O APIC range
147 //
148 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_512KB);
149
150 //
151 // Video memory + Legacy BIOS region
152 //
153 AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
154 }
155
156
157 VOID
158 MiscInitialization (
159 )
160 {
161 //
162 // Disable A20 Mask
163 //
164 IoOr8 (0x92, BIT1);
165
166 //
167 // Build the CPU hob with 36-bit addressing and 16-bits of IO space.
168 //
169 BuildCpuHob (36, 16);
170
171 //
172 // Set the PM I/O base address to 0x400
173 //
174 PciAndThenOr32 (PCI_LIB_ADDRESS (0, 1, 3, 0x40), (UINT32) ~0xfc0, 0x400);
175 }
176
177
178 VOID
179 ReserveEmuVariableNvStore (
180 )
181 {
182 EFI_PHYSICAL_ADDRESS VariableStore;
183
184 //
185 // Allocate storage for NV variables early on so it will be
186 // at a consistent address. Since VM memory is preserved
187 // across reboots, this allows the NV variable storage to survive
188 // a VM reboot.
189 //
190 VariableStore =
191 (EFI_PHYSICAL_ADDRESS)(UINTN)
192 AllocateRuntimePool (
193 2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)
194 );
195 DEBUG ((EFI_D_INFO,
196 "Reserved variable store memory: 0x%lX; size: %dkb\n",
197 VariableStore,
198 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
199 ));
200 PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);
201 }
202
203
204 VOID
205 DebugDumpCmos (
206 VOID
207 )
208 {
209 UINTN Loop;
210
211 DEBUG ((EFI_D_INFO, "CMOS:\n"));
212
213 for (Loop = 0; Loop < 0x80; Loop++) {
214 if ((Loop % 0x10) == 0) {
215 DEBUG ((EFI_D_INFO, "%02x:", Loop));
216 }
217 DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
218 if ((Loop % 0x10) == 0xf) {
219 DEBUG ((EFI_D_INFO, "\n"));
220 }
221 }
222 }
223
224
225 /**
226 Perform Platform PEI initialization.
227
228 @param FileHandle Handle of the file being invoked.
229 @param PeiServices Describes the list of possible PEI Services.
230
231 @return EFI_SUCCESS The PEIM initialized successfully.
232
233 **/
234 EFI_STATUS
235 EFIAPI
236 InitializePlatform (
237 IN EFI_PEI_FILE_HANDLE FileHandle,
238 IN CONST EFI_PEI_SERVICES **PeiServices
239 )
240 {
241 EFI_PHYSICAL_ADDRESS TopOfMemory;
242
243 DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
244
245 DebugDumpCmos ();
246
247 TopOfMemory = MemDetect ();
248
249 ReserveEmuVariableNvStore ();
250
251 PeiFvInitialization ();
252
253 MemMapInitialization (TopOfMemory);
254
255 MiscInitialization ();
256
257 return EFI_SUCCESS;
258 }