OvmfPkg/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 //
  18 // The package level header files this module uses
  19 //
  20 #include <PiPei.h>
  21
  22 //
  23 // The Library classes this module consumes
  24 //
  25 #include <Library/DebugLib.h>
  26 #include <Library/HobLib.h>
  27 #include <Library/IoLib.h>
  28 #include <Library/MemoryAllocationLib.h>
  29 #include <Library/PcdLib.h>
  30 #include <Library/PciLib.h>
  31 #include <Library/PeimEntryPoint.h>
  32 #include <Library/PeiServicesLib.h>
  33 #include <Library/QemuFwCfgLib.h>
  34 #include <Library/ResourcePublicationLib.h>
  35 #include <Library/BaseMemoryLib.h>
  36 #include <Guid/MemoryTypeInformation.h>
  37 #include <Ppi/MasterBootMode.h>
  38 #include <IndustryStandard/Pci22.h>
  39 #include <IndustryStandard/SmBios.h>
  40 #include <OvmfPlatforms.h>
  41
  42 #include "Platform.h"
  43 #include "Cmos.h"
  44
  45 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  46   { EfiACPIMemoryNVS,       0x004 },
  47   { EfiACPIReclaimMemory,   0x008 },
  48   { EfiReservedMemoryType,  0x004 },
  49   { EfiRuntimeServicesData, 0x024 },
  50   { EfiRuntimeServicesCode, 0x030 },
  51   { EfiBootServicesCode,    0x180 },
  52   { EfiBootServicesData,    0xF00 },
  53   { EfiMaxMemoryType,       0x000 }
  54 };
  55
  56
  57 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  58   {
  59     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  60     &gEfiPeiMasterBootModePpiGuid,
  61     NULL
  62   }
  63 };
  64
  65
  66 UINT16 mHostBridgeDevId;
  67
  68 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  69
  70 BOOLEAN mS3Supported = FALSE;
  71
  72
  73 VOID
  74 AddIoMemoryBaseSizeHob (
  75   EFI_PHYSICAL_ADDRESS        MemoryBase,
  76   UINT64                      MemorySize
  77   )
  78 {
  79   BuildResourceDescriptorHob (
  80     EFI_RESOURCE_MEMORY_MAPPED_IO,
  81       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  82       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  83       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  84       EFI_RESOURCE_ATTRIBUTE_TESTED,
  85     MemoryBase,
  86     MemorySize
  87     );
  88 }
  89
  90 VOID
  91 AddReservedMemoryBaseSizeHob (
  92   EFI_PHYSICAL_ADDRESS        MemoryBase,
  93   UINT64                      MemorySize
  94   )
  95 {
  96   BuildResourceDescriptorHob (
  97     EFI_RESOURCE_MEMORY_RESERVED,
  98       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  99       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 100       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 101       EFI_RESOURCE_ATTRIBUTE_TESTED,
 102     MemoryBase,
 103     MemorySize
 104     );
 105 }
 106
 107 VOID
 108 AddIoMemoryRangeHob (
 109   EFI_PHYSICAL_ADDRESS        MemoryBase,
 110   EFI_PHYSICAL_ADDRESS        MemoryLimit
 111   )
 112 {
 113   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 114 }
 115
 116
 117 VOID
 118 AddMemoryBaseSizeHob (
 119   EFI_PHYSICAL_ADDRESS        MemoryBase,
 120   UINT64                      MemorySize
 121   )
 122 {
 123   BuildResourceDescriptorHob (
 124     EFI_RESOURCE_SYSTEM_MEMORY,
 125       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 126       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 127       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 128       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 129       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 130       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 131       EFI_RESOURCE_ATTRIBUTE_TESTED,
 132     MemoryBase,
 133     MemorySize
 134     );
 135 }
 136
 137
 138 VOID
 139 AddMemoryRangeHob (
 140   EFI_PHYSICAL_ADDRESS        MemoryBase,
 141   EFI_PHYSICAL_ADDRESS        MemoryLimit
 142   )
 143 {
 144   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 145 }
 146
 147
 148 VOID
 149 AddUntestedMemoryBaseSizeHob (
 150   EFI_PHYSICAL_ADDRESS        MemoryBase,
 151   UINT64                      MemorySize
 152   )
 153 {
 154   BuildResourceDescriptorHob (
 155     EFI_RESOURCE_SYSTEM_MEMORY,
 156       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 157       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 158       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 159       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 160       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 161       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
 162     MemoryBase,
 163     MemorySize
 164     );
 165 }
 166
 167
 168 VOID
 169 AddUntestedMemoryRangeHob (
 170   EFI_PHYSICAL_ADDRESS        MemoryBase,
 171   EFI_PHYSICAL_ADDRESS        MemoryLimit
 172   )
 173 {
 174   AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 175 }
 176
 177 VOID
 178 MemMapInitialization (
 179   VOID
 180   )
 181 {
 182   //
 183   // Create Memory Type Information HOB
 184   //
 185   BuildGuidDataHob (
 186     &gEfiMemoryTypeInformationGuid,
 187     mDefaultMemoryTypeInformation,
 188     sizeof(mDefaultMemoryTypeInformation)
 189     );
 190
 191   //
 192   // Add PCI IO Port space available for PCI resource allocations.
 193   //
 194   BuildResourceDescriptorHob (
 195     EFI_RESOURCE_IO,
 196     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 197     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 198     0xC000,
 199     0x4000
 200     );
 201
 202   //
 203   // Video memory + Legacy BIOS region
 204   //
 205   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 206
 207   if (!mXen) {
 208     UINT32  TopOfLowRam;
 209     TopOfLowRam = GetSystemMemorySizeBelow4gb ();
 210
 211     //
 212     // address       purpose   size
 213     // ------------  --------  -------------------------
 214     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 215     // 0xFC000000    gap                           44 MB
 216     // 0xFEC00000    IO-APIC                        4 KB
 217     // 0xFEC01000    gap                         1020 KB
 218     // 0xFED00000    HPET                           1 KB
 219     // 0xFED00400    gap                          111 KB
 220     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 221     // 0xFED20000    gap                          896 KB
 222     // 0xFEE00000    LAPIC                          1 MB
 223     //
 224     AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?
 225                          BASE_2GB : TopOfLowRam, 0xFC000000);
 226     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 227     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 228     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 229       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 230     }
 231     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 232   }
 233 }
 234
 235
 236 VOID
 237 MiscInitialization (
 238   VOID
 239   )
 240 {
 241   UINTN  PmCmd;
 242   UINTN  Pmba;
 243   UINTN  AcpiCtlReg;
 244   UINT8  AcpiEnBit;
 245
 246   //
 247   // Disable A20 Mask
 248   //
 249   IoOr8 (0x92, BIT1);
 250
 251   //
 252   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 253   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 254   // S3 resume as well, so we build it unconditionally.)
 255   //
 256   BuildCpuHob (mPhysMemAddressWidth, 16);
 257
 258   //
 259   // Determine platform type and save Host Bridge DID to PCD
 260   //
 261   switch (mHostBridgeDevId) {
 262     case INTEL_82441_DEVICE_ID:
 263       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 264       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 265       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 266       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 267       break;
 268     case INTEL_Q35_MCH_DEVICE_ID:
 269       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 270       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 271       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 272       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 273       break;
 274     default:
 275       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 276         __FUNCTION__, mHostBridgeDevId));
 277       ASSERT (FALSE);
 278       return;
 279   }
 280   PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 281
 282   //
 283   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 284   // has been configured (e.g., by Xen) and skip the setup here.
 285   // This matches the logic in AcpiTimerLibConstructor ().
 286   //
 287   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 288     //
 289     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 290     // 1. set PMBA
 291     //
 292     PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
 293
 294     //
 295     // 2. set PCICMD/IOSE
 296     //
 297     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 298
 299     //
 300     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 301     //
 302     PciOr8 (AcpiCtlReg, AcpiEnBit);
 303   }
 304
 305   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 306     //
 307     // Set Root Complex Register Block BAR
 308     //
 309     PciWrite32 (
 310       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 311       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 312       );
 313   }
 314 }
 315
 316
 317 VOID
 318 BootModeInitialization (
 319   VOID
 320   )
 321 {
 322   EFI_STATUS    Status;
 323
 324   if (CmosRead8 (0xF) == 0xFE) {
 325     mBootMode = BOOT_ON_S3_RESUME;
 326   }
 327
 328   Status = PeiServicesSetBootMode (mBootMode);
 329   ASSERT_EFI_ERROR (Status);
 330
 331   Status = PeiServicesInstallPpi (mPpiBootMode);
 332   ASSERT_EFI_ERROR (Status);
 333 }
 334
 335
 336 VOID
 337 ReserveEmuVariableNvStore (
 338   )
 339 {
 340   EFI_PHYSICAL_ADDRESS VariableStore;
 341
 342   //
 343   // Allocate storage for NV variables early on so it will be
 344   // at a consistent address.  Since VM memory is preserved
 345   // across reboots, this allows the NV variable storage to survive
 346   // a VM reboot.
 347   //
 348   VariableStore =
 349     (EFI_PHYSICAL_ADDRESS)(UINTN)
 350       AllocateAlignedRuntimePages (
 351         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
 352         PcdGet32 (PcdFlashNvStorageFtwSpareSize)
 353         );
 354   DEBUG ((EFI_D_INFO,
 355           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 356           VariableStore,
 357           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 358         ));
 359   PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);
 360 }
 361
 362
 363 VOID
 364 DebugDumpCmos (
 365   VOID
 366   )
 367 {
 368   UINT32 Loop;
 369
 370   DEBUG ((EFI_D_INFO, "CMOS:\n"));
 371
 372   for (Loop = 0; Loop < 0x80; Loop++) {
 373     if ((Loop % 0x10) == 0) {
 374       DEBUG ((EFI_D_INFO, "%02x:", Loop));
 375     }
 376     DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
 377     if ((Loop % 0x10) == 0xf) {
 378       DEBUG ((EFI_D_INFO, "\n"));
 379     }
 380   }
 381 }
 382
 383
 384 /**
 385   Set the SMBIOS entry point version for the generic SmbiosDxe driver.
 386 **/
 387 STATIC
 388 VOID
 389 SmbiosVersionInitialization (
 390   VOID
 391   )
 392 {
 393   FIRMWARE_CONFIG_ITEM     Anchor;
 394   UINTN                    AnchorSize;
 395   SMBIOS_TABLE_ENTRY_POINT QemuAnchor;
 396   UINT16                   SmbiosVersion;
 397
 398   if (RETURN_ERROR (QemuFwCfgFindFile ("etc/smbios/smbios-anchor", &Anchor,
 399                       &AnchorSize)) ||
 400       AnchorSize != sizeof QemuAnchor) {
 401     return;
 402   }
 403
 404   QemuFwCfgSelectItem (Anchor);
 405   QemuFwCfgReadBytes (AnchorSize, &QemuAnchor);
 406   if (CompareMem (QemuAnchor.AnchorString, "_SM_", 4) != 0 ||
 407       CompareMem (QemuAnchor.IntermediateAnchorString, "_DMI_", 5) != 0) {
 408     return;
 409   }
 410
 411   SmbiosVersion = (UINT16)(QemuAnchor.MajorVersion << 8 |
 412                            QemuAnchor.MinorVersion);
 413   DEBUG ((EFI_D_INFO, "%a: SMBIOS version from QEMU: 0x%04x\n", __FUNCTION__,
 414     SmbiosVersion));
 415   PcdSet16 (PcdSmbiosVersion, SmbiosVersion);
 416 }
 417
 418
 419 /**
 420   Perform Platform PEI initialization.
 421
 422   @param  FileHandle      Handle of the file being invoked.
 423   @param  PeiServices     Describes the list of possible PEI Services.
 424
 425   @return EFI_SUCCESS     The PEIM initialized successfully.
 426
 427 **/
 428 EFI_STATUS
 429 EFIAPI
 430 InitializePlatform (
 431   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 432   IN CONST EFI_PEI_SERVICES     **PeiServices
 433   )
 434 {
 435   DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
 436
 437   DebugDumpCmos ();
 438
 439   XenDetect ();
 440
 441   if (QemuFwCfgS3Enabled ()) {
 442     DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
 443     mS3Supported = TRUE;
 444   }
 445
 446   BootModeInitialization ();
 447   AddressWidthInitialization ();
 448
 449   PublishPeiMemory ();
 450
 451   InitializeRamRegions ();
 452
 453   if (mXen) {
 454     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
 455     InitializeXen ();
 456   }
 457
 458   //
 459   // Query Host Bridge DID
 460   //
 461   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 462
 463   if (mBootMode != BOOT_ON_S3_RESUME) {
 464     ReserveEmuVariableNvStore ();
 465
 466     PeiFvInitialization ();
 467
 468     MemMapInitialization ();
 469
 470     SmbiosVersionInitialization ();
 471   }
 472
 473   MiscInitialization ();
 474
 475   return EFI_SUCCESS;
 476 }