OvmfPkg/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 //
  18 // The package level header files this module uses
  19 //
  20 #include <PiPei.h>
  21
  22 //
  23 // The Library classes this module consumes
  24 //
  25 #include <Library/BaseLib.h>
  26 #include <Library/DebugLib.h>
  27 #include <Library/HobLib.h>
  28 #include <Library/IoLib.h>
  29 #include <Library/MemoryAllocationLib.h>
  30 #include <Library/PcdLib.h>
  31 #include <Library/PciLib.h>
  32 #include <Library/PeimEntryPoint.h>
  33 #include <Library/PeiServicesLib.h>
  34 #include <Library/QemuFwCfgLib.h>
  35 #include <Library/ResourcePublicationLib.h>
  36 #include <Guid/MemoryTypeInformation.h>
  37 #include <Ppi/MasterBootMode.h>
  38 #include <IndustryStandard/Pci22.h>
  39 #include <OvmfPlatforms.h>
  40
  41 #include "Platform.h"
  42 #include "Cmos.h"
  43
  44 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  45   { EfiACPIMemoryNVS,       0x004 },
  46   { EfiACPIReclaimMemory,   0x008 },
  47   { EfiReservedMemoryType,  0x004 },
  48   { EfiRuntimeServicesData, 0x024 },
  49   { EfiRuntimeServicesCode, 0x030 },
  50   { EfiBootServicesCode,    0x180 },
  51   { EfiBootServicesData,    0xF00 },
  52   { EfiMaxMemoryType,       0x000 }
  53 };
  54
  55
  56 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  57   {
  58     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  59     &gEfiPeiMasterBootModePpiGuid,
  60     NULL
  61   }
  62 };
  63
  64
  65 UINT16 mHostBridgeDevId;
  66
  67 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  68
  69 BOOLEAN mS3Supported = FALSE;
  70
  71
  72 VOID
  73 AddIoMemoryBaseSizeHob (
  74   EFI_PHYSICAL_ADDRESS        MemoryBase,
  75   UINT64                      MemorySize
  76   )
  77 {
  78   BuildResourceDescriptorHob (
  79     EFI_RESOURCE_MEMORY_MAPPED_IO,
  80       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  81       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  82       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  83       EFI_RESOURCE_ATTRIBUTE_TESTED,
  84     MemoryBase,
  85     MemorySize
  86     );
  87 }
  88
  89 VOID
  90 AddReservedMemoryBaseSizeHob (
  91   EFI_PHYSICAL_ADDRESS        MemoryBase,
  92   UINT64                      MemorySize,
  93   BOOLEAN                     Cacheable
  94   )
  95 {
  96   BuildResourceDescriptorHob (
  97     EFI_RESOURCE_MEMORY_RESERVED,
  98       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  99       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 100       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 101       (Cacheable ?
 102        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 103        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 104        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
 105        0
 106        ) |
 107       EFI_RESOURCE_ATTRIBUTE_TESTED,
 108     MemoryBase,
 109     MemorySize
 110     );
 111 }
 112
 113 VOID
 114 AddIoMemoryRangeHob (
 115   EFI_PHYSICAL_ADDRESS        MemoryBase,
 116   EFI_PHYSICAL_ADDRESS        MemoryLimit
 117   )
 118 {
 119   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 120 }
 121
 122
 123 VOID
 124 AddMemoryBaseSizeHob (
 125   EFI_PHYSICAL_ADDRESS        MemoryBase,
 126   UINT64                      MemorySize
 127   )
 128 {
 129   BuildResourceDescriptorHob (
 130     EFI_RESOURCE_SYSTEM_MEMORY,
 131       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 132       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 133       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 134       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 135       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 136       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 137       EFI_RESOURCE_ATTRIBUTE_TESTED,
 138     MemoryBase,
 139     MemorySize
 140     );
 141 }
 142
 143
 144 VOID
 145 AddMemoryRangeHob (
 146   EFI_PHYSICAL_ADDRESS        MemoryBase,
 147   EFI_PHYSICAL_ADDRESS        MemoryLimit
 148   )
 149 {
 150   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 151 }
 152
 153
 154 VOID
 155 MemMapInitialization (
 156   VOID
 157   )
 158 {
 159   UINT64        PciIoBase;
 160   UINT64        PciIoSize;
 161   RETURN_STATUS PcdStatus;
 162
 163   PciIoBase = 0xC000;
 164   PciIoSize = 0x4000;
 165
 166   //
 167   // Create Memory Type Information HOB
 168   //
 169   BuildGuidDataHob (
 170     &gEfiMemoryTypeInformationGuid,
 171     mDefaultMemoryTypeInformation,
 172     sizeof(mDefaultMemoryTypeInformation)
 173     );
 174
 175   //
 176   // Video memory + Legacy BIOS region
 177   //
 178   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 179
 180   if (!mXen) {
 181     UINT32  TopOfLowRam;
 182     UINT64  PciExBarBase;
 183     UINT32  PciBase;
 184     UINT32  PciSize;
 185
 186     TopOfLowRam = GetSystemMemorySizeBelow4gb ();
 187     PciExBarBase = 0;
 188     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 189       //
 190       // The MMCONFIG area is expected to fall between the top of low RAM and
 191       // the base of the 32-bit PCI host aperture.
 192       //
 193       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
 194       ASSERT (TopOfLowRam <= PciExBarBase);
 195       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
 196       PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
 197     } else {
 198       PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
 199     }
 200
 201     //
 202     // address       purpose   size
 203     // ------------  --------  -------------------------
 204     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 205     // 0xFC000000    gap                           44 MB
 206     // 0xFEC00000    IO-APIC                        4 KB
 207     // 0xFEC01000    gap                         1020 KB
 208     // 0xFED00000    HPET                           1 KB
 209     // 0xFED00400    gap                          111 KB
 210     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 211     // 0xFED20000    gap                          896 KB
 212     // 0xFEE00000    LAPIC                          1 MB
 213     //
 214     PciSize = 0xFC000000 - PciBase;
 215     AddIoMemoryBaseSizeHob (PciBase, PciSize);
 216     PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);
 217     ASSERT_RETURN_ERROR (PcdStatus);
 218     PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);
 219     ASSERT_RETURN_ERROR (PcdStatus);
 220
 221     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 222     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 223     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 224       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 225       //
 226       // Note: there should be an
 227       //
 228       //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
 229       //
 230       // call below, just like the one above for RCBA. However, Linux insists
 231       // that the MMCONFIG area be marked in the E820 or UEFI memory map as
 232       // "reserved memory" -- Linux does not content itself with a simple gap
 233       // in the memory map wherever the MCFG ACPI table points to.
 234       //
 235       // This appears to be a safety measure. The PCI Firmware Specification
 236       // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
 237       // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
 238       // [...]". (Emphasis added here.)
 239       //
 240       // Normally we add memory resource descriptor HOBs in
 241       // QemuInitializeRam(), and pre-allocate from those with memory
 242       // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
 243       // is most definitely not RAM; so, as an exception, cover it with
 244       // uncacheable reserved memory right here.
 245       //
 246       AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
 247       BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
 248         EfiReservedMemoryType);
 249     }
 250     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 251
 252     //
 253     // On Q35, the IO Port space is available for PCI resource allocations from
 254     // 0x6000 up.
 255     //
 256     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 257       PciIoBase = 0x6000;
 258       PciIoSize = 0xA000;
 259       ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
 260     }
 261   }
 262
 263   //
 264   // Add PCI IO Port space available for PCI resource allocations.
 265   //
 266   BuildResourceDescriptorHob (
 267     EFI_RESOURCE_IO,
 268     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 269     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 270     PciIoBase,
 271     PciIoSize
 272     );
 273   PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);
 274   ASSERT_RETURN_ERROR (PcdStatus);
 275   PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);
 276   ASSERT_RETURN_ERROR (PcdStatus);
 277 }
 278
 279 EFI_STATUS
 280 GetNamedFwCfgBoolean (
 281   IN  CHAR8   *FwCfgFileName,
 282   OUT BOOLEAN *Setting
 283   )
 284 {
 285   EFI_STATUS           Status;
 286   FIRMWARE_CONFIG_ITEM FwCfgItem;
 287   UINTN                FwCfgSize;
 288   UINT8                Value[3];
 289
 290   Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);
 291   if (EFI_ERROR (Status)) {
 292     return Status;
 293   }
 294   if (FwCfgSize > sizeof Value) {
 295     return EFI_BAD_BUFFER_SIZE;
 296   }
 297   QemuFwCfgSelectItem (FwCfgItem);
 298   QemuFwCfgReadBytes (FwCfgSize, Value);
 299
 300   if ((FwCfgSize == 1) ||
 301       (FwCfgSize == 2 && Value[1] == '\n') ||
 302       (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {
 303     switch (Value[0]) {
 304       case '0':
 305       case 'n':
 306       case 'N':
 307         *Setting = FALSE;
 308         return EFI_SUCCESS;
 309
 310       case '1':
 311       case 'y':
 312       case 'Y':
 313         *Setting = TRUE;
 314         return EFI_SUCCESS;
 315
 316       default:
 317         break;
 318     }
 319   }
 320   return EFI_PROTOCOL_ERROR;
 321 }
 322
 323 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \
 324           do {                                                      \
 325             BOOLEAN       Setting;                                  \
 326             RETURN_STATUS PcdStatus;                                \
 327                                                                     \
 328             if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \
 329                               "opt/ovmf/" #TokenName, &Setting))) { \
 330               PcdStatus = PcdSetBoolS (TokenName, Setting);         \
 331               ASSERT_RETURN_ERROR (PcdStatus);                      \
 332             }                                                       \
 333           } while (0)
 334
 335 VOID
 336 NoexecDxeInitialization (
 337   VOID
 338   )
 339 {
 340   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);
 341   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);
 342 }
 343
 344 VOID
 345 PciExBarInitialization (
 346   VOID
 347   )
 348 {
 349   union {
 350     UINT64 Uint64;
 351     UINT32 Uint32[2];
 352   } PciExBarBase;
 353
 354   //
 355   // We only support the 256MB size for the MMCONFIG area:
 356   // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
 357   //
 358   // The masks used below enforce the Q35 requirements that the MMCONFIG area
 359   // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
 360   //
 361   // Note that (b) also ensures that the minimum address width we have
 362   // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
 363   // for DXE's page tables to cover the MMCONFIG area.
 364   //
 365   PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
 366   ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
 367   ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
 368
 369   //
 370   // Clear the PCIEXBAREN bit first, before programming the high register.
 371   //
 372   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
 373
 374   //
 375   // Program the high register. Then program the low register, setting the
 376   // MMCONFIG area size and enabling decoding at once.
 377   //
 378   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
 379   PciWrite32 (
 380     DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
 381     PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
 382     );
 383 }
 384
 385 VOID
 386 MiscInitialization (
 387   VOID
 388   )
 389 {
 390   UINTN         PmCmd;
 391   UINTN         Pmba;
 392   UINT32        PmbaAndVal;
 393   UINT32        PmbaOrVal;
 394   UINTN         AcpiCtlReg;
 395   UINT8         AcpiEnBit;
 396   RETURN_STATUS PcdStatus;
 397
 398   //
 399   // Disable A20 Mask
 400   //
 401   IoOr8 (0x92, BIT1);
 402
 403   //
 404   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 405   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 406   // S3 resume as well, so we build it unconditionally.)
 407   //
 408   BuildCpuHob (mPhysMemAddressWidth, 16);
 409
 410   //
 411   // Determine platform type and save Host Bridge DID to PCD
 412   //
 413   switch (mHostBridgeDevId) {
 414     case INTEL_82441_DEVICE_ID:
 415       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 416       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 417       PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
 418       PmbaOrVal  = PIIX4_PMBA_VALUE;
 419       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 420       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 421       break;
 422     case INTEL_Q35_MCH_DEVICE_ID:
 423       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 424       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 425       PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
 426       PmbaOrVal  = ICH9_PMBASE_VALUE;
 427       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 428       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 429       break;
 430     default:
 431       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 432         __FUNCTION__, mHostBridgeDevId));
 433       ASSERT (FALSE);
 434       return;
 435   }
 436   PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 437   ASSERT_RETURN_ERROR (PcdStatus);
 438
 439   //
 440   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 441   // has been configured (e.g., by Xen) and skip the setup here.
 442   // This matches the logic in AcpiTimerLibConstructor ().
 443   //
 444   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 445     //
 446     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 447     // 1. set PMBA
 448     //
 449     PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
 450
 451     //
 452     // 2. set PCICMD/IOSE
 453     //
 454     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 455
 456     //
 457     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 458     //
 459     PciOr8 (AcpiCtlReg, AcpiEnBit);
 460   }
 461
 462   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 463     //
 464     // Set Root Complex Register Block BAR
 465     //
 466     PciWrite32 (
 467       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 468       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 469       );
 470
 471     //
 472     // Set PCI Express Register Range Base Address
 473     //
 474     PciExBarInitialization ();
 475   }
 476 }
 477
 478
 479 VOID
 480 BootModeInitialization (
 481   VOID
 482   )
 483 {
 484   EFI_STATUS    Status;
 485
 486   if (CmosRead8 (0xF) == 0xFE) {
 487     mBootMode = BOOT_ON_S3_RESUME;
 488   }
 489   CmosWrite8 (0xF, 0x00);
 490
 491   Status = PeiServicesSetBootMode (mBootMode);
 492   ASSERT_EFI_ERROR (Status);
 493
 494   Status = PeiServicesInstallPpi (mPpiBootMode);
 495   ASSERT_EFI_ERROR (Status);
 496 }
 497
 498
 499 VOID
 500 ReserveEmuVariableNvStore (
 501   )
 502 {
 503   EFI_PHYSICAL_ADDRESS VariableStore;
 504   RETURN_STATUS        PcdStatus;
 505
 506   //
 507   // Allocate storage for NV variables early on so it will be
 508   // at a consistent address.  Since VM memory is preserved
 509   // across reboots, this allows the NV variable storage to survive
 510   // a VM reboot.
 511   //
 512   VariableStore =
 513     (EFI_PHYSICAL_ADDRESS)(UINTN)
 514       AllocateAlignedRuntimePages (
 515         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
 516         PcdGet32 (PcdFlashNvStorageFtwSpareSize)
 517         );
 518   DEBUG ((EFI_D_INFO,
 519           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 520           VariableStore,
 521           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 522         ));
 523   PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
 524   ASSERT_RETURN_ERROR (PcdStatus);
 525 }
 526
 527
 528 VOID
 529 DebugDumpCmos (
 530   VOID
 531   )
 532 {
 533   UINT32 Loop;
 534
 535   DEBUG ((EFI_D_INFO, "CMOS:\n"));
 536
 537   for (Loop = 0; Loop < 0x80; Loop++) {
 538     if ((Loop % 0x10) == 0) {
 539       DEBUG ((EFI_D_INFO, "%02x:", Loop));
 540     }
 541     DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
 542     if ((Loop % 0x10) == 0xf) {
 543       DEBUG ((EFI_D_INFO, "\n"));
 544     }
 545   }
 546 }
 547
 548
 549 VOID
 550 S3Verification (
 551   VOID
 552   )
 553 {
 554 #if defined (MDE_CPU_X64)
 555   if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
 556     DEBUG ((EFI_D_ERROR,
 557       "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
 558     DEBUG ((EFI_D_ERROR,
 559       "%a: Please disable S3 on the QEMU command line (see the README),\n",
 560       __FUNCTION__));
 561     DEBUG ((EFI_D_ERROR,
 562       "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
 563     ASSERT (FALSE);
 564     CpuDeadLoop ();
 565   }
 566 #endif
 567 }
 568
 569
 570 /**
 571   Perform Platform PEI initialization.
 572
 573   @param  FileHandle      Handle of the file being invoked.
 574   @param  PeiServices     Describes the list of possible PEI Services.
 575
 576   @return EFI_SUCCESS     The PEIM initialized successfully.
 577
 578 **/
 579 EFI_STATUS
 580 EFIAPI
 581 InitializePlatform (
 582   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 583   IN CONST EFI_PEI_SERVICES     **PeiServices
 584   )
 585 {
 586   EFI_STATUS    Status;
 587
 588   DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
 589
 590   DebugDumpCmos ();
 591
 592   XenDetect ();
 593
 594   if (QemuFwCfgS3Enabled ()) {
 595     DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
 596     mS3Supported = TRUE;
 597     Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
 598     ASSERT_EFI_ERROR (Status);
 599   }
 600
 601   S3Verification ();
 602   BootModeInitialization ();
 603   AddressWidthInitialization ();
 604
 605   PublishPeiMemory ();
 606
 607   InitializeRamRegions ();
 608
 609   if (mXen) {
 610     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
 611     InitializeXen ();
 612   }
 613
 614   //
 615   // Query Host Bridge DID
 616   //
 617   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 618
 619   if (mBootMode != BOOT_ON_S3_RESUME) {
 620     ReserveEmuVariableNvStore ();
 621     PeiFvInitialization ();
 622     MemMapInitialization ();
 623     NoexecDxeInitialization ();
 624   }
 625
 626   MiscInitialization ();
 627   InstallFeatureControlCallback ();
 628
 629   return EFI_SUCCESS;
 630 }